* [PATCH v3 0/3] phy: mtk-mipi-csi: add driver for CSI phy
@ 2023-05-24 8:30 Julien Stephan
2023-05-24 8:30 ` [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition Julien Stephan
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Julien Stephan @ 2023-05-24 8:30 UTC (permalink / raw)
Cc: mkorpershoek, khilman, Julien Stephan, Andy Hsieh,
AngeloGioacchino Del Regno, Chunfeng Yun, Chun-Kuang Hu,
Conor Dooley, devicetree, dri-devel, Kishon Vijay Abraham I,
Krzysztof Kozlowski, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-phy, Matthias Brugger, Philipp Zabel,
Rob Herring, Vinod Koul
Adding a new driver for the MIPI CSI CD-PHY module v 0.5 embedded in
some Mediatek soc, such as the MT8365
This driver was adapted from https://patchwork.kernel.org/project/linux-mediatek/cover/20200708104023.3225-1-louis.kuo@mediatek.com/
v1 can be found here: https://lore.kernel.org/all/20230403071929.360911-1-jstephan@baylibre.com/
v2 can be found here: https://lore.kernel.org/all/20230515090551.1251389-1-jstephan@baylibre.com/
Changelog
Changes in v3:
Binding file:
- rename compatible string
mediatek,phy-mipi-csi-0-5 -> mediatek,mt8365-csi-rx
- rename binding file to be as compatible string
- change property mediatek,is_cdphy -> mediatek,phy-type using an
enum value instead of boolean for scalability
- remove status property from example nodes
- rename example node name 'mipi_rx_csi0: mipi_rx_csi0@11c10000' ->
'csi0_rx: phy@11c10000'
- put reg address in lower case
include/dt-bindings/phy/phy.h:
- add PHY_TYPE_CDPHY definition
Driver:
- rename compatible string
- rename property mediatek,is_cdphy -> mediatek,phy-type
- rename CSIx* macro to CSIX* (x -> X)
- fix style issue on the driver data structure
- update MODULE_DESCRIPTION as suggested by Angelo
and update the kconfig module description to match it
- add dphy /cdphy eq tuning function to factor the code
and increase readability
- fix typo __PHY_MTK__MIPI_CSI__C_0_5_RX_REG_H_ -->
__PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H_
- reword commit message to update my contributions
- added missing copyright
- added module name in Kconfig
Changes in v2:
- fix all comments on bindings
- move the binding chunk from driver to binding commit
- fix dt_binding_check error (reported by DT_CHECKER_FLAGS)
- use a more generic compatible string
- add a new dt properties to simplify the driver
"mediatek,is_cdphy"
- rename the driver and the corresponding file to include
version
- drop of_match_ptr()
- use devm_platform_ioremap_resource
- use phy-mtk-io.h api instead of regmap
- rework the driver to use dt nodes to declare PHY instead of an
array in the driver
- remove useless define for unused registers
- remove support for CSI0A/B because it cannot be tested, and it
simplifies the driver for a first review
- edit commit message and bindings to be more descriptive about the
hardware
Florian Sylvestre (1):
dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
Julien Stephan (1):
dt-bindings: phy: add PHY_TYPE_CDPHY definition
Phi-bang Nguyen (1):
phy: mtk-mipi-csi: add driver for CSI phy
.../bindings/phy/mediatek,mt8365-csi-rx.yaml | 68 +++++
MAINTAINERS | 7 +
drivers/phy/mediatek/Kconfig | 8 +
drivers/phy/mediatek/Makefile | 2 +
.../mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h | 58 ++++
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c | 272 ++++++++++++++++++
include/dt-bindings/phy/phy.h | 3 +-
7 files changed, 417 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h
create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
--
2.40.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition
2023-05-24 8:30 [PATCH v3 0/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
@ 2023-05-24 8:30 ` Julien Stephan
2023-05-24 9:45 ` AngeloGioacchino Del Regno
2023-06-03 19:09 ` Krzysztof Kozlowski
2023-05-24 8:30 ` [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 Julien Stephan
2023-05-24 8:30 ` [PATCH v3 3/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
2 siblings, 2 replies; 9+ messages in thread
From: Julien Stephan @ 2023-05-24 8:30 UTC (permalink / raw)
Cc: mkorpershoek, khilman, Julien Stephan, Andy Hsieh,
AngeloGioacchino Del Regno, Chunfeng Yun, Chun-Kuang Hu,
Conor Dooley, devicetree, dri-devel, Kishon Vijay Abraham I,
Krzysztof Kozlowski, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-phy, Matthias Brugger, Philipp Zabel,
Rob Herring, Vinod Koul
Add definition for CDPHY phy type that can be configured in either D-PHY
mode or C-PHY mode
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 6b901b342348..a19d85dbbf16 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -23,5 +23,6 @@
#define PHY_TYPE_DPHY 10
#define PHY_TYPE_CPHY 11
#define PHY_TYPE_USXGMII 12
+#define PHY_TYPE_CDPHY 13
#endif /* _DT_BINDINGS_PHY */
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
2023-05-24 8:30 [PATCH v3 0/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
2023-05-24 8:30 ` [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition Julien Stephan
@ 2023-05-24 8:30 ` Julien Stephan
2023-05-24 9:45 ` AngeloGioacchino Del Regno
2023-05-24 8:30 ` [PATCH v3 3/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
2 siblings, 1 reply; 9+ messages in thread
From: Julien Stephan @ 2023-05-24 8:30 UTC (permalink / raw)
Cc: mkorpershoek, khilman, Florian Sylvestre, Julien Stephan,
Andy Hsieh, AngeloGioacchino Del Regno, Chunfeng Yun,
Chun-Kuang Hu, Conor Dooley, devicetree, dri-devel,
Kishon Vijay Abraham I, Krzysztof Kozlowski, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-phy, Matthias Brugger,
Philipp Zabel, Rob Herring, Vinod Koul
From: Florian Sylvestre <fsylvestre@baylibre.com>
This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in
some Mediatek soc, such as the mt8365
Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
.../bindings/phy/mediatek,mt8365-csi-rx.yaml | 67 +++++++++++++++++++
MAINTAINERS | 6 ++
2 files changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
new file mode 100644
index 000000000000..a1bd96a98051
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 MediaTek, BayLibre
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Sensor Interface MIPI CSI CD-PHY
+
+maintainers:
+ - Julien Stephan <jstephan@baylibre.com>
+ - Andy Hsieh <andy.hsieh@mediatek.com>
+
+description:
+ The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
+ receivers. The number of PHYs depends on the SoC model.
+ Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
+ capable.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8365-csi-rx
+
+ reg:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+ mediatek,phy-type:
+ description:
+ Specify the phy type. Supported phy are D-PHY only or CD-PHY capable phys.
+ See include/dt-bindings/phy/phy.h for constants.
+ enum: [10, 13]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - mediatek,phy-type
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ csi0_rx: phy@11c10000 {
+ compatible = "mediatek,mt8365-csi-rx";
+ reg = <0 0x11c10000 0 0x2000>;
+ mediatek,phy-type = <PHY_TYPE_CDPHY>;
+ #phy-cells = <0>;
+ };
+
+ csi1_rx: phy@11c12000 {
+ compatible = "mediatek,mt8365-csi-rx";
+ reg = <0 0x11c12000 0 0x2000>;
+ mediatek,phy-type = <PHY_TYPE_DPHY>;
+ #phy-cells = <0>;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index b81e9fcc66cb..5da594fbb761 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13184,6 +13184,12 @@ F: Documentation/devicetree/bindings/media/mediatek-vpu.txt
F: drivers/media/platform/mediatek/vcodec/
F: drivers/media/platform/mediatek/vpu/
+MEDIATEK MIPI-CSI CDPHY DRIVER
+M: Julien Stephan <jstephan@baylibre.com>
+M: Andy Hsieh <andy.hsieh@mediatek.com>
+S: Supported
+F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
+
MEDIATEK MMC/SD/SDIO DRIVER
M: Chaotian Jing <chaotian.jing@mediatek.com>
S: Maintained
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] phy: mtk-mipi-csi: add driver for CSI phy
2023-05-24 8:30 [PATCH v3 0/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
2023-05-24 8:30 ` [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition Julien Stephan
2023-05-24 8:30 ` [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 Julien Stephan
@ 2023-05-24 8:30 ` Julien Stephan
2 siblings, 0 replies; 9+ messages in thread
From: Julien Stephan @ 2023-05-24 8:30 UTC (permalink / raw)
Cc: mkorpershoek, khilman, Phi-bang Nguyen, Louis Kuo,
Julien Stephan, Andy Hsieh, AngeloGioacchino Del Regno,
Chunfeng Yun, Chun-Kuang Hu, Conor Dooley, devicetree, dri-devel,
Kishon Vijay Abraham I, Krzysztof Kozlowski, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-phy, Matthias Brugger,
Philipp Zabel, Rob Herring, Vinod Koul
From: Phi-bang Nguyen <pnguyen@baylibre.com>
This is a new driver that supports the MIPI CSI CD-PHY version 0.5
The number of PHYs depend on the SoC.
Each PHY can support D-PHY only or CD-PHY configuration.
The driver supports only D-PHY mode, so CD-PHY
compatible PHY are configured in D-PHY mode.
Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
Signed-off-by: Phi-bang Nguyen <pnguyen@baylibre.com>
[Julien Stephan: refactor code]
[Julien Stephan: simplify driver model: one instance per phy vs one instance
for all phys]
Co-developed-by: Julien Stephan <jstephan@baylibre.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
MAINTAINERS | 1 +
drivers/phy/mediatek/Kconfig | 12 +
drivers/phy/mediatek/Makefile | 2 +
.../mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h | 62 ++++
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c | 278 ++++++++++++++++++
5 files changed, 355 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h
create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 5da594fbb761..e505023ffda1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13189,6 +13189,7 @@ M: Julien Stephan <jstephan@baylibre.com>
M: Andy Hsieh <andy.hsieh@mediatek.com>
S: Supported
F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
+F: drivers/phy/mediatek/phy-mtk-mipi-csi-0-5*
MEDIATEK MMC/SD/SDIO DRIVER
M: Chaotian Jing <chaotian.jing@mediatek.com>
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 3125ecb5d119..7088382ebc9e 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -74,3 +74,15 @@ config PHY_MTK_DP
select GENERIC_PHY
help
Support DisplayPort PHY for MediaTek SoCs.
+
+config PHY_MTK_MIPI_CSI_0_5
+ tristate "MediaTek MIPI CSI CD-PHY v0.5 Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Enable this to support the MIPI CSI CD-PHY receiver version 0.5.
+ The driver supports multiple CSI cdphy ports simultaneously.
+
+ To compile this driver as a module, choose M here: the
+ module will be called phy-mtk-mipi-csi-0-5.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index c9a50395533e..63f2fa3ec7e5 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -19,3 +19,5 @@ phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o
obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi-drv.o
+
+obj-$(CONFIG_PHY_MTK_MIPI_CSI_0_5) += phy-mtk-mipi-csi-0-5.o
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h
new file mode 100644
index 000000000000..97b4c27a1699
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, MediaTek Inc.
+ * Copyright (c) 2023, BayLibre Inc.
+ */
+
+#ifndef __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__
+#define __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__
+
+/*
+ * CSI1 and CSI2 are identical, and similar to CSI0. All CSIX macros are
+ * applicable to the three PHYs. Where differences exist, they are denoted by
+ * macro names using CSI0 and CSI1, the latter being applicable to CSI1 and
+ * CSI2 alike.
+ */
+
+#define MIPI_RX_ANA00_CSIXA 0x0000
+#define RG_CSI0A_CPHY_EN BIT(0)
+#define RG_CSIXA_EQ_PROTECT_EN BIT(1)
+#define RG_CSIXA_BG_LPF_EN BIT(2)
+#define RG_CSIXA_BG_CORE_EN BIT(3)
+#define RG_CSIXA_DPHY_L0_CKMODE_EN BIT(5)
+#define RG_CSIXA_DPHY_L0_CKSEL BIT(6)
+#define RG_CSIXA_DPHY_L1_CKMODE_EN BIT(8)
+#define RG_CSIXA_DPHY_L1_CKSEL BIT(9)
+#define RG_CSIXA_DPHY_L2_CKMODE_EN BIT(11)
+#define RG_CSIXA_DPHY_L2_CKSEL BIT(12)
+
+#define MIPI_RX_ANA18_CSIXA 0x0018
+#define RG_CSI0A_L0_T0AB_EQ_IS GENMASK(5, 4)
+#define RG_CSI0A_L0_T0AB_EQ_BW GENMASK(7, 6)
+#define RG_CSI0A_L1_T1AB_EQ_IS GENMASK(21, 20)
+#define RG_CSI0A_L1_T1AB_EQ_BW GENMASK(23, 22)
+#define RG_CSI0A_L2_T1BC_EQ_IS GENMASK(21, 20)
+#define RG_CSI0A_L2_T1BC_EQ_BW GENMASK(23, 22)
+#define RG_CSI1A_L0_EQ_IS GENMASK(5, 4)
+#define RG_CSI1A_L0_EQ_BW GENMASK(7, 6)
+#define RG_CSI1A_L1_EQ_IS GENMASK(21, 20)
+#define RG_CSI1A_L1_EQ_BW GENMASK(23, 22)
+#define RG_CSI1A_L2_EQ_IS GENMASK(5, 4)
+#define RG_CSI1A_L2_EQ_BW GENMASK(7, 6)
+
+#define MIPI_RX_ANA1C_CSIXA 0x001c
+#define MIPI_RX_ANA20_CSI0A 0x0020
+
+#define MIPI_RX_ANA24_CSIXA 0x0024
+#define RG_CSIXA_RESERVE GENMASK(31, 24)
+
+#define MIPI_RX_ANA40_CSIXA 0x0040
+#define RG_CSIXA_CPHY_FMCK_SEL GENMASK(1, 0)
+#define RG_CSIXA_ASYNC_OPTION GENMASK(7, 4)
+#define RG_CSIXA_CPHY_SPARE GENMASK(31, 16)
+
+#define MIPI_RX_WRAPPER80_CSIXA 0x0080
+#define CSR_CSI_RST_MODE GENMASK(17, 16)
+
+#define MIPI_RX_ANAA8_CSIXA 0x00a8
+#define RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT BIT(0)
+#define RG_CSIXA_DPHY_L1_BYTECK_INVERT BIT(1)
+#define RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT BIT(2)
+
+#endif
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
new file mode 100644
index 000000000000..6eafd7c0514c
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek MIPI CSI v0.5 driver
+ *
+ * Copyright (c) 2023, MediaTek Inc.
+ * Copyright (c) 2023, BayLibre Inc.
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "phy-mtk-io.h"
+#include "phy-mtk-mipi-csi-0-5-rx-reg.h"
+
+#define CSIXB_OFFSET 0x1000
+
+struct mtk_mipi_dphy;
+
+struct mtk_mipi_dphy_port {
+ struct device *dev;
+ void __iomem *base;
+ struct phy *phy;
+ u32 type;
+};
+
+static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base)
+{
+ mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA,
+ RG_CSI0A_L0_T0AB_EQ_IS, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA,
+ RG_CSI0A_L0_T0AB_EQ_BW, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI0A_L1_T1AB_EQ_IS, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI0A_L1_T1AB_EQ_BW, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A,
+ RG_CSI0A_L2_T1BC_EQ_IS, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A,
+ RG_CSI0A_L2_T1BC_EQ_BW, 1);
+
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA,
+ RG_CSI0A_L0_T0AB_EQ_IS, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA,
+ RG_CSI0A_L0_T0AB_EQ_BW, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI0A_L1_T1AB_EQ_IS, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI0A_L1_T1AB_EQ_BW, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A,
+ RG_CSI0A_L2_T1BC_EQ_IS, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A,
+ RG_CSI0A_L2_T1BC_EQ_BW, 1);
+}
+
+static void mtk_phy_csi_dphy_ana_eq_tune(void __iomem *base)
+{
+ mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L0_EQ_IS, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L0_EQ_BW, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L1_EQ_IS, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L1_EQ_BW, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI1A_L2_EQ_IS, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI1A_L2_EQ_BW, 1);
+
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L0_EQ_IS, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L0_EQ_BW, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L1_EQ_IS, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA,
+ RG_CSI1A_L1_EQ_BW, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI1A_L2_EQ_IS, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA,
+ RG_CSI1A_L2_EQ_BW, 1);
+}
+
+static int mtk_mipi_phy_power_on(struct phy *phy)
+{
+ struct mtk_mipi_dphy_port *port = phy_get_drvdata(phy);
+ void __iomem *base = port->base;
+
+ /*
+ * The driver currently supports DPHY and CD-PHY phys,
+ * but the only mode supported is DPHY,
+ * so CD-PHY capable phys must be configured in DPHY mode
+ */
+ if (port->type == PHY_TYPE_CDPHY) {
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSI0A_CPHY_EN, 0);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSI0A_CPHY_EN, 0);
+ }
+
+ /*
+ * Lane configuration:
+ *
+ * Only 4 data + 1 clock is supported for now with the following mapping:
+ *
+ * CSIXA_LNR0 --> D2
+ * CSIXA_LNR1 --> D0
+ * CSIXA_LNR2 --> C
+ * CSIXB_LNR0 --> D1
+ * CSIXB_LNR1 --> D3
+ */
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L0_CKMODE_EN, 0);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L0_CKSEL, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L1_CKMODE_EN, 0);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L1_CKSEL, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L2_CKMODE_EN, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L2_CKSEL, 1);
+
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L0_CKMODE_EN, 0);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L0_CKSEL, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L1_CKMODE_EN, 0);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L1_CKSEL, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L2_CKMODE_EN, 0);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_DPHY_L2_CKSEL, 1);
+
+ /* Byte clock invert */
+ mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA,
+ RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA,
+ RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1);
+ mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA,
+ RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1);
+
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,
+ RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,
+ RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,
+ RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1);
+
+ /* Start ANA EQ tuning */
+ if (port->type == PHY_TYPE_CDPHY)
+ mtk_phy_csi_cdphy_ana_eq_tune(base);
+ else
+ mtk_phy_csi_dphy_ana_eq_tune(base);
+
+ /* End ANA EQ tuning */
+ mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90);
+
+ mtk_phy_update_field(base + MIPI_RX_ANA24_CSIXA,
+ RG_CSIXA_RESERVE, 0x40);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA24_CSIXA,
+ RG_CSIXA_RESERVE, 0x40);
+ mtk_phy_update_field(base + MIPI_RX_WRAPPER80_CSIXA,
+ CSR_CSI_RST_MODE, 0);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_WRAPPER80_CSIXA,
+ CSR_CSI_RST_MODE, 0);
+ /* ANA power on */
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_CORE_EN, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_CORE_EN, 1);
+ usleep_range(20, 40);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_LPF_EN, 1);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_LPF_EN, 1);
+
+ return 0;
+}
+
+static int mtk_mipi_phy_power_off(struct phy *phy)
+{
+ struct mtk_mipi_dphy_port *port = phy_get_drvdata(phy);
+ void __iomem *base = port->base;
+
+ /* Disable MIPI BG. */
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_CORE_EN, 0);
+ mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_LPF_EN, 0);
+
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_CORE_EN, 0);
+ mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
+ RG_CSIXA_BG_LPF_EN, 0);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_dphy_ops = {
+ .power_on = mtk_mipi_phy_power_on,
+ .power_off = mtk_mipi_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int mtk_mipi_dphy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ struct mtk_mipi_dphy_port *port;
+ struct phy *phy;
+ int ret;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, port);
+
+ port->dev = dev;
+
+ port->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(port->base))
+ return PTR_ERR(port->base);
+
+ ret = of_property_read_u32(dev->of_node, "mediatek,phy-type", &port->type);
+ if (ret) {
+ dev_err(dev, "Failed to read mediatek,phy-type\n");
+ return ret;
+ }
+
+ phy = devm_phy_create(dev, NULL, &mtk_dphy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(phy));
+ return PTR_ERR(phy);
+ }
+
+ port->phy = phy;
+ phy_set_drvdata(phy, port);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "Failed to register PHY provider: %ld\n",
+ PTR_ERR(phy_provider));
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id mtk_mipi_dphy_of_match[] = {
+ { .compatible = "mediatek,mt8365-csi-rx" },
+ { /* sentinel */},
+};
+MODULE_DEVICE_TABLE(of, mtk_mipi_dphy_of_match);
+
+static struct platform_driver mipi_dphy_pdrv = {
+ .probe = mtk_mipi_dphy_probe,
+ .driver = {
+ .name = "mtk-mipi-csi-0-5",
+ .of_match_table = mtk_mipi_dphy_of_match,
+ },
+};
+module_platform_driver(mipi_dphy_pdrv);
+
+MODULE_DESCRIPTION("MediaTek MIPI CSI CD-PHY v0.5 Driver");
+MODULE_AUTHOR("Louis Kuo <louis.kuo@mediatek.com>");
+MODULE_LICENSE("GPL");
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
2023-05-24 8:30 ` [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 Julien Stephan
@ 2023-05-24 9:45 ` AngeloGioacchino Del Regno
2023-05-24 14:05 ` Julien Stephan
0 siblings, 1 reply; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-05-24 9:45 UTC (permalink / raw)
To: Julien Stephan
Cc: mkorpershoek, khilman, Florian Sylvestre, Andy Hsieh,
Chunfeng Yun, Chun-Kuang Hu, Conor Dooley, devicetree, dri-devel,
Kishon Vijay Abraham I, Krzysztof Kozlowski, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-phy, Matthias Brugger,
Philipp Zabel, Rob Herring, Vinod Koul
Il 24/05/23 10:30, Julien Stephan ha scritto:
> From: Florian Sylvestre <fsylvestre@baylibre.com>
>
> This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in
> some Mediatek soc, such as the mt8365
>
> Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com>
> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> ---
> .../bindings/phy/mediatek,mt8365-csi-rx.yaml | 67 +++++++++++++++++++
> MAINTAINERS | 6 ++
> 2 files changed, 73 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> new file mode 100644
> index 000000000000..a1bd96a98051
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2023 MediaTek, BayLibre
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Sensor Interface MIPI CSI CD-PHY
> +
> +maintainers:
> + - Julien Stephan <jstephan@baylibre.com>
> + - Andy Hsieh <andy.hsieh@mediatek.com>
> +
> +description:
> + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
> + receivers. The number of PHYs depends on the SoC model.
> + Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
> + capable.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8365-csi-rx
> +
> + reg:
> + maxItems: 1
> +
> + '#phy-cells':
> + const: 0
> +
> + mediatek,phy-type:
Instead of declaring a phy-type here like this, can't we instead declare that in
the phy cells, like we're doing with MTK TPHY and like other non-MediaTek PHYs are
already doing?
device {
...
phys = <&csi0_rx PHY_TYPE_CDPHY>;
...
}
Regards,
Angelo
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition
2023-05-24 8:30 ` [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition Julien Stephan
@ 2023-05-24 9:45 ` AngeloGioacchino Del Regno
2023-06-03 19:09 ` Krzysztof Kozlowski
1 sibling, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-05-24 9:45 UTC (permalink / raw)
To: Julien Stephan
Cc: mkorpershoek, khilman, Andy Hsieh, Chunfeng Yun, Chun-Kuang Hu,
Conor Dooley, devicetree, dri-devel, Kishon Vijay Abraham I,
Krzysztof Kozlowski, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-phy, Matthias Brugger, Philipp Zabel,
Rob Herring, Vinod Koul
Il 24/05/23 10:30, Julien Stephan ha scritto:
> Add definition for CDPHY phy type that can be configured in either D-PHY
> mode or C-PHY mode
>
> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> include/dt-bindings/phy/phy.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
> index 6b901b342348..a19d85dbbf16 100644
> --- a/include/dt-bindings/phy/phy.h
> +++ b/include/dt-bindings/phy/phy.h
> @@ -23,5 +23,6 @@
> #define PHY_TYPE_DPHY 10
> #define PHY_TYPE_CPHY 11
> #define PHY_TYPE_USXGMII 12
> +#define PHY_TYPE_CDPHY 13
>
> #endif /* _DT_BINDINGS_PHY */
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
2023-05-24 9:45 ` AngeloGioacchino Del Regno
@ 2023-05-24 14:05 ` Julien Stephan
2023-06-08 20:05 ` Rob Herring
0 siblings, 1 reply; 9+ messages in thread
From: Julien Stephan @ 2023-05-24 14:05 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: mkorpershoek, khilman, Florian Sylvestre, Andy Hsieh,
Chunfeng Yun, Chun-Kuang Hu, Conor Dooley, devicetree, dri-devel,
Kishon Vijay Abraham I, Krzysztof Kozlowski, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-phy, Matthias Brugger,
Philipp Zabel, Rob Herring, Vinod Koul
On Wed, May 24, 2023 at 11:45:30AM +0200, AngeloGioacchino Del Regno wrote:
> Il 24/05/23 10:30, Julien Stephan ha scritto:
> > From: Florian Sylvestre <fsylvestre@baylibre.com>
> >
> > This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in
> > some Mediatek soc, such as the mt8365
> >
> > Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com>
> > Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> > ---
> > .../bindings/phy/mediatek,mt8365-csi-rx.yaml | 67 +++++++++++++++++++
> > MAINTAINERS | 6 ++
> > 2 files changed, 73 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> > new file mode 100644
> > index 000000000000..a1bd96a98051
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2023 MediaTek, BayLibre
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Sensor Interface MIPI CSI CD-PHY
> > +
> > +maintainers:
> > + - Julien Stephan <jstephan@baylibre.com>
> > + - Andy Hsieh <andy.hsieh@mediatek.com>
> > +
> > +description:
> > + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
> > + receivers. The number of PHYs depends on the SoC model.
> > + Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
> > + capable.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt8365-csi-rx
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#phy-cells':
> > + const: 0
> > +
> > + mediatek,phy-type:
>
> Instead of declaring a phy-type here like this, can't we instead declare that in
> the phy cells, like we're doing with MTK TPHY and like other non-MediaTek PHYs are
> already doing?
>
> device {
> ...
> phys = <&csi0_rx PHY_TYPE_CDPHY>;
> ...
> }
>
> Regards,
> Angelo
>
>
Hi Angelo,
This is a hardware property that is not dynamic, so IMHO it doesn't make sense
to use phy argument for that. Some driver already use a 'phy-type'
property (such as phy-cadence-torrent.yaml).
I was thinking of using phy argument on future upgrade when driver will
support D-PHY and C-PHY modes so the phy user will be able to choose the
mode.
Does it makes sense?
Best
Julien
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition
2023-05-24 8:30 ` [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition Julien Stephan
2023-05-24 9:45 ` AngeloGioacchino Del Regno
@ 2023-06-03 19:09 ` Krzysztof Kozlowski
1 sibling, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2023-06-03 19:09 UTC (permalink / raw)
To: Julien Stephan
Cc: mkorpershoek, khilman, Andy Hsieh, AngeloGioacchino Del Regno,
Chunfeng Yun, Chun-Kuang Hu, Conor Dooley, devicetree, dri-devel,
Kishon Vijay Abraham I, Krzysztof Kozlowski, linux-arm-kernel,
linux-kernel, linux-mediatek, linux-phy, Matthias Brugger,
Philipp Zabel, Rob Herring, Vinod Koul
On 24/05/2023 10:30, Julien Stephan wrote:
> Add definition for CDPHY phy type that can be configured in either D-PHY
> mode or C-PHY mode
>
> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> ---
> include/dt-bindings/phy/phy.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
> index 6b901b342348..a19d85dbbf16 100644
> --- a/include/dt-bindings/phy/phy.h
> +++ b/include/dt-bindings/phy/phy.h
> @@ -23,5 +23,6 @@
> #define PHY_TYPE_DPHY 10
> #define PHY_TYPE_CPHY 11
> #define PHY_TYPE_USXGMII 12
> +#define PHY_TYPE_CDPHY 13
I don't think there is CD phy. It is D-PHY or C-PHY. This is not for all
possible combinations but just types of phy.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
2023-05-24 14:05 ` Julien Stephan
@ 2023-06-08 20:05 ` Rob Herring
0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2023-06-08 20:05 UTC (permalink / raw)
To: Julien Stephan
Cc: AngeloGioacchino Del Regno, mkorpershoek, khilman,
Florian Sylvestre, Andy Hsieh, Chunfeng Yun, Chun-Kuang Hu,
Conor Dooley, devicetree, dri-devel, Kishon Vijay Abraham I,
Krzysztof Kozlowski, linux-arm-kernel, linux-kernel,
linux-mediatek, linux-phy, Matthias Brugger, Philipp Zabel,
Vinod Koul
On Wed, May 24, 2023 at 04:05:03PM +0200, Julien Stephan wrote:
> On Wed, May 24, 2023 at 11:45:30AM +0200, AngeloGioacchino Del Regno wrote:
> > Il 24/05/23 10:30, Julien Stephan ha scritto:
> > > From: Florian Sylvestre <fsylvestre@baylibre.com>
> > >
> > > This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in
> > > some Mediatek soc, such as the mt8365
> > >
> > > Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com>
> > > Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> > > ---
> > > .../bindings/phy/mediatek,mt8365-csi-rx.yaml | 67 +++++++++++++++++++
> > > MAINTAINERS | 6 ++
> > > 2 files changed, 73 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> > > new file mode 100644
> > > index 000000000000..a1bd96a98051
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
> > > @@ -0,0 +1,67 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +# Copyright (c) 2023 MediaTek, BayLibre
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Mediatek Sensor Interface MIPI CSI CD-PHY
> > > +
> > > +maintainers:
> > > + - Julien Stephan <jstephan@baylibre.com>
> > > + - Andy Hsieh <andy.hsieh@mediatek.com>
> > > +
> > > +description:
> > > + The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
> > > + receivers. The number of PHYs depends on the SoC model.
> > > + Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
> > > + capable.
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - mediatek,mt8365-csi-rx
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + '#phy-cells':
> > > + const: 0
> > > +
> > > + mediatek,phy-type:
> >
> > Instead of declaring a phy-type here like this, can't we instead declare that in
> > the phy cells, like we're doing with MTK TPHY and like other non-MediaTek PHYs are
> > already doing?
> >
> > device {
> > ...
> > phys = <&csi0_rx PHY_TYPE_CDPHY>;
> > ...
> > }
> >
> > Regards,
> > Angelo
> >
> >
>
> Hi Angelo,
>
> This is a hardware property that is not dynamic, so IMHO it doesn't make sense
> to use phy argument for that.
Why? Interrupt numbers are fixed hardware properties which go in arg
cells.
> Some driver already use a 'phy-type'
> property (such as phy-cadence-torrent.yaml).
>
> I was thinking of using phy argument on future upgrade when driver will
> support D-PHY and C-PHY modes so the phy user will be able to choose the
> mode.
Once you design the binding, you don't get to change it.
Rob
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-06-08 20:06 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-24 8:30 [PATCH v3 0/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
2023-05-24 8:30 ` [PATCH v3 1/3] dt-bindings: phy: add PHY_TYPE_CDPHY definition Julien Stephan
2023-05-24 9:45 ` AngeloGioacchino Del Regno
2023-06-03 19:09 ` Krzysztof Kozlowski
2023-05-24 8:30 ` [PATCH v3 2/3] dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5 Julien Stephan
2023-05-24 9:45 ` AngeloGioacchino Del Regno
2023-05-24 14:05 ` Julien Stephan
2023-06-08 20:05 ` Rob Herring
2023-05-24 8:30 ` [PATCH v3 3/3] phy: mtk-mipi-csi: add driver for CSI phy Julien Stephan
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