From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
To: <kernel@esmil.dk>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <krzk@kernel.org>,
<conor+dt@kernel.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<daniel.lezcano@linaro.org>, <tglx@linutronix.de>,
<conor@kernel.org>, <anup@brainfault.org>,
<gregkh@linuxfoundation.org>, <jirislaby@kernel.org>,
<michal.simek@amd.com>, <michael.zhu@starfivetech.com>,
<drew@beagleboard.org>
Cc: <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <jeeheng.sia@starfivetech.com>,
<leyfoon.tan@starfivetech.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v3 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles
Date: Fri, 1 Dec 2023 20:14:05 +0800 [thread overview]
Message-ID: <20231201121410.95298-2-jeeheng.sia@starfivetech.com> (raw)
In-Reply-To: <20231201121410.95298-1-jeeheng.sia@starfivetech.com>
Add new compatible strings for Dubhe-80 and Dubhe-90. These are
RISC-V cpu core from StarFive Technology and are used in StarFive
JH8100 SoC.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index f392e367d673..0dd2d2ce4fcd 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -45,6 +45,8 @@ properties:
- sifive,u7
- sifive,u74
- sifive,u74-mc
+ - starfive,dubhe-80
+ - starfive,dubhe-90
- thead,c906
- thead,c910
- thead,c920
--
2.34.1
next prev parent reply other threads:[~2023-12-01 12:14 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-01 12:14 [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Sia Jee Heng
2023-12-01 12:14 ` Sia Jee Heng [this message]
2023-12-01 12:14 ` [PATCH v3 2/6] dt-bindings: riscv: Add " Sia Jee Heng
2023-12-13 12:43 ` Conor Dooley
2023-12-13 13:24 ` Leyfoon Tan
2023-12-14 0:36 ` JeeHeng Sia
2023-12-14 16:22 ` Conor Dooley
2023-12-14 17:20 ` Palmer Dabbelt
2023-12-15 1:49 ` JeeHeng Sia
2023-12-16 12:06 ` Conor Dooley
2023-12-01 12:14 ` [PATCH v3 3/6] dt-bindings: timer: Add StarFive JH8100 clint Sia Jee Heng
2023-12-04 17:36 ` Daniel Lezcano
2024-01-18 19:23 ` [tip: timers/core] " tip-bot2 for Sia Jee Heng
2023-12-01 12:14 ` [PATCH v3 4/6] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Sia Jee Heng
2023-12-01 12:14 ` [PATCH v3 5/6] dt-bindings: serial: cdns: Add new compatible string for StarFive JH8100 UART Sia Jee Heng
2023-12-01 15:46 ` Conor Dooley
2023-12-01 12:14 ` [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Sia Jee Heng
2023-12-08 12:08 ` Shengyu Qu
2023-12-11 1:38 ` JeeHeng Sia
2023-12-11 7:58 ` Conor Dooley
2023-12-11 9:38 ` JeeHeng Sia
2023-12-11 17:43 ` Conor Dooley
2023-12-08 16:05 ` Emil Renner Berthing
2023-12-13 12:39 ` Emil Renner Berthing
2023-12-14 0:34 ` JeeHeng Sia
2023-12-06 16:45 ` [PATCH v3 0/6] Initial device tree support for StarFive JH8100 SoC Conor Dooley
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