From: <Lewis.Hanly@microchip.com>
To: <linus.walleij@linaro.org>
Cc: <linux-riscv@lists.infradead.org>, <Conor.Dooley@microchip.com>,
<brgl@bgdev.pl>, <linux-gpio@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <palmer@dabbelt.com>,
<maz@kernel.org>, <Daire.McNamara@microchip.com>
Subject: Re: [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support
Date: Mon, 5 Sep 2022 10:45:38 +0000 [thread overview]
Message-ID: <23d74882a69b39025005495886faec3e5b129ba7.camel@microchip.com> (raw)
In-Reply-To: <CACRpkdZqvEvqjzTN3oQqrV_CNK+D2+c4FjLiC1_ZoKQ-rMMe5A@mail.gmail.com>
On Wed, 2022-08-31 at 15:19 +0200, Linus Walleij wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
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>
> On Tue, Aug 30, 2022 at 6:51 AM <Lewis.Hanly@microchip.com> wrote:
>
> > We had looked at the bpgpio_init, our controller is not fully
> > memory
> > mapped to support the bgpio_init() and get all routines for free.
> > While we have in/out and intr (interrupt state) 32-bit registers,
> > we
> > would not get as much free as other generic memory mapped
> > controllers.
>
> You're not really saying what the problem is?
>
> Is it that some registers are not one-bit-indexed from 0 per GPIO?
Yes some of the registers are not one-bit-indexed per GPIO and for this
reason we had not implemented bgpio_init().
>
> Yours,
> Linus Walleij
next prev parent reply other threads:[~2022-09-05 10:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 12:08 [PATCH v6 0/1] Add Polarfire SoC GPIO support lewis.hanly
2022-08-15 12:08 ` [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support lewis.hanly
2022-08-15 16:18 ` Conor.Dooley
2022-08-22 11:28 ` Linus Walleij
2022-08-30 4:50 ` Lewis.Hanly
2022-08-31 13:19 ` Linus Walleij
2022-09-05 10:45 ` Lewis.Hanly [this message]
2022-09-06 13:09 ` Linus Walleij
2022-08-31 21:04 ` Andy Shevchenko
2022-09-05 10:46 ` Lewis.Hanly
2022-08-15 12:16 ` [PATCH v6 0/1] Add Polarfire SoC GPIO support Marc Zyngier
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