From: Dave Hansen <dave.hansen@intel.com>
To: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>
Cc: Borislav Petkov <bpetkov@suse.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Brian Gerst <brgerst@gmail.com>,
Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [RFC 4/7] x86/asm: Fix assumptions that the HW TSS is at the beginning of cpu_tss
Date: Mon, 13 Nov 2017 09:01:26 -0800 [thread overview]
Message-ID: <2fdf9cf9-ec48-e63f-2ec8-44160c206c9a@intel.com> (raw)
In-Reply-To: <03fb20a8639aeecfeda3ba18a520ce646267eb9a.1510371795.git.luto@kernel.org>
On 11/10/2017 08:05 PM, Andy Lutomirski wrote:
> -struct tss_struct doublefault_tss __cacheline_aligned = {
> - .x86_tss = {
> - .sp0 = STACK_START,
> - .ss0 = __KERNEL_DS,
> - .ldt = 0,
...
> +struct x86_hw_tss doublefault_tss __cacheline_aligned = {
> + .sp0 = STACK_START,
> + .ss0 = __KERNEL_DS,
> + .ldt = 0,
> + .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
FWIW, I really like the trend of renaming the hardware structures in
such a way that it's clear that they *are* hardware structures.
It might also be nice to reference the relevant SDM sections on the
topic, or even to include a comment along the lines of how it get used.
This chunk from the SDM is particularly relevant:
"The TSS holds information important to 64-bit mode and that is not
directly related to the task-switch mechanism."
next prev parent reply other threads:[~2017-11-13 17:01 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-11 4:05 [RFC 0/7] Prep code for better stack switching Andy Lutomirski
2017-11-11 4:05 ` [RFC 1/7] x86/asm/64: Allocate and enable the SYSENTER stack Andy Lutomirski
2017-11-13 19:07 ` Dave Hansen
2017-11-14 2:17 ` Andy Lutomirski
2017-11-14 7:15 ` Ingo Molnar
2017-11-11 4:05 ` [RFC 2/7] x86/gdt: Put per-cpu GDT remaps in ascending order Andy Lutomirski
2017-11-11 4:05 ` [RFC 3/7] x86/fixmap: Generalize the GDT fixmap mechanism Andy Lutomirski
2017-11-11 4:05 ` [RFC 4/7] x86/asm: Fix assumptions that the HW TSS is at the beginning of cpu_tss Andy Lutomirski
2017-11-13 17:01 ` Dave Hansen [this message]
2017-11-26 13:48 ` [PATCH v2] x86/entry: " Ingo Molnar
2017-11-26 15:41 ` Andy Lutomirski
2017-11-26 15:58 ` Ingo Molnar
2017-11-26 16:00 ` Ingo Molnar
2017-11-26 16:05 ` Andy Lutomirski
2017-11-26 16:43 ` Ingo Molnar
2017-11-11 4:05 ` [RFC 5/7] x86/asm: Rearrange struct cpu_tss to enlarge SYSENTER_stack and fix alignment Andy Lutomirski
2017-11-11 4:11 ` Andy Lutomirski
2017-11-13 19:19 ` Dave Hansen
2017-11-11 4:05 ` [RFC 6/7] x86/asm: Remap the TSS into the cpu entry area Andy Lutomirski
2017-11-13 19:22 ` Dave Hansen
2017-11-13 19:36 ` Linus Torvalds
2017-11-14 2:25 ` Andy Lutomirski
2017-11-14 2:28 ` Linus Torvalds
2017-11-14 2:30 ` Andy Lutomirski
2017-11-14 2:27 ` Andy Lutomirski
2017-11-11 4:05 ` [RFC 7/7] x86/unwind/64: Add support for the SYSENTER stack Andy Lutomirski
2017-11-13 22:46 ` Josh Poimboeuf
2017-11-14 2:13 ` Andy Lutomirski
2017-11-11 10:58 ` [RFC 0/7] Prep code for better stack switching Borislav Petkov
2017-11-12 2:59 ` Andy Lutomirski
2017-11-12 4:25 ` Andy Lutomirski
2017-11-13 4:37 ` Andy Lutomirski
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