[PATCH V1] one wire ds1wm patch

[PATCH V1] one wire ds1wm patch

[Johannes Pöhlmann]

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To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
with a register offset multiplier of 4 i had to make some changes to

          drivers/w1/masters/ds1wm.c
and    include/linux/mfd/ds1wm.h.

I grouped theses into 4 patches of falling priority.

[PATCH 1/4] fix and simplify register access
[PATCH 2/4] Add level interrupt modes (maybe no longer needed in newer
kernels)
[PATCH 3/4] Silence interrupts on HW before claiming the interrupt
[PATCH 4/4] optional: add messages to make incorporation in  mfd drivers
easier

The patches applied cleanly against
   commit 32c1431eea4881a6b17bd7c639315010aeefa452
   Author: Linus Torvalds <torvalds@linux-foundation.org>
   Date:   Sun Jun 11 16:48:20 2017 -0700
    Linux 4.12-rc5

I could build the patched kernel (as above) with ds1wm configured in
with no errors or warnings.

I could test and verify the correct working of the patch against
kernel 3.12.15, but not against the current kernel.



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[-- Attachment #2: 0001-fix-and-simplify-register-access.patch --]
[-- Type: text/x-patch; name="0001-fix-and-simplify-register-access.patch", Size: 5526 bytes --]

From 6edd0fa88631cc20a742e0567c2e0e6cb9e5a8fc Mon Sep 17 00:00:00 2001
From: Johannes Poeehlmann <johannes.poehlmann@izt-labs.de>
Date: Thu, 9 Feb 2017 14:05:22 +0100
Subject: [PATCH 1/4] fix and simplify register access

o Replace incorrect register offsett calculation by
direct configuration of bus_shift in mfd-cell.
Indirect definition of address-shift by resource size
was unobvious and should have used a binary log.
o Make endian clean, make HW-endianness configurable.
o Use ioread*, iowrite* instead of __raw_readb,__raw_writeb
to also use memory-barriers when accessing HW-registers.
We do not want reordering to happen here.

Signed-off-by: Johannes Poeehlmann <johannes.poehlmann@izt-labs.de>
---
 drivers/w1/masters/ds1wm.c | 92 +++++++++++++++++++++++++++++++++++++++++++---
 include/linux/mfd/ds1wm.h  | 10 +++++
 2 files changed, 97 insertions(+), 5 deletions(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index e0b8a4b..e6284b7 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -97,6 +97,7 @@ static struct {
 struct ds1wm_data {
 	void     __iomem *map;
 	int      bus_shift; /* # of shifts to calc register offsets */
+	int      isHwBigEndian;
 	struct platform_device *pdev;
 	const struct mfd_cell   *cell;
 	int      irq;
@@ -116,12 +117,83 @@ struct ds1wm_data {
 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 					u8 val)
 {
-	__raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
+	if (ds1wm_data->isHwBigEndian) {
+		switch (ds1wm_data->bus_shift) {
+		case BUSWIDTH8:
+			writeb(val, ds1wm_data->map + (reg << BUSWIDTH8));
+			break;
+		case BUSWIDTH16:
+			writew_be((u16)val, ds1wm_data->map+(reg<<BUSWIDTH16));
+			break;
+		case BUSWIDTH32:
+			writel_be((u32)val, ds1wm_data->map+(reg<<BUSWIDTH32));
+			break;
+		default:
+		  dev_err(&ds1wm_data->pdev->dev,
+		  "illegal bus shift %d, not written",
+		  ds1wm_data->bus_shift);
+		}
+	} else {
+		switch (ds1wm_data->bus_shift) {
+		case BUSWIDTH8:
+			writeb(val, ds1wm_data->map + (reg << BUSWIDTH8));
+			break;
+		case BUSWIDTH16:
+			writew((u16) val, ds1wm_data->map+(reg << BUSWIDTH16));
+			break;
+		case BUSWIDTH32:
+			writel((u32) val, ds1wm_data->map+(reg << BUSWIDTH32));
+			break;
+		default:
+		  dev_err(&ds1wm_data->pdev->dev,
+		  "illegal bus shift %d, not written",
+		  ds1wm_data->bus_shift);
+		}
+	}
 }
 
 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 {
-	return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
+
+	u32 val = 0;
+	if (ds1wm_data->isHwBigEndian) {
+		switch (ds1wm_data->bus_shift) {
+		case BUSWIDTH8:
+			val = readb(ds1wm_data->map + (reg << BUSWIDTH8));
+			break;
+		case BUSWIDTH16:
+			val = readw_be(ds1wm_data->map + (reg << BUSWIDTH16));
+			break;
+		case BUSWIDTH32:
+			val = readl_be(ds1wm_data->map + (reg << BUSWIDTH32));
+			break;
+		default:
+		   dev_err(&ds1wm_data->pdev->dev,
+		   "illegal bus shift %d, not read",
+		   ds1wm_data->bus_shift);
+		}
+	} else {
+		switch (ds1wm_data->bus_shift) {
+		case BUSWIDTH8:
+			val = readb(ds1wm_data->map + (reg << BUSWIDTH8));
+			break;
+		case BUSWIDTH16:
+			val = readw(ds1wm_data->map + (reg << BUSWIDTH16));
+			break;
+		case BUSWIDTH32:
+			val = readl(ds1wm_data->map + (reg << BUSWIDTH32));
+			break;
+		default:
+		   dev_err(&ds1wm_data->pdev->dev,
+		   "illegal bus shift %d, not read",
+		   ds1wm_data->bus_shift);
+
+		   return 0;
+		}
+	}
+	dev_dbg(&ds1wm_data->pdev->dev,
+		"ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val);
+	return (u8) val;
 }
 
 
@@ -474,9 +546,6 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (!ds1wm_data->map)
 		return -ENOMEM;
 
-	/* calculate bus shift from mem resource */
-	ds1wm_data->bus_shift = resource_size(res) >> 3;
-
 	ds1wm_data->pdev = pdev;
 	ds1wm_data->cell = mfd_get_cell(pdev);
 	if (!ds1wm_data->cell)
@@ -485,6 +554,19 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (!plat)
 		return -ENODEV;
 
+	/* how many bits to shift register number to get register offset */
+	ds1wm_data->bus_shift = plat->bus_shift;
+
+	/* make sure resource has space for 8 registers */
+	if ( (8 << ds1wm_data->bus_shift ) > resource_size(res)  ){
+		dev_err(&ds1wm_data->pdev->dev,
+			"memory ressource size %d to small, should be %d\n",
+			(int) resource_size(res),
+			8 << ds1wm_data->bus_shift);
+	}
+
+	ds1wm_data->isHwBigEndian = plat->isHwBigEndian;
+
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (!res)
 		return -ENXIO;
diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
index 38a372a..2fbc433 100644
--- a/include/linux/mfd/ds1wm.h
+++ b/include/linux/mfd/ds1wm.h
@@ -1,5 +1,10 @@
 /* MFD cell driver data for the DS1WM driver */
 
+/* bus shift constants */
+#define BUSWIDTH8		0
+#define BUSWIDTH16		1
+#define BUSWIDTH32		2
+
 struct ds1wm_driver_data {
 	int active_high;
 	int clock_rate;
@@ -10,4 +15,9 @@ struct ds1wm_driver_data {
 	/* ds1wm implements the precise timings of*/
 	/* a reset pulse/presence detect sequence.*/
 	unsigned int reset_recover_delay;
+	/* Say 1 here for big endian Hardware
+	 * (only relevant with bus-shift > 0*/
+	int isHwBigEndian;
+	/* left shift of register number to get register address offsett */
+	int bus_shift;
 };
-- 
2.1.4





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[-- Attachment #3: 0002-Add-level-interrupt-modes-maybe-no-longer-needed-in-.patch --]
[-- Type: text/x-patch; name="0002-Add-level-interrupt-modes-maybe-no-longer-needed-in-.patch", Size: 1163 bytes --]

From b7dffcbde0fb81fcbf4fb6ac7b54e59ec9064d27 Mon Sep 17 00:00:00 2001
From: Johannes Poeehlmann <johannes.poehlmann@izt-labs.de>
Date: Thu, 9 Feb 2017 14:06:08 +0100
Subject: [PATCH 2/4] Add level interrupt modes (maybe no longer needed in
 newer kernels)

Signed-off-by: Johannes Poeehlmann <johannes.poehlmann@izt-labs.de>
---
 drivers/w1/masters/ds1wm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index e6284b7..bed512b2 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -578,6 +578,10 @@ static int ds1wm_probe(struct platform_device *pdev)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 	if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
+	if (res->flags & IORESOURCE_IRQ_HIGHLEVEL)
+		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_HIGH);
+	if (res->flags & IORESOURCE_IRQ_LOWLEVEL)
+		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_LOW);
 
 	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
 			IRQF_SHARED, "ds1wm", ds1wm_data);
-- 
2.1.4





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[-- Attachment #4: 0003-Silence-interrupts-on-HW-before-claiming-the-interru.patch --]
[-- Type: text/x-patch; name="0003-Silence-interrupts-on-HW-before-claiming-the-interru.patch", Size: 1289 bytes --]

From 1f29d55030a65e2223ea8bea9d18889a34770210 Mon Sep 17 00:00:00 2001
From: Johannes Poeehlmann <johannes.poehlmann@izt-labs.de>
Date: Thu, 9 Feb 2017 14:07:10 +0100
Subject: [PATCH 3/4] Silence interrupts on HW before claiming the interrupt

---
 drivers/w1/masters/ds1wm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index bed512b2..bdfb19c 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -528,6 +528,7 @@ static int ds1wm_probe(struct platform_device *pdev)
 	struct ds1wm_driver_data *plat;
 	struct resource *res;
 	int ret;
+	u8 inten;
 
 	if (!pdev)
 		return -ENODEV;
@@ -574,6 +575,11 @@ static int ds1wm_probe(struct platform_device *pdev)
 	ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
 	ds1wm_data->reset_recover_delay = plat->reset_recover_delay;
 
+	/* Mask interrupts, set IAS before claiming interrupt */
+	inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
+	ds1wm_write_register(ds1wm_data,
+		DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
+
 	if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 	if (res->flags & IORESOURCE_IRQ_LOWEDGE)
-- 
2.1.4





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[-- Attachment #5: 0004-optional-add-messages-to-make-incorporation-in-mfd-d.patch --]
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From 49457b8f75bd169d1cc511355341ce459ac9095a Mon Sep 17 00:00:00 2001
From: Johannes Poeehlmann <johannes.poehlmann@izt-labs.de>
Date: Thu, 9 Feb 2017 14:09:56 +0100
Subject: [PATCH 4/4] optional: add messages to make incorporation in
 mfd-drivers easier

---
 drivers/w1/masters/ds1wm.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index bdfb19c..d480c27 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -591,8 +591,14 @@ static int ds1wm_probe(struct platform_device *pdev)
 
 	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
 			IRQF_SHARED, "ds1wm", ds1wm_data);
-	if (ret)
+	if (ret){
+		dev_err(&ds1wm_data->pdev->dev,
+			"devm_request_irq %d failed with errno %d\n",
+			ds1wm_data->irq,
+			ret);
+
 		return ret;
+	}
 
 	ds1wm_up(ds1wm_data);
 
@@ -602,6 +608,14 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (ret)
 		goto err;
 
+	dev_info(&ds1wm_data->pdev->dev,
+		"ds1wm: probe successful, IAS: %d, rec.delay: %d, "
+		"clockrate: %d, bus-shift: %d, is Hw Big Endian: %d\n",
+		plat->active_high,
+		plat->reset_recover_delay,
+		plat->clock_rate,
+		ds1wm_data->bus_shift,
+		ds1wm_data->isHwBigEndian);
 	return 0;
 
 err:
-- 
2.1.4

Re: [PATCH V1] one wire ds1wm patch

[Evgeniy Polyalkov]

Hi

19.06.2017, 14:38, "Johannes Pöhlmann" <johannes.poehlmann@izt-labs.de>:
> To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
> with a register offset multiplier of 4 i had to make some changes to
>
>           drivers/w1/masters/ds1wm.c
> and include/linux/mfd/ds1wm.h.
>
> I grouped theses into 4 patches of falling priority.
>
> [PATCH 1/4] fix and simplify register access
> [PATCH 2/4] Add level interrupt modes (maybe no longer needed in newer
> kernels)
> [PATCH 3/4] Silence interrupts on HW before claiming the interrupt
> [PATCH 4/4] optional: add messages to make incorporation in mfd drivers
> easier

Patches look good, thank you.
Greg, please pull them into your tree, is it ok to be sent as attachment?

Acked-by: Evgeniy Polyakov <zbr@ioremap.net>

Re: [PATCH V1] one wire ds1wm patch

[Greg Kroah-Hartman]

On Mon, Jun 19, 2017 at 05:55:12PM +0300, Evgeniy Polyalkov wrote:
> Hi
> 
> 19.06.2017, 14:38, "Johannes Pöhlmann" <johannes.poehlmann@izt-labs.de>:
> > To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
> > with a register offset multiplier of 4 i had to make some changes to
> >
> >           drivers/w1/masters/ds1wm.c
> > and include/linux/mfd/ds1wm.h.
> >
> > I grouped theses into 4 patches of falling priority.
> >
> > [PATCH 1/4] fix and simplify register access
> > [PATCH 2/4] Add level interrupt modes (maybe no longer needed in newer
> > kernels)
> > [PATCH 3/4] Silence interrupts on HW before claiming the interrupt
> > [PATCH 4/4] optional: add messages to make incorporation in mfd drivers
> > easier
> 
> Patches look good, thank you.

No they do not, they need to be sent in the correct format, with the
correct signed-off-by, and all of the needed information...

> Greg, please pull them into your tree, is it ok to be sent as attachment?

Not at all.

> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>

Johannes, please fix up and resend and add Evgeniy's acked-by to the
patchs and I will be glad to take them.  Please read
Documentation/SubmittingPatches for the correct format to use.

thanks,

greg k-h

Re: [PATCH V1] one wire ds1wm patch

[kbuild test robot]

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Hi Johannes,

[auto build test ERROR on linus/master]
[also build test ERROR on v4.12-rc6 next-20170619]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Johannes-P-hlmann/one-wire-ds1wm-patch/20170620-011329
config: x86_64-randconfig-x010-201725 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/w1/masters/ds1wm.c: In function 'ds1wm_write_register':
>> drivers/w1/masters/ds1wm.c:126:4: error: implicit declaration of function 'writew_be' [-Werror=implicit-function-declaration]
       writew_be((u16)val, ds1wm_data->map+(reg<<BUSWIDTH16));
       ^~~~~~~~~
>> drivers/w1/masters/ds1wm.c:129:4: error: implicit declaration of function 'writel_be' [-Werror=implicit-function-declaration]
       writel_be((u32)val, ds1wm_data->map+(reg<<BUSWIDTH32));
       ^~~~~~~~~
   drivers/w1/masters/ds1wm.c: In function 'ds1wm_read_register':
>> drivers/w1/masters/ds1wm.c:165:10: error: implicit declaration of function 'readw_be' [-Werror=implicit-function-declaration]
       val = readw_be(ds1wm_data->map + (reg << BUSWIDTH16));
             ^~~~~~~~
>> drivers/w1/masters/ds1wm.c:168:10: error: implicit declaration of function 'readl_be' [-Werror=implicit-function-declaration]
       val = readl_be(ds1wm_data->map + (reg << BUSWIDTH32));
             ^~~~~~~~
   cc1: some warnings being treated as errors

vim +/writew_be +126 drivers/w1/masters/ds1wm.c

   120		if (ds1wm_data->isHwBigEndian) {
   121			switch (ds1wm_data->bus_shift) {
   122			case BUSWIDTH8:
   123				writeb(val, ds1wm_data->map + (reg << BUSWIDTH8));
   124				break;
   125			case BUSWIDTH16:
 > 126				writew_be((u16)val, ds1wm_data->map+(reg<<BUSWIDTH16));
   127				break;
   128			case BUSWIDTH32:
 > 129				writel_be((u32)val, ds1wm_data->map+(reg<<BUSWIDTH32));
   130				break;
   131			default:
   132			  dev_err(&ds1wm_data->pdev->dev,
   133			  "illegal bus shift %d, not written",
   134			  ds1wm_data->bus_shift);
   135			}
   136		} else {
   137			switch (ds1wm_data->bus_shift) {
   138			case BUSWIDTH8:
   139				writeb(val, ds1wm_data->map + (reg << BUSWIDTH8));
   140				break;
   141			case BUSWIDTH16:
   142				writew((u16) val, ds1wm_data->map+(reg << BUSWIDTH16));
   143				break;
   144			case BUSWIDTH32:
   145				writel((u32) val, ds1wm_data->map+(reg << BUSWIDTH32));
   146				break;
   147			default:
   148			  dev_err(&ds1wm_data->pdev->dev,
   149			  "illegal bus shift %d, not written",
   150			  ds1wm_data->bus_shift);
   151			}
   152		}
   153	}
   154	
   155	static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
   156	{
   157	
   158		u32 val = 0;
   159		if (ds1wm_data->isHwBigEndian) {
   160			switch (ds1wm_data->bus_shift) {
   161			case BUSWIDTH8:
   162				val = readb(ds1wm_data->map + (reg << BUSWIDTH8));
   163				break;
   164			case BUSWIDTH16:
 > 165				val = readw_be(ds1wm_data->map + (reg << BUSWIDTH16));
   166				break;
   167			case BUSWIDTH32:
 > 168				val = readl_be(ds1wm_data->map + (reg << BUSWIDTH32));
   169				break;
   170			default:
   171			   dev_err(&ds1wm_data->pdev->dev,

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 22811 bytes --]

Re: [PATCH v2 0/4] w1: ds1wm: register access patch

[Evgeniy Polyakov]

Hi everyone

Greg, please pull this into your tree

23.06.2017, 13:47, "Johannes Poehlmann" <johannes.poehlmann@izt-labs.de>:
> To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
> with a register offset multiplier of 4 I had to make some changes to
>
>        drivers/w1/masters/ds1wm.c
> and include/linux/mfd/ds1wm.h.
>
> Version 2 of the patchset
>
> o fixes kbuild reported build problems on x86_64
> o removes unobvious shift constants
> o moves shift value checking into the probe function
> o rename variable (fix 'CamelCase' style)
>
> Johannes Poehlmann:
>   w1: ds1wm: fix and simplify register access
>   w1: ds1wm: add level interrupt modes
>   w1: ds1wm: silence interrupts on HW before claiming the interrupt
>   w1: ds1wm: add messages to make incorporation in mfd-drivers easier
>
>  drivers/w1/masters/ds1wm.c | 109 ++++++++++++++++++++++++++++++++++++++++++---
>  include/linux/mfd/ds1wm.h | 9 ++++
>  2 files changed, 111 insertions(+), 7 deletions(-)
>
> --
> 2.1.4

Re: [PATCH v2 3/4] w1: ds1wm: silence interrupts on HW before claiming the interrupt

[Greg Kroah-Hartman]

On Fri, Jun 23, 2017 at 12:47:14PM +0200, Johannes Poehlmann wrote:
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> 
> 6	0	drivers/w1/masters/ds1wm.c

What is that line for?

And I can not take patches without changelog text.

Also, kbuild found some issues with this patchset, can you please fix up
and resend?

thanks,

greg k-h

Re: [PATCH v2 4/4] w1: ds1wm: add messages to make incorporation in mfd-drivers easier

[Greg Kroah-Hartman]

On Fri, Jun 23, 2017 at 12:47:15PM +0200, Johannes Poehlmann wrote:
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> 
> 14	1	drivers/w1/masters/ds1wm.c

Again, odd changelog text :(

Re: [PATCH v2 1/4] w1: ds1wm: fix and simplify register access

[Greg Kroah-Hartman]

On Fri, Jun 23, 2017 at 12:47:12PM +0200, Johannes Poehlmann wrote:
> o Replace incorrect register offsett calculation by
> direct configuration of bus_shift in mfd-cell.
> Indirect definition of address-shift by resource size
> was unobvious and should have used a binary log.
> o Make endian clean, make HW-endianness configurable.
> o Use ioread*, iowrite* instead of __raw_readb,__raw_writeb
> to also use memory-barriers when accessing HW-registers.
> We do not want reordering to happen here.
> 
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> 
> 78	6	drivers/w1/masters/ds1wm.c
> 9	0	include/linux/mfd/ds1wm.h

And again, something went wrong here :(

[PATCH v3 0/4] w1: ds1wm: register access patch

[Johannes Poehlmann]

To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
with a register offset multiplier of 4 I had to make some changes to

       drivers/w1/masters/ds1wm.c
and    include/linux/mfd/ds1wm.h.

Version 2 of the patchset 

o fixes kbuild reported build problems on x86_64 
o removes unobvious shift constants
o moves shift value checking into the probe function
o rename variable (fix 'CamelCase' style)

Version 3 of the patchset
o rebased on v4.13-rc1 and resent to lkml

Johannes Poehlmann (4):
  w1: ds1wm: fix and simplify register access
  w1: ds1wm: add level interrupt modes
  w1: ds1wm: silence interrupts on HW before claiming the interrupt
  w1: ds1wm: add messages to make incorporation in mfd-drivers easier

 drivers/w1/masters/ds1wm.c | 109 ++++++++++++++++++++++++++++++++++++++++++---
 include/linux/mfd/ds1wm.h  |   9 ++++
 2 files changed, 111 insertions(+), 7 deletions(-)

-- 
2.1.4

[PATCH v3 1/4] w1: ds1wm: fix and simplify register access

[Johannes Poehlmann]

o Replace incorrect register offsett calculation by
direct configuration of bus_shift in mfd-cell.
Indirect definition of address-shift by resource size
was unobvious and should have used a binary log.
o Make endian clean, make HW-endianness configurable.
o Use ioread*, iowrite* instead of __raw_readb,__raw_writeb
to also use memory-barriers when accessing HW-registers.
We do not want reordering to happen here.

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 84 ++++++++++++++++++++++++++++++++++++++++++----
 include/linux/mfd/ds1wm.h  |  9 +++++
 2 files changed, 87 insertions(+), 6 deletions(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index fd2e9da..6bba2fe 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -95,7 +95,8 @@ static struct {
 
 struct ds1wm_data {
 	void     __iomem *map;
-	int      bus_shift; /* # of shifts to calc register offsets */
+	unsigned int      bus_shift; /* # of shifts to calc register offsets */
+	int      is_hw_big_endian;
 	struct platform_device *pdev;
 	const struct mfd_cell   *cell;
 	int      irq;
@@ -115,12 +116,66 @@ struct ds1wm_data {
 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 					u8 val)
 {
-	__raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
+	if (ds1wm_data->is_hw_big_endian) {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			iowrite8(val, ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			iowrite16be((u16)val, ds1wm_data->map+(reg<<1));
+			break;
+		case 2:
+			iowrite32be((u32)val, ds1wm_data->map+(reg<<2));
+			break;
+		}
+	} else {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			iowrite8(val, ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			iowrite16((u16) val, ds1wm_data->map+(reg << 1));
+			break;
+		case 2:
+			iowrite32((u32) val, ds1wm_data->map+(reg << 2));
+			break;
+		}
+	}
 }
 
 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 {
-	return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
+
+	u32 val = 0;
+
+	if (ds1wm_data->is_hw_big_endian) {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			val = ioread8(ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			val = ioread16be(ds1wm_data->map + (reg << 1));
+			break;
+		case 2:
+			val = ioread32be(ds1wm_data->map + (reg << 2));
+			break;
+		}
+	} else {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			val = ioread8(ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			val = ioread16(ds1wm_data->map + (reg << 1));
+			break;
+		case 2:
+			val = ioread32(ds1wm_data->map + (reg << 2));
+			break;
+		}
+	}
+	dev_dbg(&ds1wm_data->pdev->dev,
+		"ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val);
+	return (u8) val;
 }
 
 
@@ -473,9 +528,6 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (!ds1wm_data->map)
 		return -ENOMEM;
 
-	/* calculate bus shift from mem resource */
-	ds1wm_data->bus_shift = resource_size(res) >> 3;
-
 	ds1wm_data->pdev = pdev;
 	ds1wm_data->cell = mfd_get_cell(pdev);
 	if (!ds1wm_data->cell)
@@ -484,6 +536,26 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (!plat)
 		return -ENODEV;
 
+	/* how many bits to shift register number to get register offset */
+	if (plat->bus_shift > 2) {
+		dev_err(&ds1wm_data->pdev->dev,
+			"illegal bus shift %d, not written",
+			ds1wm_data->bus_shift);
+		return -EINVAL;
+	}
+
+	ds1wm_data->bus_shift = plat->bus_shift;
+	/* make sure resource has space for 8 registers */
+	if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
+		dev_err(&ds1wm_data->pdev->dev,
+			"memory resource size %d to small, should be %d\n",
+			(int) resource_size(res),
+			8 << ds1wm_data->bus_shift);
+		return -EINVAL;
+	}
+
+	ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian;
+
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (!res)
 		return -ENXIO;
diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
index 38a372a..4efd626 100644
--- a/include/linux/mfd/ds1wm.h
+++ b/include/linux/mfd/ds1wm.h
@@ -3,6 +3,7 @@
 struct ds1wm_driver_data {
 	int active_high;
 	int clock_rate;
+
 	/* in milliseconds, the amount of time to */
 	/* sleep following a reset pulse. Zero    */
 	/* should work if your bus devices recover*/
@@ -10,4 +11,12 @@ struct ds1wm_driver_data {
 	/* ds1wm implements the precise timings of*/
 	/* a reset pulse/presence detect sequence.*/
 	unsigned int reset_recover_delay;
+
+	/* Say 1 here for big endian Hardware */
+	/* (only relevant with bus-shift > 0 */
+	int is_hw_big_endian;
+
+	/* left shift of register number to get register address offsett */
+	/* only 0,1,2 allowed for 8,16 or 32 bit bus width respectively */
+	unsigned int bus_shift;
 };
-- 
2.1.4

[PATCH v3 2/4] w1: ds1wm: add level interrupt modes

[Johannes Poehlmann]

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 6bba2fe..1b37def 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -567,6 +567,10 @@ static int ds1wm_probe(struct platform_device *pdev)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 	if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
+	if (res->flags & IORESOURCE_IRQ_HIGHLEVEL)
+		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_HIGH);
+	if (res->flags & IORESOURCE_IRQ_LOWLEVEL)
+		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_LOW);
 
 	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
 			IRQF_SHARED, "ds1wm", ds1wm_data);
-- 
2.1.4

[PATCH v3 3/4] w1: ds1wm: silence interrupts on HW before claiming the interrupt

[Johannes Poehlmann]

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 1b37def..7cb4460 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -510,6 +510,7 @@ static int ds1wm_probe(struct platform_device *pdev)
 	struct ds1wm_driver_data *plat;
 	struct resource *res;
 	int ret;
+	u8 inten;
 
 	if (!pdev)
 		return -ENODEV;
@@ -563,6 +564,11 @@ static int ds1wm_probe(struct platform_device *pdev)
 	ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
 	ds1wm_data->reset_recover_delay = plat->reset_recover_delay;
 
+	/* Mask interrupts, set IAS before claiming interrupt */
+	inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
+	ds1wm_write_register(ds1wm_data,
+		DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
+
 	if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 	if (res->flags & IORESOURCE_IRQ_LOWEDGE)
-- 
2.1.4

[PATCH v3 4/4] w1: ds1wm: add messages to make incorporation in mfd-drivers easier

[Johannes Poehlmann]

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 7cb4460..76b4573 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -580,8 +580,14 @@ static int ds1wm_probe(struct platform_device *pdev)
 
 	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
 			IRQF_SHARED, "ds1wm", ds1wm_data);
-	if (ret)
+	if (ret) {
+		dev_err(&ds1wm_data->pdev->dev,
+			"devm_request_irq %d failed with errno %d\n",
+			ds1wm_data->irq,
+			ret);
+
 		return ret;
+	}
 
 	ds1wm_up(ds1wm_data);
 
@@ -591,6 +597,13 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (ret)
 		goto err;
 
+	dev_info(&ds1wm_data->pdev->dev,
+		"ds1wm: probe successful, IAS: %d, rec.delay: %d, clockrate: %d, bus-shift: %d, is Hw Big Endian: %d\n",
+		plat->active_high,
+		plat->reset_recover_delay,
+		plat->clock_rate,
+		ds1wm_data->bus_shift,
+		ds1wm_data->is_hw_big_endian);
 	return 0;
 
 err:
-- 
2.1.4

Re: [PATCH v3 1/4] w1: ds1wm: fix and simplify register access

[Greg Kroah-Hartman]

On Tue, Jul 18, 2017 at 01:26:50PM +0200, Johannes Poehlmann wrote:
> o Replace incorrect register offsett calculation by
> direct configuration of bus_shift in mfd-cell.
> Indirect definition of address-shift by resource size
> was unobvious and should have used a binary log.
> o Make endian clean, make HW-endianness configurable.
> o Use ioread*, iowrite* instead of __raw_readb,__raw_writeb
> to also use memory-barriers when accessing HW-registers.
> We do not want reordering to happen here.

Can you format the above to make it a bit more easier to read?

And why do all of this in one single patch?  Shouldn't this be multiple
ones?

> 
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> ---
>  drivers/w1/masters/ds1wm.c | 84 ++++++++++++++++++++++++++++++++++++++++++----
>  include/linux/mfd/ds1wm.h  |  9 +++++
>  2 files changed, 87 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
> index fd2e9da..6bba2fe 100644
> --- a/drivers/w1/masters/ds1wm.c
> +++ b/drivers/w1/masters/ds1wm.c
> @@ -95,7 +95,8 @@ static struct {
>  
>  struct ds1wm_data {
>  	void     __iomem *map;
> -	int      bus_shift; /* # of shifts to calc register offsets */
> +	unsigned int      bus_shift; /* # of shifts to calc register offsets */
> +	int      is_hw_big_endian;

bool?



>  	struct platform_device *pdev;
>  	const struct mfd_cell   *cell;
>  	int      irq;
> @@ -115,12 +116,66 @@ struct ds1wm_data {
>  static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
>  					u8 val)
>  {
> -	__raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
> +	if (ds1wm_data->is_hw_big_endian) {
> +		switch (ds1wm_data->bus_shift) {
> +		case 0:
> +			iowrite8(val, ds1wm_data->map + (reg << 0));
> +			break;
> +		case 1:
> +			iowrite16be((u16)val, ds1wm_data->map+(reg<<1));
> +			break;
> +		case 2:
> +			iowrite32be((u32)val, ds1wm_data->map+(reg<<2));
> +			break;
> +		}
> +	} else {
> +		switch (ds1wm_data->bus_shift) {
> +		case 0:
> +			iowrite8(val, ds1wm_data->map + (reg << 0));
> +			break;
> +		case 1:
> +			iowrite16((u16) val, ds1wm_data->map+(reg << 1));
> +			break;
> +		case 2:
> +			iowrite32((u32) val, ds1wm_data->map+(reg << 2));
> +			break;
> +		}
> +	}
>  }
>  
>  static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
>  {
> -	return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
> +
> +	u32 val = 0;
> +
> +	if (ds1wm_data->is_hw_big_endian) {
> +		switch (ds1wm_data->bus_shift) {
> +		case 0:
> +			val = ioread8(ds1wm_data->map + (reg << 0));
> +			break;
> +		case 1:
> +			val = ioread16be(ds1wm_data->map + (reg << 1));
> +			break;
> +		case 2:
> +			val = ioread32be(ds1wm_data->map + (reg << 2));
> +			break;
> +		}
> +	} else {
> +		switch (ds1wm_data->bus_shift) {
> +		case 0:
> +			val = ioread8(ds1wm_data->map + (reg << 0));
> +			break;
> +		case 1:
> +			val = ioread16(ds1wm_data->map + (reg << 1));
> +			break;
> +		case 2:
> +			val = ioread32(ds1wm_data->map + (reg << 2));
> +			break;
> +		}
> +	}
> +	dev_dbg(&ds1wm_data->pdev->dev,
> +		"ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val);
> +	return (u8) val;
>  }
>  
>  
> @@ -473,9 +528,6 @@ static int ds1wm_probe(struct platform_device *pdev)
>  	if (!ds1wm_data->map)
>  		return -ENOMEM;
>  
> -	/* calculate bus shift from mem resource */
> -	ds1wm_data->bus_shift = resource_size(res) >> 3;
> -
>  	ds1wm_data->pdev = pdev;
>  	ds1wm_data->cell = mfd_get_cell(pdev);
>  	if (!ds1wm_data->cell)
> @@ -484,6 +536,26 @@ static int ds1wm_probe(struct platform_device *pdev)
>  	if (!plat)
>  		return -ENODEV;
>  
> +	/* how many bits to shift register number to get register offset */
> +	if (plat->bus_shift > 2) {
> +		dev_err(&ds1wm_data->pdev->dev,
> +			"illegal bus shift %d, not written",
> +			ds1wm_data->bus_shift);
> +		return -EINVAL;
> +	}
> +
> +	ds1wm_data->bus_shift = plat->bus_shift;
> +	/* make sure resource has space for 8 registers */
> +	if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
> +		dev_err(&ds1wm_data->pdev->dev,
> +			"memory resource size %d to small, should be %d\n",
> +			(int) resource_size(res),
> +			8 << ds1wm_data->bus_shift);
> +		return -EINVAL;
> +	}
> +
> +	ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian;
> +
>  	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
>  	if (!res)
>  		return -ENXIO;
> diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
> index 38a372a..4efd626 100644
> --- a/include/linux/mfd/ds1wm.h
> +++ b/include/linux/mfd/ds1wm.h
> @@ -3,6 +3,7 @@
>  struct ds1wm_driver_data {
>  	int active_high;
>  	int clock_rate;
> +
>  	/* in milliseconds, the amount of time to */
>  	/* sleep following a reset pulse. Zero    */
>  	/* should work if your bus devices recover*/
> @@ -10,4 +11,12 @@ struct ds1wm_driver_data {
>  	/* ds1wm implements the precise timings of*/
>  	/* a reset pulse/presence detect sequence.*/
>  	unsigned int reset_recover_delay;
> +
> +	/* Say 1 here for big endian Hardware */
> +	/* (only relevant with bus-shift > 0 */
> +	int is_hw_big_endian;

bool?

And who is setting this?  What is the initial value?

> +
> +	/* left shift of register number to get register address offsett */
> +	/* only 0,1,2 allowed for 8,16 or 32 bit bus width respectively */
> +	unsigned int bus_shift;

u8?

Please use multi-line comments in the correct format, checkpatch.pl
should have complained about these, right?

thanks,

greg k-h

Re: [PATCH v3 2/4] w1: ds1wm: add level interrupt modes

[Greg Kroah-Hartman]

On Tue, Jul 18, 2017 at 01:26:51PM +0200, Johannes Poehlmann wrote:
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> ---
>  drivers/w1/masters/ds1wm.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 

I can not take a patch without any changelog text at all, sorry.  Please
write something as obviously the patch does do something...

thanks,

greg k-h

Re: [PATCH v3 3/4] w1: ds1wm: silence interrupts on HW before claiming the interrupt

[Greg Kroah-Hartman]

On Tue, Jul 18, 2017 at 01:26:52PM +0200, Johannes Poehlmann wrote:
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> ---
>  drivers/w1/masters/ds1wm.c | 6 ++++++
>  1 file changed, 6 insertions(+)

Same here, I need a changelog text.

thanks,

greg k-h

Re: [PATCH v3 4/4] w1: ds1wm: add messages to make incorporation in mfd-drivers easier

[Greg Kroah-Hartman]

On Tue, Jul 18, 2017 at 01:26:53PM +0200, Johannes Poehlmann wrote:
> Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
> ---
>  drivers/w1/masters/ds1wm.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)

And here as well.



> 
> diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
> index 7cb4460..76b4573 100644
> --- a/drivers/w1/masters/ds1wm.c
> +++ b/drivers/w1/masters/ds1wm.c
> @@ -580,8 +580,14 @@ static int ds1wm_probe(struct platform_device *pdev)
>  
>  	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
>  			IRQF_SHARED, "ds1wm", ds1wm_data);
> -	if (ret)
> +	if (ret) {
> +		dev_err(&ds1wm_data->pdev->dev,
> +			"devm_request_irq %d failed with errno %d\n",
> +			ds1wm_data->irq,
> +			ret);
> +
>  		return ret;
> +	}
>  
>  	ds1wm_up(ds1wm_data);
>  
> @@ -591,6 +597,13 @@ static int ds1wm_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err;
>  
> +	dev_info(&ds1wm_data->pdev->dev,
> +		"ds1wm: probe successful, IAS: %d, rec.delay: %d, clockrate: %d, bus-shift: %d, is Hw Big Endian: %d\n",
> +		plat->active_high,
> +		plat->reset_recover_delay,
> +		plat->clock_rate,
> +		ds1wm_data->bus_shift,
> +		ds1wm_data->is_hw_big_endian);

Ick, why be so noisy?  Drivers should be quiet unless something bad
happens, they should not print random things when devices are found if
at all possible.

thanks,

greg k-h

[PATCH v4 0/5] w1: ds1wm: register access patch

[Johannes Poehlmann]

To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
with a register offset multiplier of 4 I had to make some changes to

       drivers/w1/masters/ds1wm.c
and    include/linux/mfd/ds1wm.h.

Version 2 of the patchset 

o fixes kbuild reported build problems on x86_64 
o removes unobvious shift constants
o moves shift value checking into the probe function
o rename variable (fix 'CamelCase' style)

Version 3 of the patchset
o rebased on v4.13-rc1 and resent to lkml

Version 4 of the patchset
   work on Greg Kroah-Hartmanns comments:
o added changelog to every patch
o separate one big patch into two
o use bool
o use blockcomments
o dev_dbg instead of dev_info 
o rebased to v4.13-rc2

Johannes Poehlmann (5):
  w1: ds1wm: fix register offset (bus shift) calculation
  w1: ds1wm: make endian clean and use standard io memory accessors
  w1: ds1wm: add level interrupt modes
  w1: ds1wm: silence interrupts on HW before claiming the interrupt
  w1: ds1wm: add messages to make incorporation in mfd-drivers easier

 drivers/w1/masters/ds1wm.c | 108 ++++++++++++++++++++++++++++++++++++++++++---
 include/linux/mfd/ds1wm.h  |  29 +++++++++---
 2 files changed, 123 insertions(+), 14 deletions(-)

-- 
2.1.4

[PATCH v4 1/5] w1: ds1wm: fix register offset (bus shift) calculation

[Johannes Poehlmann]

Replace incorrect register offsett calculation by
direct configuration of bus_shift in mfd-cell.

Indirect definition of address-shift by resource size
was unobvious and was wrong (should have used a binary log).

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 23 +++++++++++++++++++----
 include/linux/mfd/ds1wm.h  | 24 +++++++++++++++++-------
 2 files changed, 36 insertions(+), 11 deletions(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index fd2e9da..401e53e 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -95,7 +95,7 @@ static struct {
 
 struct ds1wm_data {
 	void     __iomem *map;
-	int      bus_shift; /* # of shifts to calc register offsets */
+	unsigned int      bus_shift; /* # of shifts to calc register offsets */
 	struct platform_device *pdev;
 	const struct mfd_cell   *cell;
 	int      irq;
@@ -473,9 +473,6 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (!ds1wm_data->map)
 		return -ENOMEM;
 
-	/* calculate bus shift from mem resource */
-	ds1wm_data->bus_shift = resource_size(res) >> 3;
-
 	ds1wm_data->pdev = pdev;
 	ds1wm_data->cell = mfd_get_cell(pdev);
 	if (!ds1wm_data->cell)
@@ -484,6 +481,24 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (!plat)
 		return -ENODEV;
 
+	/* how many bits to shift register number to get register offset */
+	if (plat->bus_shift > 2) {
+		dev_err(&ds1wm_data->pdev->dev,
+			"illegal bus shift %d, not written",
+			ds1wm_data->bus_shift);
+		return -EINVAL;
+	}
+
+	ds1wm_data->bus_shift = plat->bus_shift;
+	/* make sure resource has space for 8 registers */
+	if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
+		dev_err(&ds1wm_data->pdev->dev,
+			"memory resource size %d to small, should be %d\n",
+			(int)resource_size(res),
+			8 << ds1wm_data->bus_shift);
+		return -EINVAL;
+	}
+
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (!res)
 		return -ENXIO;
diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
index 38a372a..79a01e8 100644
--- a/include/linux/mfd/ds1wm.h
+++ b/include/linux/mfd/ds1wm.h
@@ -1,13 +1,23 @@
-/* MFD cell driver data for the DS1WM driver */
+/* MFD cell driver data for the DS1WM driver
+ *
+ * to be defined in the MFD device that is
+ * using this driver for one of his sub devices
+ */
 
 struct ds1wm_driver_data {
 	int active_high;
 	int clock_rate;
-	/* in milliseconds, the amount of time to */
-	/* sleep following a reset pulse. Zero    */
-	/* should work if your bus devices recover*/
-	/* time respects the 1-wire spec since the*/
-	/* ds1wm implements the precise timings of*/
-	/* a reset pulse/presence detect sequence.*/
+	/* in milliseconds, the amount of time to
+	 * sleep following a reset pulse. Zero
+	 * should work if your bus devices recover
+	 * time respects the 1-wire spec since the
+	 * ds1wm implements the precise timings of
+	 * a reset pulse/presence detect sequence.
+	 */
 	unsigned int reset_recover_delay;
+
+	/* left shift of register number to get register address offsett.
+	 * Only 0,1,2 allowed for 8,16 or 32 bit bus width respectively
+	 */
+	unsigned int bus_shift;
 };
-- 
2.1.4

[PATCH v4 2/5] w1: ds1wm: make endian clean and use standard io memory accessors

[Johannes Poehlmann]

o Make endian clean, make HW-endianness configurable.

o Use ioread*, iowrite* instead of __raw_readb,__raw_writeb
  to also use memory-barriers when accessing HW-registers.
  We do not want reordering to happen here.

Both changes are tightly coupled, so I do them in one patch

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 60 ++++++++++++++++++++++++++++++++++++++++++++--
 include/linux/mfd/ds1wm.h  |  5 ++++
 2 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 401e53e..d15575d 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -96,6 +96,7 @@ static struct {
 struct ds1wm_data {
 	void     __iomem *map;
 	unsigned int      bus_shift; /* # of shifts to calc register offsets */
+	bool      is_hw_big_endian;
 	struct platform_device *pdev;
 	const struct mfd_cell   *cell;
 	int      irq;
@@ -115,12 +116,65 @@ struct ds1wm_data {
 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 					u8 val)
 {
-	__raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
+	if (ds1wm_data->is_hw_big_endian) {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			iowrite8(val, ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			iowrite16be((u16)val, ds1wm_data->map + (reg << 1));
+			break;
+		case 2:
+			iowrite32be((u32)val, ds1wm_data->map + (reg << 2));
+			break;
+		}
+	} else {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			iowrite8(val, ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			iowrite16((u16)val, ds1wm_data->map + (reg << 1));
+			break;
+		case 2:
+			iowrite32((u32)val, ds1wm_data->map + (reg << 2));
+			break;
+		}
+	}
 }
 
 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 {
-	return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
+	u32 val = 0;
+
+	if (ds1wm_data->is_hw_big_endian) {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			val = ioread8(ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			val = ioread16be(ds1wm_data->map + (reg << 1));
+			break;
+		case 2:
+			val = ioread32be(ds1wm_data->map + (reg << 2));
+			break;
+		}
+	} else {
+		switch (ds1wm_data->bus_shift) {
+		case 0:
+			val = ioread8(ds1wm_data->map + (reg << 0));
+			break;
+		case 1:
+			val = ioread16(ds1wm_data->map + (reg << 1));
+			break;
+		case 2:
+			val = ioread32(ds1wm_data->map + (reg << 2));
+			break;
+		}
+	}
+	dev_dbg(&ds1wm_data->pdev->dev,
+		"ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val);
+	return (u8)val;
 }
 
 
@@ -499,6 +553,8 @@ static int ds1wm_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian;
+
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (!res)
 		return -ENXIO;
diff --git a/include/linux/mfd/ds1wm.h b/include/linux/mfd/ds1wm.h
index 79a01e8..2227c6a 100644
--- a/include/linux/mfd/ds1wm.h
+++ b/include/linux/mfd/ds1wm.h
@@ -16,6 +16,11 @@ struct ds1wm_driver_data {
 	 */
 	unsigned int reset_recover_delay;
 
+	/* Say 1 here for big endian Hardware
+	 * (only relevant with bus-shift > 0
+	 */
+	bool is_hw_big_endian;
+
 	/* left shift of register number to get register address offsett.
 	 * Only 0,1,2 allowed for 8,16 or 32 bit bus width respectively
 	 */
-- 
2.1.4

[PATCH v4 3/5] w1: ds1wm: add level interrupt modes

[Johannes Poehlmann]

w1: ds1wm: add level interrupt modes

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index d15575d..f8a3ba0 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -566,6 +566,10 @@ static int ds1wm_probe(struct platform_device *pdev)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 	if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
+	if (res->flags & IORESOURCE_IRQ_HIGHLEVEL)
+		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_HIGH);
+	if (res->flags & IORESOURCE_IRQ_LOWLEVEL)
+		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_LOW);
 
 	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
 			IRQF_SHARED, "ds1wm", ds1wm_data);
-- 
2.1.4

[PATCH v4 4/5] w1: ds1wm: silence interrupts on HW before claiming the interrupt

[Johannes Poehlmann]

w1: ds1wm: silence interrupts on HW before claiming the interrupt.
This way avoid possible invalid interrupts in the initialization phase.

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index f8a3ba0..5314379 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -509,6 +509,7 @@ static int ds1wm_probe(struct platform_device *pdev)
 	struct ds1wm_driver_data *plat;
 	struct resource *res;
 	int ret;
+	u8 inten;
 
 	if (!pdev)
 		return -ENODEV;
@@ -562,6 +563,11 @@ static int ds1wm_probe(struct platform_device *pdev)
 	ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
 	ds1wm_data->reset_recover_delay = plat->reset_recover_delay;
 
+	/* Mask interrupts, set IAS before claiming interrupt */
+	inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
+	ds1wm_write_register(ds1wm_data,
+		DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
+
 	if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 		irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 	if (res->flags & IORESOURCE_IRQ_LOWEDGE)
-- 
2.1.4

[PATCH v4 5/5] w1: ds1wm: add messages to make incorporation in mfd-drivers easier

[Johannes Poehlmann]

w1: ds1wm: add messages to make incorporation in mfd-drivers easier

Signed-off-by: Johannes Poehlmann <johannes.poehlmann@izt-labs.de>
Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
---
 drivers/w1/masters/ds1wm.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index 5314379..f661695 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -579,8 +579,14 @@ static int ds1wm_probe(struct platform_device *pdev)
 
 	ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
 			IRQF_SHARED, "ds1wm", ds1wm_data);
-	if (ret)
+	if (ret) {
+		dev_err(&ds1wm_data->pdev->dev,
+			"devm_request_irq %d failed with errno %d\n",
+			ds1wm_data->irq,
+			ret);
+
 		return ret;
+	}
 
 	ds1wm_up(ds1wm_data);
 
@@ -590,6 +596,13 @@ static int ds1wm_probe(struct platform_device *pdev)
 	if (ret)
 		goto err;
 
+	dev_dbg(&ds1wm_data->pdev->dev,
+		"ds1wm: probe successful, IAS: %d, rec.delay: %d, clockrate: %d, bus-shift: %d, is Hw Big Endian: %d\n",
+		plat->active_high,
+		plat->reset_recover_delay,
+		plat->clock_rate,
+		ds1wm_data->bus_shift,
+		ds1wm_data->is_hw_big_endian);
 	return 0;
 
 err:
-- 
2.1.4

Re: [PATCH v4 0/5] w1: ds1wm: register access patch

[Evgeniy Polyakov]

Hi everyone

25.07.2017, 14:27, "Johannes Poehlmann" <johannes.poehlmann@izt-labs.de>:
> To make the ds1wm driver work on a powerpc architecture (big endian, 32bit)
> with a register offset multiplier of 4 I had to make some changes to

> Version 4 of the patchset
>    work on Greg Kroah-Hartmanns comments:
> o added changelog to every patch
> o separate one big patch into two
> o use bool
> o use blockcomments
> o dev_dbg instead of dev_info
> o rebased to v4.13-rc2

Greg, please pull this series named [PATCH v4 ...] w1: ds1wm ... into the tree, it looks ok