* [PATCH v2 0/3] RK356x/Quartz64 Model A SPI @ 2021-11-27 14:19 Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli ` (3 more replies) 0 siblings, 4 replies; 8+ messages in thread From: Nicolas Frattaroli @ 2021-11-27 14:19 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Nicolas Frattaroli, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Changes in v2: - sort properties in rk356x.dtsi correctly - remove pinctrl-1 line from rk356x.dtsi as it refers to non-mainline stuff Original cover letter: The first patch of this series adds a compatible for rk3568-spi to the DT bindings. The second adds the SPI nodes for RK3566 and RK3568 SoCs. The nodes were lifted from the downstream vendor kernel's devicetree, and were double-checked for correctness. The third patch sets up the broken-out SPI pins on the Quartz64 Model A; they use the "m1" set of the pins, not the "m0" set. I assume the "m" stands for "mux". I've tested both patches by connecting an MCP2515 SPI CAN bus controller to the spi pins, which initialised fine. Regards, Nicolas Frattaroli Nicolas Frattaroli (3): dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible arm64: dts: rockchip: Add spi nodes on rk356x arm64: dts: rockchip: Add spi1 pins on Quartz64 A .../devicetree/bindings/spi/spi-rockchip.yaml | 1 + .../boot/dts/rockchip/rk3566-quartz64-a.dts | 5 ++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 +++++++++++++++++++ 3 files changed, 70 insertions(+) -- 2.34.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible 2021-11-27 14:19 [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli @ 2021-11-27 14:19 ` Nicolas Frattaroli 2021-11-29 12:01 ` Mark Brown 2021-11-27 14:19 ` [PATCH v2 2/3] arm64: dts: rockchip: Add spi nodes on rk356x Nicolas Frattaroli ` (2 subsequent siblings) 3 siblings, 1 reply; 8+ messages in thread From: Nicolas Frattaroli @ 2021-11-27 14:19 UTC (permalink / raw) To: Mark Brown, Rob Herring, Heiko Stuebner Cc: Nicolas Frattaroli, linux-spi, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel This adds a compatible string for the SPI controller found on the RK3566 and RK3568 SoCs. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> --- Documentation/devicetree/bindings/spi/spi-rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml index 7f987e79337c..52a78a2e362e 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml @@ -33,6 +33,7 @@ properties: - rockchip,rk3328-spi - rockchip,rk3368-spi - rockchip,rk3399-spi + - rockchip,rk3568-spi - rockchip,rv1126-spi - const: rockchip,rk3066-spi -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible 2021-11-27 14:19 ` [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli @ 2021-11-29 12:01 ` Mark Brown 0 siblings, 0 replies; 8+ messages in thread From: Mark Brown @ 2021-11-29 12:01 UTC (permalink / raw) To: Nicolas Frattaroli Cc: Rob Herring, Heiko Stuebner, linux-spi, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel [-- Attachment #1: Type: text/plain, Size: 493 bytes --] On Sat, Nov 27, 2021 at 03:19:07PM +0100, Nicolas Frattaroli wrote: > This adds a compatible string for the SPI controller found on > the RK3566 and RK3568 SoCs. Please submit patches using subject lines reflecting the style for the subsystem, this makes it easier for people to identify relevant patches. Look at what existing commits in the area you're changing are doing and make sure your subject lines visually resemble what they're doing. There's no need to resubmit to fix this alone. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] arm64: dts: rockchip: Add spi nodes on rk356x 2021-11-27 14:19 [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli @ 2021-11-27 14:19 ` Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A Nicolas Frattaroli 2021-12-12 12:40 ` (subset) [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Heiko Stuebner 3 siblings, 0 replies; 8+ messages in thread From: Nicolas Frattaroli @ 2021-11-27 14:19 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Nicolas Frattaroli, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel This adds the four spi nodes (spi0, spi1, spi2, spi3) to the rk356x dtsi. These are from the downstream device tree, though I have double-checked that their interrupts and DMA numbers are correct. I have also tested spi1 with an SPI device. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 46d9552f6028..a058a9e9d5d7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -39,6 +39,10 @@ aliases { serial7 = &uart7; serial8 = &uart8; serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; }; cpus { @@ -742,6 +746,66 @@ wdt: watchdog@fe600000 { clock-names = "tclk", "pclk"; }; + spi0: spi@fe610000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@fe650000 { compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; reg = <0x0 0xfe650000 0x0 0x100>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A 2021-11-27 14:19 [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 2/3] arm64: dts: rockchip: Add spi nodes on rk356x Nicolas Frattaroli @ 2021-11-27 14:19 ` Nicolas Frattaroli 2021-11-27 15:29 ` Johan Jonker 2021-12-12 12:40 ` (subset) [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Heiko Stuebner 3 siblings, 1 reply; 8+ messages in thread From: Nicolas Frattaroli @ 2021-11-27 14:19 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Nicolas Frattaroli, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The Quartz64 Model A has the SPI pins broken out on its pin header. The actual pins being used though are not the m0 variant, but the m1 variant, which also lacks the cs1 pin. This commit overrides pinctrl-0 accordingly for this board. spi1 is intentionally left disabled, as anyone wishing to add SPI devices needs to edit the dts anyway, and the pins are more useful as GPIOs for the rest of the users. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 4d4b2a301b1a..166399b7f13f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -509,6 +509,11 @@ &spdif { status = "okay"; }; +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A 2021-11-27 14:19 ` [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A Nicolas Frattaroli @ 2021-11-27 15:29 ` Johan Jonker 2021-11-27 15:40 ` Nicolas Frattaroli 0 siblings, 1 reply; 8+ messages in thread From: Johan Jonker @ 2021-11-27 15:29 UTC (permalink / raw) To: Nicolas Frattaroli, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 11/27/21 3:19 PM, Nicolas Frattaroli wrote: > The Quartz64 Model A has the SPI pins broken out on its pin > header. The actual pins being used though are not the m0 > variant, but the m1 variant, which also lacks the cs1 pin. > > This commit overrides pinctrl-0 accordingly for this board. > > spi1 is intentionally left disabled, as anyone wishing to add > SPI devices needs to edit the dts anyway, and the pins are more > useful as GPIOs for the rest of the users. > > Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> > --- > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index 4d4b2a301b1a..166399b7f13f 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -509,6 +509,11 @@ &spdif { > status = "okay"; > }; > > +&spi1 { > + pinctrl-names = "default"; With the removal off pinctrl-1 the pinctrl-names property is already correctly defined. + spi1: spi@fe620000 { + compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; > + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; > +}; > + > &tsadc { > /* tshut mode 0:CRU 1:GPIO */ > rockchip,hw-tshut-mode = <1>; > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A 2021-11-27 15:29 ` Johan Jonker @ 2021-11-27 15:40 ` Nicolas Frattaroli 0 siblings, 0 replies; 8+ messages in thread From: Nicolas Frattaroli @ 2021-11-27 15:40 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner, Johan Jonker Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On Samstag, 27. November 2021 16:29:33 CET Johan Jonker wrote: > > On 11/27/21 3:19 PM, Nicolas Frattaroli wrote: > > The Quartz64 Model A has the SPI pins broken out on its pin > > header. The actual pins being used though are not the m0 > > variant, but the m1 variant, which also lacks the cs1 pin. > > > > This commit overrides pinctrl-0 accordingly for this board. > > > > spi1 is intentionally left disabled, as anyone wishing to add > > SPI devices needs to edit the dts anyway, and the pins are more > > useful as GPIOs for the rest of the users. > > > > Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> > > --- > > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index 4d4b2a301b1a..166399b7f13f 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -509,6 +509,11 @@ &spdif { > > status = "okay"; > > }; > > > > +&spi1 { > > > + pinctrl-names = "default"; > > With the removal off pinctrl-1 the pinctrl-names property is already > correctly defined. > If it ever gets re-added in the future, it no longer is, so it's better to be explicit right now than to risk one board breaking in the future when the SoC's definition changes. Regards, Nicolas Frattaroli ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: (subset) [PATCH v2 0/3] RK356x/Quartz64 Model A SPI 2021-11-27 14:19 [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli ` (2 preceding siblings ...) 2021-11-27 14:19 ` [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A Nicolas Frattaroli @ 2021-12-12 12:40 ` Heiko Stuebner 3 siblings, 0 replies; 8+ messages in thread From: Heiko Stuebner @ 2021-12-12 12:40 UTC (permalink / raw) To: Rob Herring, Nicolas Frattaroli Cc: Heiko Stuebner, linux-arm-kernel, linux-kernel, devicetree, linux-rockchip On Sat, 27 Nov 2021 15:19:06 +0100, Nicolas Frattaroli wrote: > Changes in v2: > - sort properties in rk356x.dtsi correctly > - remove pinctrl-1 line from rk356x.dtsi as it refers to > non-mainline stuff > > Original cover letter: > > [...] Applied, thanks! [2/3] arm64: dts: rockchip: Add spi nodes on rk356x commit: aaa552d84580e9213d0e2bf0f9243477d1227bdd [3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A commit: ea1847c09c34234c2980b99b6bb732a55447c33f Best regards, -- Heiko Stuebner <heiko@sntech.de> ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-12-12 12:41 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-11-27 14:19 [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 1/3] dt-bindings: spi: spi-rockchip: Add rk3568-spi compatible Nicolas Frattaroli 2021-11-29 12:01 ` Mark Brown 2021-11-27 14:19 ` [PATCH v2 2/3] arm64: dts: rockchip: Add spi nodes on rk356x Nicolas Frattaroli 2021-11-27 14:19 ` [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A Nicolas Frattaroli 2021-11-27 15:29 ` Johan Jonker 2021-11-27 15:40 ` Nicolas Frattaroli 2021-12-12 12:40 ` (subset) [PATCH v2 0/3] RK356x/Quartz64 Model A SPI Heiko Stuebner
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