* [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers
@ 2016-07-29 0:48 Andrey Smirnov
2016-07-29 0:48 ` [RESEND PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register Andrey Smirnov
2016-07-29 8:30 ` [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Arnd Bergmann
0 siblings, 2 replies; 4+ messages in thread
From: Andrey Smirnov @ 2016-07-29 0:48 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Andrey Smirnov, Russell King, Arnd Bergmann, linux-kernel
Replace magic numbers used for L310 Prefetch Control Register
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mm/cache-l2x0.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9f9d542..30e2012 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -716,8 +716,10 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
revision < L310_CACHE_ID_RTL_R3P2) {
u32 val = l2x0_saved_regs.prefetch_ctrl;
/* I don't think bit23 is required here... but iMX6 does so */
- if (val & (BIT(30) | BIT(23))) {
- val &= ~(BIT(30) | BIT(23));
+ if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL |
+ L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) {
+ val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL |
+ L310_PREFETCH_CTRL_DBL_LINEFILL_INCR);
l2x0_saved_regs.prefetch_ctrl = val;
errata[n++] = "752271";
}
--
2.5.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* [RESEND PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register
2016-07-29 0:48 [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Andrey Smirnov
@ 2016-07-29 0:48 ` Andrey Smirnov
2016-07-29 8:30 ` [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Arnd Bergmann
1 sibling, 0 replies; 4+ messages in thread
From: Andrey Smirnov @ 2016-07-29 0:48 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Andrey Smirnov, Russell King, Arnd Bergmann, linux-kernel
As per L2C-310 TRM[1]:
"... You can control this feature using bits 30,27 and 23 of the
Prefetch Control Register. Bit 23 and 27 are only used if you set bit 30
HIGH..."
which means there is no need to clear bit 23 if bit 30 is being cleared.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246e/CJAJACBJ.html
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mm/cache-l2x0.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 30e2012..12c1ba7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -715,11 +715,8 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
if (revision >= L310_CACHE_ID_RTL_R3P0 &&
revision < L310_CACHE_ID_RTL_R3P2) {
u32 val = l2x0_saved_regs.prefetch_ctrl;
- /* I don't think bit23 is required here... but iMX6 does so */
- if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL |
- L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) {
- val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL |
- L310_PREFETCH_CTRL_DBL_LINEFILL_INCR);
+ if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) {
+ val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
l2x0_saved_regs.prefetch_ctrl = val;
errata[n++] = "752271";
}
--
2.5.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers
2016-07-29 0:48 [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Andrey Smirnov
2016-07-29 0:48 ` [RESEND PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register Andrey Smirnov
@ 2016-07-29 8:30 ` Arnd Bergmann
1 sibling, 0 replies; 4+ messages in thread
From: Arnd Bergmann @ 2016-07-29 8:30 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: linux-arm-kernel, Russell King, linux-kernel
On Thursday, July 28, 2016 5:48:41 PM CEST Andrey Smirnov wrote:
> Replace magic numbers used for L310 Prefetch Control Register
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>
Please send the two patches the patch tracker at
http://www.arm.linux.org.uk/developer/patches/
Arnd
^ permalink raw reply [flat|nested] 4+ messages in thread
* [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers
@ 2016-06-28 4:34 Andrey Smirnov
0 siblings, 0 replies; 4+ messages in thread
From: Andrey Smirnov @ 2016-06-28 4:34 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Andrey Smirnov, Russell King, Arnd Bergmann,
Uwe Kleine-König, linux-kernel
Replace magic numbers used for L310 Prefetch Control Register
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mm/cache-l2x0.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9f9d542..30e2012 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -716,8 +716,10 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
revision < L310_CACHE_ID_RTL_R3P2) {
u32 val = l2x0_saved_regs.prefetch_ctrl;
/* I don't think bit23 is required here... but iMX6 does so */
- if (val & (BIT(30) | BIT(23))) {
- val &= ~(BIT(30) | BIT(23));
+ if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL |
+ L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) {
+ val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL |
+ L310_PREFETCH_CTRL_DBL_LINEFILL_INCR);
l2x0_saved_regs.prefetch_ctrl = val;
errata[n++] = "752271";
}
--
2.5.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2016-07-29 0:48 [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Andrey Smirnov
2016-07-29 0:48 ` [RESEND PATCH 2/2] ARM: cache-l2x0.c: Do not clear bit 23 in prefetch control register Andrey Smirnov
2016-07-29 8:30 ` [RESEND PATCH 1/2] ARM: cache-l2x0.c: Replace magic numbers Arnd Bergmann
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