From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, acme@kernel.org,
tglx@linutronix.de, bp@alien8.de, namhyung@kernel.org,
jolsa@redhat.com, ak@linux.intel.com, yao.jin@linux.intel.com,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
ricardo.neri-calderon@linux.intel.com
Subject: Re: [PATCH V5 16/25] perf/x86: Register hybrid PMUs
Date: Fri, 9 Apr 2021 09:50:20 -0400 [thread overview]
Message-ID: <41c7b4ec-b742-2f7c-9991-7b23c9971dc6@linux.intel.com> (raw)
In-Reply-To: <YG/7BgFaRC/Eos76@hirez.programming.kicks-ass.net>
On 4/9/2021 2:58 AM, Peter Zijlstra wrote:
> On Mon, Apr 05, 2021 at 08:10:58AM -0700, kan.liang@linux.intel.com wrote:
>> @@ -2089,9 +2119,46 @@ static int __init init_hw_perf_events(void)
>> if (err)
>> goto out1;
>>
>> - err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
>> - if (err)
>> - goto out2;
>> + if (!is_hybrid()) {
>> + err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
>> + if (err)
>> + goto out2;
>> + } else {
>> + u8 cpu_type = get_this_hybrid_cpu_type();
>> + struct x86_hybrid_pmu *hybrid_pmu;
>> + bool registered = false;
>> + int i;
>> +
>> + if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
>> + cpu_type = x86_pmu.get_hybrid_cpu_type();
>> +
>> + for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
>> + hybrid_pmu = &x86_pmu.hybrid_pmu[i];
>> +
>> + hybrid_pmu->pmu = pmu;
>> + hybrid_pmu->pmu.type = -1;
>> + hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
>> + hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
>> +
>> + err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
>> + (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
>> + if (err)
>> + continue;
>> +
>> + if (cpu_type == hybrid_pmu->cpu_type)
>> + x86_pmu_update_cpu_context(&hybrid_pmu->pmu, raw_smp_processor_id());
>> +
>> + registered = true;
>> + }
>> +
>> + if (!registered) {
>> + pr_warn("Failed to register hybrid PMUs\n");
>> + kfree(x86_pmu.hybrid_pmu);
>> + x86_pmu.hybrid_pmu = NULL;
>> + x86_pmu.num_hybrid_pmus = 0;
>> + goto out2;
>> + }
>
> I don't think this is quite right. registered will be true even if one
> fails, while I think you meant to only have it true when all (both)
> types registered correctly.
No, I mean that perf error out only when all types fail to be registered.
For the case (1 failure, 1 success), users can still access the
registered PMU.
When a CPU belongs to the unregistered PMU online, a warning will be
displayed. Because in init_hybrid_pmu(), we will check the PMU type
before update the CPU mask.
if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
cpuc->pmu = NULL;
return false;
}
Thanks,
Kan
next prev parent reply other threads:[~2021-04-09 13:50 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-05 15:10 [PATCH V5 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-04-05 15:10 ` [PATCH V5 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-04-05 15:10 ` [PATCH V5 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU kan.liang
2021-04-05 15:10 ` [PATCH V5 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-04-05 15:10 ` [PATCH V5 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-04-08 13:40 ` Peter Zijlstra
2021-04-08 14:19 ` Peter Zijlstra
2021-04-08 18:24 ` Liang, Kan
2021-04-08 17:00 ` Peter Zijlstra
2021-04-08 17:40 ` Liang, Kan
2021-04-05 15:10 ` [PATCH V5 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-04-05 15:10 ` [PATCH V5 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-04-05 15:10 ` [PATCH V5 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-04-05 15:10 ` [PATCH V5 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-04-08 14:22 ` Peter Zijlstra
2021-04-05 15:10 ` [PATCH V5 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-04-05 15:10 ` [PATCH V5 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-04-05 15:10 ` [PATCH V5 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-04-05 15:10 ` [PATCH V5 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-04-05 15:10 ` [PATCH V5 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-04-05 15:10 ` [PATCH V5 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-04-05 15:10 ` [PATCH V5 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-04-05 15:10 ` [PATCH V5 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-04-09 6:58 ` Peter Zijlstra
2021-04-09 13:50 ` Liang, Kan [this message]
2021-04-09 15:45 ` Peter Zijlstra
2021-04-09 15:47 ` Liang, Kan
2021-04-05 15:10 ` [PATCH V5 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-04-05 15:11 ` [PATCH V5 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-04-05 15:11 ` [PATCH V5 19/25] perf/x86: Support filter_match callback kan.liang
2021-04-05 15:11 ` [PATCH V5 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-04-05 15:11 ` [PATCH V5 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-04-09 9:21 ` Peter Zijlstra
2021-04-09 15:24 ` Liang, Kan
2021-04-09 15:51 ` Peter Zijlstra
2021-04-05 15:11 ` [PATCH V5 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-04-05 15:11 ` [PATCH V5 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-04-09 9:24 ` Peter Zijlstra
2021-04-09 14:35 ` Liang, Kan
2021-04-05 15:11 ` [PATCH V5 24/25] perf/x86/cstate: " kan.liang
2021-04-05 15:11 ` [PATCH V5 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang
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