From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: mingo@kernel.org, linux-kernel@vger.kernel.org, acme@kernel.org,
tglx@linutronix.de, bp@alien8.de, namhyung@kernel.org,
jolsa@redhat.com, ak@linux.intel.com, yao.jin@linux.intel.com,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
ricardo.neri-calderon@linux.intel.com
Subject: Re: [PATCH V5 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities
Date: Thu, 8 Apr 2021 13:40:41 -0400 [thread overview]
Message-ID: <42ca6320-dca8-ae58-a764-037a46936d78@linux.intel.com> (raw)
In-Reply-To: <YG82scZuZAsxj2js@hirez.programming.kicks-ass.net>
On 4/8/2021 1:00 PM, Peter Zijlstra wrote:
> On Mon, Apr 05, 2021 at 08:10:46AM -0700, kan.liang@linux.intel.com wrote:
>> +#define is_hybrid() (!!x86_pmu.num_hybrid_pmus)
>
> Given this is sprinkled all over the place, can you make this a
> static_key_false + static_branch_unlikely() such that the hybrid case is
> out-of-line?
>
Sure, I will add a new static_key_false "perf_is_hybrid" to indicate a
hybrid system as below (not test yet).
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index f8d1222..bd6412e 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -54,6 +54,7 @@ DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
+DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
/*
* This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2b553d9..7cef3cd 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6119,6 +6119,7 @@ __init int intel_pmu_init(void)
GFP_KERNEL);
if (!x86_pmu.hybrid_pmu)
return -ENOMEM;
+ static_branch_enable(&perf_is_hybrid);
x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS;
x86_pmu.late_ack = true;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index bfbecde..d6383d1 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -663,8 +663,8 @@ static __always_inline struct x86_hybrid_pmu
*hybrid_pmu(struct pmu *pmu)
return container_of(pmu, struct x86_hybrid_pmu, pmu);
}
-/* The number of hybrid PMUs implies whether it's a hybrid system */
-#define is_hybrid() (!!x86_pmu.num_hybrid_pmus)
+extern struct static_key_false perf_is_hybrid;
+#define is_hybrid() static_branch_unlikely(&perf_is_hybrid)
#define hybrid(_pmu, _field) \
({ \
Thanks,
Kan
next prev parent reply other threads:[~2021-04-08 17:40 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-05 15:10 [PATCH V5 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-04-05 15:10 ` [PATCH V5 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-04-05 15:10 ` [PATCH V5 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU kan.liang
2021-04-05 15:10 ` [PATCH V5 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-04-05 15:10 ` [PATCH V5 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-04-08 13:40 ` Peter Zijlstra
2021-04-08 14:19 ` Peter Zijlstra
2021-04-08 18:24 ` Liang, Kan
2021-04-08 17:00 ` Peter Zijlstra
2021-04-08 17:40 ` Liang, Kan [this message]
2021-04-05 15:10 ` [PATCH V5 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-04-05 15:10 ` [PATCH V5 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-04-05 15:10 ` [PATCH V5 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-04-05 15:10 ` [PATCH V5 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-04-08 14:22 ` Peter Zijlstra
2021-04-05 15:10 ` [PATCH V5 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-04-05 15:10 ` [PATCH V5 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-04-05 15:10 ` [PATCH V5 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-04-05 15:10 ` [PATCH V5 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-04-05 15:10 ` [PATCH V5 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-04-05 15:10 ` [PATCH V5 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-04-05 15:10 ` [PATCH V5 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-04-05 15:10 ` [PATCH V5 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-04-09 6:58 ` Peter Zijlstra
2021-04-09 13:50 ` Liang, Kan
2021-04-09 15:45 ` Peter Zijlstra
2021-04-09 15:47 ` Liang, Kan
2021-04-05 15:10 ` [PATCH V5 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-04-05 15:11 ` [PATCH V5 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-04-05 15:11 ` [PATCH V5 19/25] perf/x86: Support filter_match callback kan.liang
2021-04-05 15:11 ` [PATCH V5 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-04-05 15:11 ` [PATCH V5 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-04-09 9:21 ` Peter Zijlstra
2021-04-09 15:24 ` Liang, Kan
2021-04-09 15:51 ` Peter Zijlstra
2021-04-05 15:11 ` [PATCH V5 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-04-05 15:11 ` [PATCH V5 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-04-09 9:24 ` Peter Zijlstra
2021-04-09 14:35 ` Liang, Kan
2021-04-05 15:11 ` [PATCH V5 24/25] perf/x86/cstate: " kan.liang
2021-04-05 15:11 ` [PATCH V5 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang
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