From: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> To: "Stephen Boyd" <sboyd@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>, "Andreas Färber" <afaerber@suse.de>, "Michael Turquette" <mturquette@baylibre.com>, "Edgar Bernardi Righi" <edgar.righi@lsitec.org.br> Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC Date: Thu, 10 Jun 2021 23:05:21 +0300 [thread overview] Message-ID: <4714d05982b19ac5fec2ed74f54be42d8238e392.1623354574.git.cristian.ciocaltea@gmail.com> (raw) In-Reply-To: <cover.1623354574.git.cristian.ciocaltea@gmail.com> Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Changes in v3: - None Changes in v2: - Added Reviewed-by from Mani drivers/clk/actions/owl-s500.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 61bb224f6330..75b7186185b0 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -305,7 +305,7 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, @@ -317,31 +317,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, -- 2.32.0
next prev parent reply other threads:[~2021-06-10 20:05 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-10 20:05 [PATCH v3 0/6] Improve clock support for Actions " Cristian Ciocaltea 2021-06-10 20:05 ` Cristian Ciocaltea [this message] 2021-06-28 1:46 ` [PATCH v3 1/6] clk: actions: Fix UART clock dividers on Owl " Stephen Boyd 2021-06-10 20:05 ` [PATCH v3 2/6] clk: actions: Fix SD clocks factor table " Cristian Ciocaltea 2021-06-28 1:47 ` Stephen Boyd 2021-06-10 20:05 ` [PATCH v3 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea 2021-06-28 1:47 ` Stephen Boyd 2021-06-10 20:05 ` [PATCH v3 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea 2021-06-11 4:11 ` Manivannan Sadhasivam 2021-06-28 1:47 ` Stephen Boyd 2021-06-10 20:05 ` [PATCH v3 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea 2021-06-28 1:47 ` Stephen Boyd 2021-06-10 20:05 ` [PATCH v3 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea 2021-06-28 1:47 ` Stephen Boyd 2021-06-16 16:06 ` [PATCH v3 0/6] Improve " Cristian Ciocaltea
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