* [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
@ 2021-01-20 19:51 Nishanth Menon
2021-01-20 20:49 ` Suman Anna
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Nishanth Menon @ 2021-01-20 19:51 UTC (permalink / raw)
To: Sudeep Holla, Suman Anna, Dave Gerlach
Cc: Tero Kristo, Rob Herring, linux-kernel, devicetree,
linux-arm-kernel, Nishanth Menon
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/
J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/
J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/
Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/
I have'nt split this patch up for fixes tag primarily because the
basic functionality works and this is an improvement than a critical
fixup to backport for older kernels.
arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +-
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index d84c0bc05023..a9fc1af03f27 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 {
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a53-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 66169bcf7c9a..b7005b803149 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 {
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index cc483f7344af..f0587fde147e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 {
};
pmu: pmu {
- compatible = "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a72-pmu";
/* Recommendation from GIC500 TRM Table A.3 */
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.25.1.377.g2d2118b814c1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
2021-01-20 19:51 [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific Nishanth Menon
@ 2021-01-20 20:49 ` Suman Anna
2021-01-21 10:37 ` Tero Kristo
2021-01-22 12:49 ` Nishanth Menon
2 siblings, 0 replies; 4+ messages in thread
From: Suman Anna @ 2021-01-20 20:49 UTC (permalink / raw)
To: Nishanth Menon, Sudeep Holla, Dave Gerlach
Cc: Tero Kristo, Rob Herring, linux-kernel, devicetree, linux-arm-kernel
On 1/20/21 1:51 PM, Nishanth Menon wrote:
> We can use CPU specific pmu configuration to expose the appropriate
> CPU specific events rather than just the basic generic pmuv3 perf
> events.
>
> Reported-by: Sudeep Holla <sudeep.holla@arm.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
regards
Suman
> ---
>
> AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/
> J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/
> J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/
>
> Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/
>
> I have'nt split this patch up for fixes tag primarily because the
> basic functionality works and this is an improvement than a critical
> fixup to backport for older kernels.
>
> arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +-
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
> index d84c0bc05023..a9fc1af03f27 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
> @@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 {
> };
>
> pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a53-pmu";
> /* Recommendation from GIC500 TRM Table A.3 */
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> index 66169bcf7c9a..b7005b803149 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 {
> };
>
> pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a72-pmu";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index cc483f7344af..f0587fde147e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 {
> };
>
> pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a72-pmu";
> /* Recommendation from GIC500 TRM Table A.3 */
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> };
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
2021-01-20 19:51 [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific Nishanth Menon
2021-01-20 20:49 ` Suman Anna
@ 2021-01-21 10:37 ` Tero Kristo
2021-01-22 12:49 ` Nishanth Menon
2 siblings, 0 replies; 4+ messages in thread
From: Tero Kristo @ 2021-01-21 10:37 UTC (permalink / raw)
To: Nishanth Menon, Sudeep Holla, Suman Anna, Dave Gerlach
Cc: Rob Herring, linux-kernel, devicetree, linux-arm-kernel
On 20/01/2021 21:51, Nishanth Menon wrote:
> We can use CPU specific pmu configuration to expose the appropriate
> CPU specific events rather than just the basic generic pmuv3 perf
> events.
>
> Reported-by: Sudeep Holla <sudeep.holla@arm.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
> ---
>
> AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/
> J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/
> J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/
>
> Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/
>
> I have'nt split this patch up for fixes tag primarily because the
> basic functionality works and this is an improvement than a critical
> fixup to backport for older kernels.
>
> arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +-
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
> index d84c0bc05023..a9fc1af03f27 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
> @@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 {
> };
>
> pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a53-pmu";
> /* Recommendation from GIC500 TRM Table A.3 */
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> index 66169bcf7c9a..b7005b803149 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 {
> };
>
> pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a72-pmu";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index cc483f7344af..f0587fde147e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 {
> };
>
> pmu: pmu {
> - compatible = "arm,armv8-pmuv3";
> + compatible = "arm,cortex-a72-pmu";
> /* Recommendation from GIC500 TRM Table A.3 */
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> };
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
2021-01-20 19:51 [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific Nishanth Menon
2021-01-20 20:49 ` Suman Anna
2021-01-21 10:37 ` Tero Kristo
@ 2021-01-22 12:49 ` Nishanth Menon
2 siblings, 0 replies; 4+ messages in thread
From: Nishanth Menon @ 2021-01-22 12:49 UTC (permalink / raw)
To: Dave Gerlach, Suman Anna, Nishanth Menon, Sudeep Holla
Cc: Tero Kristo, linux-kernel, devicetree, Rob Herring, linux-arm-kernel
On Wed, 20 Jan 2021 13:51:45 -0600, Nishanth Menon wrote:
> We can use CPU specific pmu configuration to expose the appropriate
> CPU specific events rather than just the basic generic pmuv3 perf
> events.
Hi Nishanth Menon,
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/1] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
commit: c72bf319f12803d8c8ddc3dbf54927380fc65b50
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-01-20 19:51 [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific Nishanth Menon
2021-01-20 20:49 ` Suman Anna
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