* [PATCH] tty: serial: uartlite: Specify time for sending chars
@ 2014-05-05 14:48 Michal Simek
2014-05-05 15:03 ` Peter Korsgaard
0 siblings, 1 reply; 5+ messages in thread
From: Michal Simek @ 2014-05-05 14:48 UTC (permalink / raw)
To: linux-kernel
Cc: Michal Simek, Michal Simek, Greg Kroah-Hartman, linux-serial,
arnd, Peter Korsgaard, Grant Likely, Rob Herring, Jiri Slaby
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Xilinx MDM (Microblaze Debug Module) also contains
uart interface via JTAG which is compatible with
uartlite driver. This interface is really slow
that's why timeout is setup to 1s.
Make this time delay not to be cpu speed dependent.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
RFC sent here:
https://lkml.org/lkml/2013/9/30/250
I finally got HW design which is just slow to be able
to test it.
---
drivers/tty/serial/uartlite.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
index 5f90ef24d475..723a6b79cd14 100644
--- a/drivers/tty/serial/uartlite.c
+++ b/drivers/tty/serial/uartlite.c
@@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = {
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
- int i;
u8 val;
+ unsigned long timeout;
/* Spin waiting for TX fifo to have space available */
- for (i = 0; i < 100000; i++) {
+ timeout = jiffies + msecs_to_jiffies(1000);
+ while (1) {
val = uart_in32(ULITE_STATUS, port);
if ((val & ULITE_STATUS_TXFULL) == 0)
break;
+ if (time_after(jiffies, timeout)) {
+ dev_warn(port->dev,
+ "timeout waiting for TX buffer empty\n");
+ break;
+ }
cpu_relax();
}
}
--
1.8.2.3
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] tty: serial: uartlite: Specify time for sending chars
2014-05-05 14:48 [PATCH] tty: serial: uartlite: Specify time for sending chars Michal Simek
@ 2014-05-05 15:03 ` Peter Korsgaard
2014-05-05 18:24 ` Michal Simek
0 siblings, 1 reply; 5+ messages in thread
From: Peter Korsgaard @ 2014-05-05 15:03 UTC (permalink / raw)
To: Michal Simek
Cc: linux-kernel, Michal Simek, Greg Kroah-Hartman, linux-serial,
arnd, Peter Korsgaard, Grant Likely, Rob Herring, Jiri Slaby
>>>>> "Michal" == Michal Simek <michal.simek@xilinx.com> writes:
> Xilinx MDM (Microblaze Debug Module) also contains
> uart interface via JTAG which is compatible with
> uartlite driver. This interface is really slow
> that's why timeout is setup to 1s.
> Make this time delay not to be cpu speed dependent.
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> RFC sent here:
> https://lkml.org/lkml/2013/9/30/250
> I finally got HW design which is just slow to be able
> to test it.
> ---
> drivers/tty/serial/uartlite.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
> diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
> index 5f90ef24d475..723a6b79cd14 100644
> --- a/drivers/tty/serial/uartlite.c
> +++ b/drivers/tty/serial/uartlite.c
> @@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = {
> #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
> static void ulite_console_wait_tx(struct uart_port *port)
> {
> - int i;
> u8 val;
> + unsigned long timeout;
> /* Spin waiting for TX fifo to have space available */
> - for (i = 0; i < 100000; i++) {
It would be good to add a note about the slow jtag variant here.
Otherwise:
Acked-by: Peter Korsgaard <peter@korsgaard.com>
> + timeout = jiffies + msecs_to_jiffies(1000);
> + while (1) {
> val = uart_in32(ULITE_STATUS, port);
> if ((val & ULITE_STATUS_TXFULL) == 0)
> break;
> + if (time_after(jiffies, timeout)) {
> + dev_warn(port->dev,
> + "timeout waiting for TX buffer empty\n");
> + break;
> + }
> cpu_relax();
> }
> }
> --
> 1.8.2.3
--
Bye, Peter Korsgaard
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] tty: serial: uartlite: Specify time for sending chars
2014-05-05 15:03 ` Peter Korsgaard
@ 2014-05-05 18:24 ` Michal Simek
2014-05-05 19:42 ` Peter Korsgaard
0 siblings, 1 reply; 5+ messages in thread
From: Michal Simek @ 2014-05-05 18:24 UTC (permalink / raw)
To: Peter Korsgaard, Michal Simek
Cc: linux-kernel, Greg Kroah-Hartman, linux-serial, arnd,
Peter Korsgaard, Grant Likely, Rob Herring, Jiri Slaby
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On 05/05/2014 05:03 PM, Peter Korsgaard wrote:
>>>>>> "Michal" == Michal Simek <michal.simek@xilinx.com> writes:
>
> > Xilinx MDM (Microblaze Debug Module) also contains
> > uart interface via JTAG which is compatible with
> > uartlite driver. This interface is really slow
> > that's why timeout is setup to 1s.
>
> > Make this time delay not to be cpu speed dependent.
>
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > ---
>
> > RFC sent here:
> > https://lkml.org/lkml/2013/9/30/250
> > I finally got HW design which is just slow to be able
> > to test it.
>
> > ---
> > drivers/tty/serial/uartlite.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
>
> > diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
> > index 5f90ef24d475..723a6b79cd14 100644
> > --- a/drivers/tty/serial/uartlite.c
> > +++ b/drivers/tty/serial/uartlite.c
> > @@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = {
> > #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
> > static void ulite_console_wait_tx(struct uart_port *port)
> > {
> > - int i;
> > u8 val;
> > + unsigned long timeout;
>
> > /* Spin waiting for TX fifo to have space available */
> > - for (i = 0; i < 100000; i++) {
>
> It would be good to add a note about the slow jtag variant here.
What exactly you would like to see here?
Just that this 1s is here because of mdm uart.
You can find out commit ID via git blame and description
is in commit message.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] tty: serial: uartlite: Specify time for sending chars
2014-05-05 18:24 ` Michal Simek
@ 2014-05-05 19:42 ` Peter Korsgaard
2014-05-06 4:48 ` Michal Simek
0 siblings, 1 reply; 5+ messages in thread
From: Peter Korsgaard @ 2014-05-05 19:42 UTC (permalink / raw)
To: monstr
Cc: Michal Simek, linux-kernel, Greg Kroah-Hartman, linux-serial,
arnd, Peter Korsgaard, Grant Likely, Rob Herring, Jiri Slaby
>>>>> "Michal" == Michal Simek <monstr@monstr.eu> writes:
Hi,
>> > diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
>> > index 5f90ef24d475..723a6b79cd14 100644
>> > --- a/drivers/tty/serial/uartlite.c
>> > +++ b/drivers/tty/serial/uartlite.c
>> > @@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = {
>> > #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
>> > static void ulite_console_wait_tx(struct uart_port *port)
>> > {
>> > - int i;
>> > u8 val;
>> > + unsigned long timeout;
>>
>> > /* Spin waiting for TX fifo to have space available */
>> > - for (i = 0; i < 100000; i++) {
>>
>> It would be good to add a note about the slow jtag variant here.
> What exactly you would like to see here?
> Just that this 1s is here because of mdm uart.
Something like:
/*
* Spin waiting for TX fifo to have space available.
* When using the Microblaze Debug Module this can take up to 1s
*/
--
Bye, Peter Korsgaard
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] tty: serial: uartlite: Specify time for sending chars
2014-05-05 19:42 ` Peter Korsgaard
@ 2014-05-06 4:48 ` Michal Simek
0 siblings, 0 replies; 5+ messages in thread
From: Michal Simek @ 2014-05-06 4:48 UTC (permalink / raw)
To: Peter Korsgaard
Cc: Michal Simek, linux-kernel, Greg Kroah-Hartman, linux-serial,
arnd, Peter Korsgaard, Grant Likely, Rob Herring, Jiri Slaby
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On 05/05/2014 09:42 PM, Peter Korsgaard wrote:
>>>>>> "Michal" == Michal Simek <monstr@monstr.eu> writes:
>
> Hi,
>
> >> > diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c
> >> > index 5f90ef24d475..723a6b79cd14 100644
> >> > --- a/drivers/tty/serial/uartlite.c
> >> > +++ b/drivers/tty/serial/uartlite.c
> >> > @@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = {
> >> > #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
> >> > static void ulite_console_wait_tx(struct uart_port *port)
> >> > {
> >> > - int i;
> >> > u8 val;
> >> > + unsigned long timeout;
> >>
> >> > /* Spin waiting for TX fifo to have space available */
> >> > - for (i = 0; i < 100000; i++) {
> >>
> >> It would be good to add a note about the slow jtag variant here.
>
> > What exactly you would like to see here?
> > Just that this 1s is here because of mdm uart.
>
> Something like:
>
> /*
> * Spin waiting for TX fifo to have space available.
> * When using the Microblaze Debug Module this can take up to 1s
> */
up to you. You are driver owner. :-)
I have sent v2 with this change and I have added your ACK.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2014-05-05 14:48 [PATCH] tty: serial: uartlite: Specify time for sending chars Michal Simek
2014-05-05 15:03 ` Peter Korsgaard
2014-05-05 18:24 ` Michal Simek
2014-05-05 19:42 ` Peter Korsgaard
2014-05-06 4:48 ` Michal Simek
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