From: "Moger, Babu" <Babu.Moger@amd.com>
To: James Morse <james.morse@arm.com>
Cc: "tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"fenghua.yu@intel.com" <fenghua.yu@intel.com>,
"reinette.chatre@intel.com" <reinette.chatre@intel.com>,
"vikas.shivappa@linux.intel.com" <vikas.shivappa@linux.intel.com>,
"tony.luck@intel.com" <tony.luck@intel.com>,
"x86@kernel.org" <x86@kernel.org>,
"peterz@infradead.org" <peterz@infradead.org>,
"pombredanne@nexb.com" <pombredanne@nexb.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"kstewart@linuxfoundation.org" <kstewart@linuxfoundation.org>,
"bp@suse.de" <bp@suse.de>,
"rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"kirill.shutemov@linux.intel.com"
<kirill.shutemov@linux.intel.com>,
"xiaochen.shen@intel.com" <xiaochen.shen@intel.com>,
"colin.king@canonical.com" <colin.king@canonical.com>,
"Hurwitz, Sherry" <sherry.hurwitz@amd.com>,
"Lendacky, Thomas" <Thomas.Lendacky@amd.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"dwmw@amazon.co.uk" <dwmw@amazon.co.uk>,
"luto@kernel.org" <luto@kernel.org>,
"jroedel@suse.de" <jroedel@suse.de>,
"jannh@google.com" <jannh@google.com>,
"dima@arista.com" <dima@arista.com>,
"jpoimboe@redhat.com" <jpoimboe@redhat.com>,
"vkuznets@redhat.com" <vkuznets@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH 10/10] arch/x86: Introduce QOS feature for AMD
Date: Fri, 5 Oct 2018 17:18:35 +0000 [thread overview]
Message-ID: <51b0b05e-800a-86ad-799e-6b8d1ff1ae14@amd.com> (raw)
In-Reply-To: <81d5c963-0f00-29fa-2259-2b7fc26da123@arm.com>
Hi James,
On 10/05/2018 11:20 AM, James Morse wrote:
> Hi Babu,
>
> On 24/09/18 20:19, Moger, Babu wrote:
>> Enables QOS feature on AMD.
>> Following QoS sub-features are supported in AMD if the underlying
>> hardware supports it.
>> - L3 Cache allocation enforcement
>> - L3 Cache occupancy monitoring
>> - L3 Code-Data Prioritization support
>> - Memory Bandwidth Enforcement(Allocation)
>>
>> There are differences in the way some of the features are implemented.
>> Separate those functions and add those as vendor specific functions.
>> The major difference is in MBA feature.
>> - AMD uses CPUID leaf 0x80000020 to initialize the MBA features.
>> - AMD uses direct bandwidth value instead of delay based on bandwidth
>> values.
>> - MSR register base addresses are different for MBA.
>
>> - Also AMD allows non-contiguous L3 cache bit masks.
>
> Nice!
>
> This is visible to user-space, the 'Cache Bit Masks (CBM)' section of
> Documentation/x86/intel_rdt_ui.txt currently says 'X86 hardware requires ... a
> contiguous block'.
>
> Does user-space need to know it can do this in advance, or is it a try-it-and-see?
It is try-it-and-see.
>
> Arm's MPAM stuff can do this too, but I'm against having the ABI vary between
> architectures. If this is going to be discoverable, I'd like it to work on Arm too.
It not discoverable at this point. Mostly predefined. Yes. It will be bit
of a challenge handle these differences. We may have to come up with some
kind of a flag(or something) to make it look similar on the ABI side.
>
>
> Thanks,
>
> James
>
>> Adds following functions to take care of the differences.
>> rdt_get_mem_config_amd : MBA initialization function
>> parse_bw_amd : Bandwidth parsing
>> mba_wrmsr_amd: Writes bandwidth value
>> cbm_validate_amd : L3 cache bitmask validation
>
>> diff --git a/arch/x86/kernel/cpu/rdt_ctrlmondata.c b/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> index 5a282b6c4bd7..1e4631f88696 100644
>> --- a/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> +++ b/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> @@ -123,6 +169,41 @@ bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
>> return true;
>> }
>>
>> +/*
>> + * Check whether a cache bit mask is valid. AMD allows
>> + * non-contiguous masks.
>> + */
>> +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r)
>> +{
>> + unsigned long first_bit, zero_bit, val;
>> + unsigned int cbm_len = r->cache.cbm_len;
>> + int ret;
>> +
>> + ret = kstrtoul(buf, 16, &val);
>> + if (ret) {
>> + rdt_last_cmd_printf("non-hex character in mask %s\n", buf);
>> + return false;
>> + }
>> +
>> + if (val == 0 || val > r->default_ctrl) {
>> + rdt_last_cmd_puts("mask out of range\n");
>> + return false;
>> + }
>> +
>> + first_bit = find_first_bit(&val, cbm_len);
>> + zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);
>> +
>> +
>> + if ((zero_bit - first_bit) < r->cache.min_cbm_bits) {
>> + rdt_last_cmd_printf("Need at least %d bits in mask\n",
>> + r->cache.min_cbm_bits);
>> + return false;
>> + }
>> +
>> + *data = val;
>> + return true;
>> +}
>> +
>> struct rdt_cbm_parse_data {
>> struct rdtgroup *rdtgrp;
>> char *buf;
>>
>
next prev parent reply other threads:[~2018-10-05 17:18 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-24 19:18 [RFC PATCH 00/10] arch/x86: AMD QoS support Moger, Babu
2018-09-24 19:18 ` [RFC PATCH 01/10] arch/x86: Start renaming the rdt files to more generic names Moger, Babu
2018-09-24 19:18 ` [RFC PATCH 02/10] arch/x86: Rename the RDT functions and definitions Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 03/10] arch/x86: Re-arrange RDT init code Moger, Babu
2018-10-02 19:21 ` Reinette Chatre
2018-10-02 23:41 ` Moger, Babu
2018-10-03 18:54 ` Reinette Chatre
2018-10-03 20:12 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 04/10] arch/x86: Introduce a new config parameter PLATFORM_QOS Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 05/10] arch/x86: Use new config parameter PLATFORM_QOS for compilation Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 06/10] arch/x86: Initialize the resource functions that are different Moger, Babu
2018-10-02 22:06 ` Reinette Chatre
2018-10-03 15:25 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 07/10] arch/x86: Bring few more functions into the resource structure Moger, Babu
2018-10-02 22:07 ` Reinette Chatre
2018-10-03 15:32 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 08/10] arch/x86: Introduce new config parameter AMD_QOS Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 09/10] arch/x86: Add AMD feature bit X86_FEATURE_MBA in cpuid bits array Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 10/10] arch/x86: Introduce QOS feature for AMD Moger, Babu
2018-10-02 18:27 ` Fenghua Yu
2018-10-03 15:56 ` Moger, Babu
2018-10-02 22:13 ` Reinette Chatre
2018-10-03 17:21 ` Moger, Babu
2018-10-05 16:20 ` James Morse
2018-10-05 17:18 ` Moger, Babu [this message]
2018-09-27 20:14 ` [RFC PATCH 00/10] arch/x86: AMD QoS support Thomas Gleixner
2018-09-28 1:57 ` Moger, Babu
2018-10-05 16:18 ` James Morse
2018-10-05 17:03 ` Moger, Babu
2018-10-02 17:06 ` Fenghua Yu
2018-10-02 17:44 ` Moger, Babu
2018-10-02 18:46 ` Fenghua Yu
2018-10-02 19:16 ` Moger, Babu
2018-10-03 18:52 ` Fenghua Yu
2018-10-03 19:48 ` Thomas Gleixner
2018-10-03 20:09 ` Moger, Babu
2018-10-05 16:19 ` James Morse
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=51b0b05e-800a-86ad-799e-6b8d1ff1ae14@amd.com \
--to=babu.moger@amd.com \
--cc=Thomas.Lendacky@amd.com \
--cc=ak@linux.intel.com \
--cc=bp@suse.de \
--cc=colin.king@canonical.com \
--cc=dima@arista.com \
--cc=dwmw@amazon.co.uk \
--cc=fenghua.yu@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=hpa@zytor.com \
--cc=james.morse@arm.com \
--cc=jannh@google.com \
--cc=jpoimboe@redhat.com \
--cc=jroedel@suse.de \
--cc=kirill.shutemov@linux.intel.com \
--cc=kstewart@linuxfoundation.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luto@kernel.org \
--cc=mingo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=pombredanne@nexb.com \
--cc=rafael.j.wysocki@intel.com \
--cc=reinette.chatre@intel.com \
--cc=sherry.hurwitz@amd.com \
--cc=tglx@linutronix.de \
--cc=tony.luck@intel.com \
--cc=vikas.shivappa@linux.intel.com \
--cc=vkuznets@redhat.com \
--cc=x86@kernel.org \
--cc=xiaochen.shen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).