* [PATCH 0/3] Add maintainers + Clovertrail support to Intel Mid
@ 2013-10-18 21:18 David Cohen
2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: David Cohen @ 2013-10-18 21:18 UTC (permalink / raw)
To: tglx, hpa, mingo, x86
Cc: sathyanarayanan.kuppuswamy, linux-kernel, David Cohen
This is the next series of patches to add initial support to more Intel Mid
platforms. This time is Clovertrail. Next it will be Merrifield.
This patch set:
1. adds maintainers to Intel Mid architecture
2. moves Medfield code to its own file
3. adds Clovertrail support to Intel Mid
---
David Cohen (2):
MAINTAINERS: INTEL MID SOC: add maintainers
x86: intel-mid: move Medfield code out of intel-mid.c core file
Kuppuswamy Sathyanarayanan (1):
x86: intel-mid: add Clovertrail platform support
MAINTAINERS | 9 +++
arch/x86/include/asm/intel-mid.h | 46 ++++++++++++-
arch/x86/platform/intel-mid/Makefile | 4 +-
arch/x86/platform/intel-mid/intel-mid.c | 60 ++++++++---------
arch/x86/platform/intel-mid/intel_mid_weak_decls.h | 18 ++++++
arch/x86/platform/intel-mid/mfld.c | 75 ++++++++++++++++++++++
6 files changed, 178 insertions(+), 34 deletions(-)
create mode 100644 arch/x86/platform/intel-mid/intel_mid_weak_decls.h
create mode 100644 arch/x86/platform/intel-mid/mfld.c
--
1.8.4.rc3
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers 2013-10-18 21:18 [PATCH 0/3] Add maintainers + Clovertrail support to Intel Mid David Cohen @ 2013-10-18 21:18 ` David Cohen 2013-10-18 21:21 ` Joe Perches 2013-10-18 21:34 ` [PATCH v1.1 " David Cohen 2013-10-18 21:18 ` [PATCH 2/3] x86: intel-mid: move Medfield code out of intel-mid.c core file David Cohen 2013-10-18 21:18 ` [PATCH 3/3] x86: intel-mid: add Clovertrail platform support David Cohen 2 siblings, 2 replies; 10+ messages in thread From: David Cohen @ 2013-10-18 21:18 UTC (permalink / raw) To: tglx, hpa, mingo, x86 Cc: sathyanarayanan.kuppuswamy, linux-kernel, David Cohen Low-power Intel MID SoC support is currently quite outdated. The code is meant for the old Moorestown platform and has not proper support for newer platforms like Medfield, Clovertrail, Merrifield, ... This patch adds official maintainers for such platforms in order to get things in a better shape from now on. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7534a80..8ef9e65 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7570,6 +7570,15 @@ F: arch/x86/platform/sfi/ F: drivers/sfi/ F: include/linux/sfi*.h +LOW-POWER INTEL MID SOC SUPPORT +M: David Cohen <david.a.cohen@linux.intel.com> +M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> +S: Supported +F: arch/x86/platform/intel-mid/ +F: arch/x86/pci/intel_mid_pci.c +F: arch/x86/include/asm/intel-mid.h +F: arch/x86/include/asm/intel_mid*.h + SIMTEC EB110ATX (Chalice CATS) P: Ben Dooks P: Vincent Sanders <vince@simtec.co.uk> -- 1.8.4.rc3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers 2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen @ 2013-10-18 21:21 ` Joe Perches 2013-10-18 21:30 ` David Cohen 2013-10-18 21:34 ` [PATCH v1.1 " David Cohen 1 sibling, 1 reply; 10+ messages in thread From: Joe Perches @ 2013-10-18 21:21 UTC (permalink / raw) To: David Cohen Cc: tglx, hpa, mingo, x86, sathyanarayanan.kuppuswamy, linux-kernel On Fri, 2013-10-18 at 14:18 -0700, David Cohen wrote: > Low-power Intel MID SoC support is currently quite outdated. > The code is meant for the old Moorestown platform and has not proper > support for newer platforms like Medfield, Clovertrail, Merrifield, ... > > This patch adds official maintainers for such platforms in order to get > things in a better shape from now on. >From MAINTAINERS: Note: For the hard of thinking, this list is meant to remain in alphabetical order. If you could add yourselves to it in alphabetical order that would be so much easier [Ed] > diff --git a/MAINTAINERS b/MAINTAINERS > @@ -7570,6 +7570,15 @@ F: arch/x86/platform/sfi/ > F: drivers/sfi/ > F: include/linux/sfi*.h > > +LOW-POWER INTEL MID SOC SUPPORT > +M: David Cohen <david.a.cohen@linux.intel.com> > +M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > +S: Supported > +F: arch/x86/platform/intel-mid/ > +F: arch/x86/pci/intel_mid_pci.c > +F: arch/x86/include/asm/intel-mid.h > +F: arch/x86/include/asm/intel_mid*.h > + > SIMTEC EB110ATX (Chalice CATS) > P: Ben Dooks > P: Vincent Sanders <vince@simtec.co.uk> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers 2013-10-18 21:21 ` Joe Perches @ 2013-10-18 21:30 ` David Cohen 0 siblings, 0 replies; 10+ messages in thread From: David Cohen @ 2013-10-18 21:30 UTC (permalink / raw) To: Joe Perches Cc: tglx, hpa, mingo, x86, sathyanarayanan.kuppuswamy, linux-kernel On 10/18/2013 02:21 PM, Joe Perches wrote: > On Fri, 2013-10-18 at 14:18 -0700, David Cohen wrote: >> Low-power Intel MID SoC support is currently quite outdated. >> The code is meant for the old Moorestown platform and has not proper >> support for newer platforms like Medfield, Clovertrail, Merrifield, ... >> >> This patch adds official maintainers for such platforms in order to get >> things in a better shape from now on. > > From MAINTAINERS: > > Note: For the hard of thinking, this list is meant to remain in alphabetical > order. If you could add yourselves to it in alphabetical order that would be > so much easier [Ed] Thanks. Fixing it right now. Br, David Cohen ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1.1 1/3] MAINTAINERS: INTEL MID SOC: add maintainers 2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen 2013-10-18 21:21 ` Joe Perches @ 2013-10-18 21:34 ` David Cohen 1 sibling, 0 replies; 10+ messages in thread From: David Cohen @ 2013-10-18 21:34 UTC (permalink / raw) To: tglx, hpa, mingo, x86 Cc: sathyanarayanan.kuppuswamy, linux-kernel, David Cohen Low-power Intel MID SoC support is currently quite outdated. The code is meant for the old Moorestown platform and has not proper support for newer platforms like Medfield, Clovertrail, Merrifield, ... This patch adds official maintainers for such platforms in order to get things in a better shape from now on. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7534a80..25a0aa0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5203,6 +5203,15 @@ W: logfs.org S: Maintained F: fs/logfs/ +LOW-POWER INTEL MID SOC SUPPORT +M: David Cohen <david.a.cohen@linux.intel.com> +M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> +S: Supported +F: arch/x86/platform/intel-mid/ +F: arch/x86/pci/intel_mid_pci.c +F: arch/x86/include/asm/intel-mid.h +F: arch/x86/include/asm/intel_mid*.h + LPC32XX MACHINE SUPPORT M: Roland Stigge <stigge@antcom.de> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- 1.8.4.rc3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] x86: intel-mid: move Medfield code out of intel-mid.c core file 2013-10-18 21:18 [PATCH 0/3] Add maintainers + Clovertrail support to Intel Mid David Cohen 2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen @ 2013-10-18 21:18 ` David Cohen 2013-10-18 21:18 ` [PATCH 3/3] x86: intel-mid: add Clovertrail platform support David Cohen 2 siblings, 0 replies; 10+ messages in thread From: David Cohen @ 2013-10-18 21:18 UTC (permalink / raw) To: tglx, hpa, mingo, x86 Cc: sathyanarayanan.kuppuswamy, linux-kernel, David Cohen In order make the driver more portable and support other Intel Mid platforms we need to move Medfield code from intel-mid.c core to its own mfld.c file. This patch does no functional change. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> --- arch/x86/platform/intel-mid/Makefile | 4 +- arch/x86/platform/intel-mid/intel-mid.c | 37 +--------------- arch/x86/platform/intel-mid/intel_mid_weak_decls.h | 15 +++++++ arch/x86/platform/intel-mid/mfld.c | 51 ++++++++++++++++++++++ 4 files changed, 70 insertions(+), 37 deletions(-) create mode 100644 arch/x86/platform/intel-mid/intel_mid_weak_decls.h create mode 100644 arch/x86/platform/intel-mid/mfld.c diff --git a/arch/x86/platform/intel-mid/Makefile b/arch/x86/platform/intel-mid/Makefile index 01cc29e..78a14ba 100644 --- a/arch/x86/platform/intel-mid/Makefile +++ b/arch/x86/platform/intel-mid/Makefile @@ -1,6 +1,6 @@ -obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o -obj-$(CONFIG_X86_INTEL_MID) += intel_mid_vrtc.o +obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_intel_mid.o + # SFI specific code ifdef CONFIG_X86_INTEL_MID obj-$(CONFIG_SFI) += sfi.o device_libs/ diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index 523a1c8..803a17f 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -35,6 +35,8 @@ #include <asm/apb_timer.h> #include <asm/reboot.h> +#include "intel_mid_weak_decls.h" + /* * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, * cmdline option x86_intel_mid_timer can be used to override the configuration @@ -61,46 +63,11 @@ enum intel_mid_timer_options intel_mid_timer_options; enum intel_mid_cpu_type __intel_mid_cpu_chip; EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); -static void intel_mid_power_off(void) -{ -} - static void intel_mid_reboot(void) { intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); } -static unsigned long __init intel_mid_calibrate_tsc(void) -{ - unsigned long fast_calibrate; - u32 lo, hi, ratio, fsb; - - rdmsr(MSR_IA32_PERF_STATUS, lo, hi); - pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi); - ratio = (hi >> 8) & 0x1f; - pr_debug("ratio is %d\n", ratio); - if (!ratio) { - pr_err("read a zero ratio, should be incorrect!\n"); - pr_err("force tsc ratio to 16 ...\n"); - ratio = 16; - } - rdmsr(MSR_FSB_FREQ, lo, hi); - if ((lo & 0x7) == 0x7) - fsb = PENWELL_FSB_FREQ_83SKU; - else - fsb = PENWELL_FSB_FREQ_100SKU; - fast_calibrate = ratio * fsb; - pr_debug("read penwell tsc %lu khz\n", fast_calibrate); - lapic_timer_frequency = fsb * 1000 / HZ; - /* mark tsc clocksource as reliable */ - set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); - - if (fast_calibrate) - return fast_calibrate; - - return 0; -} - static void __init intel_mid_time_init(void) { sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); diff --git a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h new file mode 100644 index 0000000..519beb7 --- /dev/null +++ b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h @@ -0,0 +1,15 @@ +/* + * intel_mid_weak_decls.h: Weak declarations of intel-mid.c + * + * (C) Copyright 2013 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + + +/* __attribute__((weak)) makes these declarations overridable */ +extern void intel_mid_power_off(void) __attribute__((weak)); +extern unsigned long __init intel_mid_calibrate_tsc(void) __attribute__((weak)); diff --git a/arch/x86/platform/intel-mid/mfld.c b/arch/x86/platform/intel-mid/mfld.c new file mode 100644 index 0000000..c7ff83c --- /dev/null +++ b/arch/x86/platform/intel-mid/mfld.c @@ -0,0 +1,51 @@ +/* + * mfld.c: Intel Medfield platform setup code + * + * (C) Copyright 2013 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#include <linux/init.h> + +#include <asm/apic.h> +#include <asm/intel-mid.h> +#include <asm/intel_mid_vrtc.h> + +void intel_mid_power_off(void) +{ +} + +unsigned long __init intel_mid_calibrate_tsc(void) +{ + unsigned long fast_calibrate; + u32 lo, hi, ratio, fsb; + + rdmsr(MSR_IA32_PERF_STATUS, lo, hi); + pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi); + ratio = (hi >> 8) & 0x1f; + pr_debug("ratio is %d\n", ratio); + if (!ratio) { + pr_err("read a zero ratio, should be incorrect!\n"); + pr_err("force tsc ratio to 16 ...\n"); + ratio = 16; + } + rdmsr(MSR_FSB_FREQ, lo, hi); + if ((lo & 0x7) == 0x7) + fsb = PENWELL_FSB_FREQ_83SKU; + else + fsb = PENWELL_FSB_FREQ_100SKU; + fast_calibrate = ratio * fsb; + pr_debug("read penwell tsc %lu khz\n", fast_calibrate); + lapic_timer_frequency = fsb * 1000 / HZ; + /* mark tsc clocksource as reliable */ + set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); + + if (fast_calibrate) + return fast_calibrate; + + return 0; +} -- 1.8.4.rc3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] x86: intel-mid: add Clovertrail platform support 2013-10-18 21:18 [PATCH 0/3] Add maintainers + Clovertrail support to Intel Mid David Cohen 2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen 2013-10-18 21:18 ` [PATCH 2/3] x86: intel-mid: move Medfield code out of intel-mid.c core file David Cohen @ 2013-10-18 21:18 ` David Cohen 2013-10-22 23:33 ` [PATCH] x86: intel-mid: add Merrifield " David Cohen 2 siblings, 1 reply; 10+ messages in thread From: David Cohen @ 2013-10-18 21:18 UTC (permalink / raw) To: tglx, hpa, mingo, x86 Cc: sathyanarayanan.kuppuswamy, linux-kernel, David Cohen, Fei Yang From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> This patch adds Clovertrail support on intel-mid and makes it more flexible to support other SoCs. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Fei Yang <fei.yang@intel.com> --- arch/x86/include/asm/intel-mid.h | 46 +++++++++++++++++++++- arch/x86/platform/intel-mid/intel-mid.c | 39 ++++++++++++++++-- arch/x86/platform/intel-mid/intel_mid_weak_decls.h | 7 +++- arch/x86/platform/intel-mid/mfld.c | 32 +++++++++++++-- 4 files changed, 113 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h index 459769d..f8a8314 100644 --- a/arch/x86/include/asm/intel-mid.h +++ b/arch/x86/include/asm/intel-mid.h @@ -51,10 +51,39 @@ struct devs_id { enum intel_mid_cpu_type { /* 1 was Moorestown */ INTEL_MID_CPU_CHIP_PENWELL = 2, + INTEL_MID_CPU_CHIP_CLOVERVIEW, }; extern enum intel_mid_cpu_type __intel_mid_cpu_chip; +/** + * struct intel_mid_ops - Interface between intel-mid & sub archs + * @arch_setup: arch_setup function to re-initialize platform + * structures (x86_init, x86_platform_init) + * + * This structure can be extended if any new interface is required + * between intel-mid & its sub arch files. + */ +struct intel_mid_ops { + void (*arch_setup)(void); +}; + +/* Helper API's for INTEL_MID_OPS_INIT */ +#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \ + [cpuid] = get_##cpuname##_ops + +/* Maximum number of CPU ops */ +#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *)) + +/* + * For every new cpu addition, a weak get_<cpuname>_ops() function needs be + * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h. + */ +#define INTEL_MID_OPS_INIT {\ + DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ + DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ +}; + #ifdef CONFIG_X86_INTEL_MID static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void) @@ -86,8 +115,21 @@ extern enum intel_mid_timer_options intel_mid_timer_options; * Penwell uses spread spectrum clock, so the freq number is not exactly * the same as reported by MSR based on SDM. */ -#define PENWELL_FSB_FREQ_83SKU 83200 -#define PENWELL_FSB_FREQ_100SKU 99840 +#define FSB_FREQ_83SKU 83200 +#define FSB_FREQ_100SKU 99840 +#define FSB_FREQ_133SKU 133000 + +#define FSB_FREQ_167SKU 167000 +#define FSB_FREQ_200SKU 200000 +#define FSB_FREQ_267SKU 267000 +#define FSB_FREQ_333SKU 333000 +#define FSB_FREQ_400SKU 400000 + +/* Bus Select SoC Fuse value */ +#define BSEL_SOC_FUSE_MASK 0x7 +#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */ +#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */ +#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */ #define SFI_MTMR_MAX_NUM 8 #define SFI_MRTC_MAX 8 diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index 803a17f..bb0cf4d 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -60,14 +60,27 @@ enum intel_mid_timer_options intel_mid_timer_options; +/* intel_mid_ops to store sub arch ops */ +struct intel_mid_ops *intel_mid_ops; +/* getter function for sub arch ops*/ +static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; enum intel_mid_cpu_type __intel_mid_cpu_chip; EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); +static void intel_mid_power_off(void) +{ +}; + static void intel_mid_reboot(void) { intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); } +static unsigned long __init intel_mid_calibrate_tsc(void) +{ + return 0; +} + static void __init intel_mid_time_init(void) { sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); @@ -92,13 +105,33 @@ static void __init intel_mid_time_init(void) static void __cpuinit intel_mid_arch_setup(void) { - if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27) - __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; - else { + if (boot_cpu_data.x86 != 6) { pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", boot_cpu_data.x86, boot_cpu_data.x86_model); __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; + goto out; + } + + switch (boot_cpu_data.x86_model) { + case 0x35: + __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; + break; + case 0x27: + default: + __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; + break; } + + if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) + intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); + else { + intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); + pr_info("ARCH: Uknown SoC, assuming PENWELL!\n"); + } + +out: + if (intel_mid_ops->arch_setup) + intel_mid_ops->arch_setup(); } /* MID systems don't have i8042 controller */ diff --git a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h index 519beb7..9ebce04 100644 --- a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h +++ b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h @@ -11,5 +11,8 @@ /* __attribute__((weak)) makes these declarations overridable */ -extern void intel_mid_power_off(void) __attribute__((weak)); -extern unsigned long __init intel_mid_calibrate_tsc(void) __attribute__((weak)); +/* For every CPU addition a new get_<cpuname>_ops interface needs + * to be added. + */ +extern void * __cpuinit get_penwell_ops(void) __attribute__((weak)); +extern void * __cpuinit get_cloverview_ops(void) __attribute__((weak)); diff --git a/arch/x86/platform/intel-mid/mfld.c b/arch/x86/platform/intel-mid/mfld.c index c7ff83c..4f7884e 100644 --- a/arch/x86/platform/intel-mid/mfld.c +++ b/arch/x86/platform/intel-mid/mfld.c @@ -15,11 +15,19 @@ #include <asm/intel-mid.h> #include <asm/intel_mid_vrtc.h> -void intel_mid_power_off(void) +#include "intel_mid_weak_decls.h" + +static void penwell_arch_setup(void); +/* penwell arch ops */ +static struct intel_mid_ops penwell_ops = { + .arch_setup = penwell_arch_setup, +}; + +static void mfld_power_off(void) { } -unsigned long __init intel_mid_calibrate_tsc(void) +static unsigned long __init mfld_calibrate_tsc(void) { unsigned long fast_calibrate; u32 lo, hi, ratio, fsb; @@ -35,9 +43,9 @@ unsigned long __init intel_mid_calibrate_tsc(void) } rdmsr(MSR_FSB_FREQ, lo, hi); if ((lo & 0x7) == 0x7) - fsb = PENWELL_FSB_FREQ_83SKU; + fsb = FSB_FREQ_83SKU; else - fsb = PENWELL_FSB_FREQ_100SKU; + fsb = FSB_FREQ_100SKU; fast_calibrate = ratio * fsb; pr_debug("read penwell tsc %lu khz\n", fast_calibrate); lapic_timer_frequency = fsb * 1000 / HZ; @@ -49,3 +57,19 @@ unsigned long __init intel_mid_calibrate_tsc(void) return 0; } + +static void __init penwell_arch_setup() +{ + x86_platform.calibrate_tsc = mfld_calibrate_tsc; + pm_power_off = mfld_power_off; +} + +void * __cpuinit get_penwell_ops() +{ + return &penwell_ops; +} + +void * __cpuinit get_cloverview_ops() +{ + return &penwell_ops; +} -- 1.8.4.rc3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH] x86: intel-mid: add Merrifield platform support 2013-10-18 21:18 ` [PATCH 3/3] x86: intel-mid: add Clovertrail platform support David Cohen @ 2013-10-22 23:33 ` David Cohen 2013-10-23 0:49 ` Yang, Fei 0 siblings, 1 reply; 10+ messages in thread From: David Cohen @ 2013-10-22 23:33 UTC (permalink / raw) To: tglx, mingo, hpa, x86 Cc: linux-kernel, David Cohen, Fei Yang, Mark F. Brown, Kuppuswamy Sathyanarayanan This code was partially based on Mark Brown's previous work. Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Fei Yang <fei.yang@intel.com> Cc: Mark F. Brown <mark.f.brown@intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> --- This patch should be applied right after the following one already submitted: - [PATCH 3/3] x86: intel-mid: add Clovertrail platform support Br, David Cohen --- arch/x86/include/asm/intel-mid.h | 2 + arch/x86/pci/intel_mid_pci.c | 6 +- arch/x86/platform/intel-mid/Makefile | 2 +- arch/x86/platform/intel-mid/intel-mid.c | 4 + arch/x86/platform/intel-mid/intel_mid_weak_decls.h | 1 + arch/x86/platform/intel-mid/mrfl.c | 103 +++++++++++++++++++++ arch/x86/platform/intel-mid/sfi.c | 34 +++++-- 7 files changed, 144 insertions(+), 8 deletions(-) create mode 100644 arch/x86/platform/intel-mid/mrfl.c diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h index f8a8314..e34e097 100644 --- a/arch/x86/include/asm/intel-mid.h +++ b/arch/x86/include/asm/intel-mid.h @@ -52,6 +52,7 @@ enum intel_mid_cpu_type { /* 1 was Moorestown */ INTEL_MID_CPU_CHIP_PENWELL = 2, INTEL_MID_CPU_CHIP_CLOVERVIEW, + INTEL_MID_CPU_CHIP_TANGIER, }; extern enum intel_mid_cpu_type __intel_mid_cpu_chip; @@ -82,6 +83,7 @@ struct intel_mid_ops { #define INTEL_MID_OPS_INIT {\ DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \ DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \ + DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \ }; #ifdef CONFIG_X86_INTEL_MID diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 51384ca..84b9d67 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -31,6 +31,7 @@ #include <asm/pci_x86.h> #include <asm/hw_irq.h> #include <asm/io_apic.h> +#include <asm/intel-mid.h> #define PCIE_CAP_OFFSET 0x100 @@ -219,7 +220,10 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) irq_attr.ioapic = mp_find_ioapic(dev->irq); irq_attr.ioapic_pin = dev->irq; irq_attr.trigger = 1; /* level */ - irq_attr.polarity = 1; /* active low */ + if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) + irq_attr.polarity = 0; /* active high */ + else + irq_attr.polarity = 1; /* active low */ io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr); return 0; diff --git a/arch/x86/platform/intel-mid/Makefile b/arch/x86/platform/intel-mid/Makefile index 78a14ba..0a8ee70 100644 --- a/arch/x86/platform/intel-mid/Makefile +++ b/arch/x86/platform/intel-mid/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o +obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o mrfl.o obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_intel_mid.o # SFI specific code diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index bb0cf4d..2e59353 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -116,6 +116,10 @@ static void __cpuinit intel_mid_arch_setup(void) case 0x35: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; break; + case 0x3C: + case 0x4A: + __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; + break; case 0x27: default: __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; diff --git a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h index 9ebce04..a537ffc 100644 --- a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h +++ b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h @@ -16,3 +16,4 @@ */ extern void * __cpuinit get_penwell_ops(void) __attribute__((weak)); extern void * __cpuinit get_cloverview_ops(void) __attribute__((weak)); +extern void * __init get_tangier_ops(void) __attribute__((weak)); diff --git a/arch/x86/platform/intel-mid/mrfl.c b/arch/x86/platform/intel-mid/mrfl.c new file mode 100644 index 0000000..09d1015 --- /dev/null +++ b/arch/x86/platform/intel-mid/mrfl.c @@ -0,0 +1,103 @@ +/* + * mrfl.c: Intel Merrifield platform specific setup code + * + * (C) Copyright 2013 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#include <linux/init.h> + +#include <asm/apic.h> +#include <asm/intel-mid.h> + +#include "intel_mid_weak_decls.h" + +static unsigned long __init tangier_calibrate_tsc(void) +{ + unsigned long fast_calibrate; + u32 lo, hi, ratio, fsb, bus_freq; + + /* *********************** */ + /* Compute TSC:Ratio * FSB */ + /* *********************** */ + + /* Compute Ratio */ + rdmsr(MSR_PLATFORM_INFO, lo, hi); + pr_debug("IA32 PLATFORM_INFO is 0x%x : %x\n", hi, lo); + + ratio = (lo >> 8) & 0xFF; + pr_debug("ratio is %d\n", ratio); + if (!ratio) { + pr_err("Read a zero ratio, force tsc ratio to 4 ...\n"); + ratio = 4; + } + + /* Compute FSB */ + rdmsr(MSR_FSB_FREQ, lo, hi); + pr_debug("Actual FSB frequency detected by SOC 0x%x : %x\n", + hi, lo); + + bus_freq = lo & 0x7; + pr_debug("bus_freq = 0x%x\n", bus_freq); + + if (bus_freq == 0) + fsb = FSB_FREQ_100SKU; + else if (bus_freq == 1) + fsb = FSB_FREQ_100SKU; + else if (bus_freq == 2) + fsb = FSB_FREQ_133SKU; + else if (bus_freq == 3) + fsb = FSB_FREQ_167SKU; + else if (bus_freq == 4) + fsb = FSB_FREQ_83SKU; + else if (bus_freq == 5) + fsb = FSB_FREQ_400SKU; + else if (bus_freq == 6) + fsb = FSB_FREQ_267SKU; + else if (bus_freq == 7) + fsb = FSB_FREQ_333SKU; + else { + BUG(); + pr_err("Invalid bus_freq! Setting to minimal value!\n"); + fsb = FSB_FREQ_100SKU; + } + + /* TSC = FSB Freq * Resolved HFM Ratio */ + fast_calibrate = ratio * fsb; + pr_debug("calculate tangier tsc %lu KHz\n", fast_calibrate); + + /* ************************************ */ + /* Calculate Local APIC Timer Frequency */ + /* ************************************ */ + lapic_timer_frequency = (fsb * 1000) / HZ; + + pr_debug("Setting lapic_timer_frequency = %d\n", + lapic_timer_frequency); + + /* mark tsc clocksource as reliable */ + set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); + + if (fast_calibrate) + return fast_calibrate; + + return 0; +} + +static void __init tangier_arch_setup(void) +{ + x86_platform.calibrate_tsc = tangier_calibrate_tsc; +} + +/* tangier arch ops */ +static struct intel_mid_ops tangier_ops = { + .arch_setup = tangier_arch_setup, +}; + +void * __cpuinit get_tangier_ops() +{ + return &tangier_ops; +} diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c index c84c1ca..80a5228 100644 --- a/arch/x86/platform/intel-mid/sfi.c +++ b/arch/x86/platform/intel-mid/sfi.c @@ -443,13 +443,35 @@ static int __init sfi_parse_devs(struct sfi_table_header *table) * so we have to enable them one by one here */ ioapic = mp_find_ioapic(irq); - irq_attr.ioapic = ioapic; - irq_attr.ioapic_pin = irq; - irq_attr.trigger = 1; - irq_attr.polarity = 1; - io_apic_set_pci_routing(NULL, irq, &irq_attr); - } else + if (ioapic >= 0) { + irq_attr.ioapic = ioapic; + irq_attr.ioapic_pin = irq; + irq_attr.trigger = 1; + if (intel_mid_identify_cpu() == + INTEL_MID_CPU_CHIP_TANGIER) { + if (!strncmp(pentry->name, + "r69001-ts-i2c", 13)) + /* active low */ + irq_attr.polarity = 1; + else if (!strncmp(pentry->name, + "synaptics_3202", 14)) + /* active low */ + irq_attr.polarity = 1; + else if (irq == 41) + /* fast_int_1 */ + irq_attr.polarity = 1; + else + /* active high */ + irq_attr.polarity = 0; + } else { + /* PNW and CLV go with active low */ + irq_attr.polarity = 1; + } + io_apic_set_pci_routing(NULL, irq, &irq_attr); + } + } else { irq = 0; /* No irq */ + } dev = get_device_id(pentry->type, pentry->name); -- 1.8.4.rc3 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCH] x86: intel-mid: add Merrifield platform support 2013-10-22 23:33 ` [PATCH] x86: intel-mid: add Merrifield " David Cohen @ 2013-10-23 0:49 ` Yang, Fei 2013-10-23 2:49 ` David Cohen 0 siblings, 1 reply; 10+ messages in thread From: Yang, Fei @ 2013-10-23 0:49 UTC (permalink / raw) To: David Cohen, tglx, mingo, hpa, x86 Cc: linux-kernel, Brown, Mark F, Kuppuswamy Sathyanarayanan + if (intel_mid_identify_cpu() == + INTEL_MID_CPU_CHIP_TANGIER) { + if (!strncmp(pentry->name, + "r69001-ts-i2c", 13)) + /* active low */ + irq_attr.polarity = 1; + else if (!strncmp(pentry->name, + "synaptics_3202", 14)) + /* active low */ + irq_attr.polarity = 1; + else if (irq == 41) + /* fast_int_1 */ + irq_attr.polarity = 1; Do you really want to upstream these very hardware specific hacks? It's needed for Saltbay, but might not be correct for other Merrifield based hardware, if any. -Fei ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] x86: intel-mid: add Merrifield platform support 2013-10-23 0:49 ` Yang, Fei @ 2013-10-23 2:49 ` David Cohen 0 siblings, 0 replies; 10+ messages in thread From: David Cohen @ 2013-10-23 2:49 UTC (permalink / raw) To: Yang, Fei Cc: tglx, mingo, hpa, x86, linux-kernel, Brown, Mark F, Kuppuswamy Sathyanarayanan On 10/22/2013 05:49 PM, Yang, Fei wrote: > + if (intel_mid_identify_cpu() == > + INTEL_MID_CPU_CHIP_TANGIER) { > + if (!strncmp(pentry->name, > + "r69001-ts-i2c", 13)) > + /* active low */ > + irq_attr.polarity = 1; > + else if (!strncmp(pentry->name, > + "synaptics_3202", 14)) > + /* active low */ > + irq_attr.polarity = 1; > + else if (irq == 41) > + /* fast_int_1 */ > + irq_attr.polarity = 1; > > Do you really want to upstream these very hardware specific hacks? It's needed for > Saltbay, but might not be correct for other Merrifield based hardware, if any. At this very initial moment we do want to support saltbay, which is the main reference for Merrifield. So we can't run away from the ugly hack :) Later, when we upstream the support to detect specific intel mid board details, this code will be isolated for saltbay (and maybe other required boards) and won't affect Merrifield in general. Br, David Cohen ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2013-10-23 2:51 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-10-18 21:18 [PATCH 0/3] Add maintainers + Clovertrail support to Intel Mid David Cohen 2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen 2013-10-18 21:21 ` Joe Perches 2013-10-18 21:30 ` David Cohen 2013-10-18 21:34 ` [PATCH v1.1 " David Cohen 2013-10-18 21:18 ` [PATCH 2/3] x86: intel-mid: move Medfield code out of intel-mid.c core file David Cohen 2013-10-18 21:18 ` [PATCH 3/3] x86: intel-mid: add Clovertrail platform support David Cohen 2013-10-22 23:33 ` [PATCH] x86: intel-mid: add Merrifield " David Cohen 2013-10-23 0:49 ` Yang, Fei 2013-10-23 2:49 ` David Cohen
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