From: "Yun Wu (Abel)" <wuyun.wu@huawei.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: "tglx@linutronix.de" <tglx@linutronix.de>,
"jason@lakedaemon.net" <jason@lakedaemon.net>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 5/6] irqchip: gicv3-its: add support for power down
Date: Tue, 17 Feb 2015 18:15:15 +0800 [thread overview]
Message-ID: <54E314B3.40803@huawei.com> (raw)
In-Reply-To: <20150217092935.1fefcb24@arm.com>
On 2015/2/17 17:29, Marc Zyngier wrote:
> On Sun, 15 Feb 2015 09:32:02 +0000
> Yun Wu <wuyun.wu@huawei.com> wrote:
>
>> It's unsafe to change the configurations of an activated ITS directly
>> since this will lead to unpredictable results. This patch guarantees
>> a safe quiescent status before initializing an ITS.
>
> Please change the title of this patch to reflect what it actually
> does. Nothing here is about powering down anything.
My miss, I will fix this in next version.
>
>> Signed-off-by: Yun Wu <wuyun.wu@huawei.com>
>> ---
>> drivers/irqchip/irq-gic-v3-its.c | 32
>> ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c
>> b/drivers/irqchip/irq-gic-v3-its.c index 42c03b2..29eb665 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -1321,6 +1321,31 @@ static const struct irq_domain_ops
>> its_domain_ops = { .deactivate =
>> its_irq_domain_deactivate, };
>>
>> +static int its_check_quiesced(void __iomem *base)
>> +{
>> + u32 count = 1000000; /* 1s */
>> + u32 val;
>> +
>> + val = readl_relaxed(base + GITS_CTLR);
>> + if (val & GITS_CTLR_QUIESCENT)
>> + return 0;
>> +
>> + /* Disable the generation of all interrupts to this ITS */
>> + val &= ~GITS_CTLR_ENABLE;
>> + writel_relaxed(val, base + GITS_CTLR);
>> +
>> + /* Poll GITS_CTLR and wait until ITS becomes quiescent */
>> + while (count--) {
>> + val = readl_relaxed(base + GITS_CTLR);
>> + if (val & GITS_CTLR_QUIESCENT)
>> + return 0;
>> + cpu_relax();
>> + udelay(1);
>> + }
>
> You're now introducing a third variant of a 1s timeout loop. Notice a
> pattern?
>
I am not sure I know exactly what you suggest. Do you mean I should code
like below to keep the coding style same as the other 2 loops?
while (1) {
val = readl_relaxed(base + GITS_CTLR);
if (val & GITS_CTLR_QUIESCENT)
return 0;
count--;
if (!count)
return -EBUSY;
cpu_relax();
udelay(1);
}
Thanks,
Abel
next prev parent reply other threads:[~2015-02-17 10:16 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-15 9:31 [PATCH v2 0/6] enhance configuring an ITS Yun Wu
2015-02-15 9:31 ` [PATCH v2 1/6] irqchip: gicv3-its: zero itt before handling to hardware Yun Wu
2015-02-15 9:31 ` [PATCH v2 2/6] irqchip: gicv3-its: use 64KB page as default granule Yun Wu
2015-02-17 9:46 ` Marc Zyngier
2015-02-15 9:32 ` [PATCH v2 3/6] irqchip: gicv3-its: limit order of DT size to MAX_ORDER Yun Wu
2015-02-17 9:19 ` Marc Zyngier
2015-02-17 10:00 ` Yun Wu (Abel)
2015-02-15 9:32 ` [PATCH v2 4/6] irqchip: gicv3-its: define macros for GITS_CTLR fields Yun Wu
2015-02-15 9:32 ` [PATCH v2 5/6] irqchip: gicv3-its: add support for power down Yun Wu
2015-02-17 9:29 ` Marc Zyngier
2015-02-17 10:15 ` Yun Wu (Abel) [this message]
2015-02-17 11:11 ` Marc Zyngier
2015-02-17 12:27 ` Yun Wu (Abel)
2015-03-04 3:10 ` Yun Wu (Abel)
2015-02-15 9:32 ` [PATCH v2 6/6] irqchip: gicv3: skip ITS init when no ITS available Yun Wu
2015-02-16 10:05 ` Vladimir Murzin
2015-02-16 14:57 ` Yun Wu (Abel)
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