[PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Pan Xinhui]

This patch aims to get rid of endianness in queued_write_unlock(). We
want to set  __qrwlock->wmode to NULL, however the address is not
&lock->cnts in big endian machine. That causes queued_write_unlock()
write NULL to the wrong field of __qrwlock.

Actually qrwlock can have same layout, IOW we can remove the #if
__little_endian in struct __qrwlock. With such modification, we only
need define some _QW* and _QR* with corresponding values in different
endian systems.

Suggested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Pan Xinhui <xinhui.pan@linux.vnet.ibm.com>
Acked-by: Waiman Long <Waiman.Long@hpe.com>
---
change from v2:
	change macro's name, add comments.
change from v1:
	A typo fix which is really bad...
	thanks Will for the carefull review. :)
---
 include/asm-generic/qrwlock.h | 15 +++++++++++----
 kernel/locking/qrwlock.c      | 11 +++++------
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/include/asm-generic/qrwlock.h b/include/asm-generic/qrwlock.h
index 54a8e65..28fb94a 100644
--- a/include/asm-generic/qrwlock.h
+++ b/include/asm-generic/qrwlock.h
@@ -27,11 +27,18 @@
 /*
  * Writer states & reader shift and bias
  */
-#define	_QW_WAITING	1		/* A writer is waiting	   */
-#define	_QW_LOCKED	0xff		/* A writer holds the lock */
-#define	_QW_WMASK	0xff		/* Writer mask		   */
+#ifdef	__LITTLE_ENDIAN
 #define	_QR_SHIFT	8		/* Reader count shift	   */
-#define _QR_BIAS	(1U << _QR_SHIFT)
+#define	_QW_SHIFT	0		/* Writer mode shift	*/
+#else
+#define	_QR_SHIFT	0		/* Reader count shift	   */
+#define	_QW_SHIFT	24		/* Writer mode shift	*/
+#endif
+
+#define	_QW_WAITING	(1U << _QW_SHIFT)	/* A writer is waiting	   */
+#define	_QW_LOCKED	(0xffU << _QW_SHIFT)	/* A writer holds the lock */
+#define	_QW_WMASK	(0xffU << _QW_SHIFT)	/* Writer mask		   */
+#define	_QR_BIAS	(1U << _QR_SHIFT)
 
 /*
  * External function declarations
diff --git a/kernel/locking/qrwlock.c b/kernel/locking/qrwlock.c
index fec0823..0502e3a 100644
--- a/kernel/locking/qrwlock.c
+++ b/kernel/locking/qrwlock.c
@@ -30,18 +30,16 @@ struct __qrwlock {
 	union {
 		atomic_t cnts;
 		struct {
-#ifdef __LITTLE_ENDIAN
 			u8 wmode;	/* Writer mode   */
 			u8 rcnts[3];	/* Reader counts */
-#else
-			u8 rcnts[3];	/* Reader counts */
-			u8 wmode;	/* Writer mode   */
-#endif
 		};
 	};
 	arch_spinlock_t	lock;
 };
 
+/* get the value of wmode when cnts is v */
+#define	_QW_BYTEVAL(v)	((v) >> _QW_SHIFT)
+
 /**
  * rspin_until_writer_unlock - inc reader count & spin until writer is gone
  * @lock  : Pointer to queue rwlock structure
@@ -127,7 +125,8 @@ void queued_write_lock_slowpath(struct qrwlock *lock)
 		struct __qrwlock *l = (struct __qrwlock *)lock;
 
 		if (!READ_ONCE(l->wmode) &&
-		   (cmpxchg_relaxed(&l->wmode, 0, _QW_WAITING) == 0))
+		   (cmpxchg_relaxed(&l->wmode, 0,
+					_QW_BYTEVAL(_QW_WAITING)) == 0))
 			break;
 
 		cpu_relax_lowlatency();
-- 
1.9.1

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Peter Zijlstra]

On Mon, Jun 20, 2016 at 02:20:52PM +0800, Pan Xinhui wrote:
> This patch aims to get rid of endianness in queued_write_unlock(). We
> want to set  __qrwlock->wmode to NULL, however the address is not
> &lock->cnts in big endian machine. That causes queued_write_unlock()
> write NULL to the wrong field of __qrwlock.
> 
> Actually qrwlock can have same layout, IOW we can remove the #if
> __little_endian in struct __qrwlock. With such modification, we only
> need define some _QW* and _QR* with corresponding values in different
> endian systems.
> 
> Suggested-by: Will Deacon <will.deacon@arm.com>
> Signed-off-by: Pan Xinhui <xinhui.pan@linux.vnet.ibm.com>
> Acked-by: Waiman Long <Waiman.Long@hpe.com>
> ---

Urgh, I hate this stuff :/

OK, so I poked at this a bit and I ended up with the below; but now
qrwlock and qspinlock are inconsistent; although I suspect qspinlock is
similarly busted wrt endian muck.

Not sure what to do..

--- a/include/asm-generic/qrwlock.h
+++ b/include/asm-generic/qrwlock.h
@@ -25,13 +25,31 @@
 #include <asm-generic/qrwlock_types.h>
 
 /*
- * Writer states & reader shift and bias
+ * Writer states & reader shift and bias.
+ *
+ *       | +0 | +1 | +2 | +3 |
+ *   ----+----+----+----+----+
+ *    LE | 12 | 34 | 56 | 78 | 0x12345678
+ *   ----+----+----+----+----+
+ *    BE | 78 | 56 | 34 | 12 | 0x12345678
+ *   ----+----+----+----+----+
+ *       | wr |      rd      |
+ *       +----+----+----+----+
+ *
  */
-#define	_QW_WAITING	1		/* A writer is waiting	   */
-#define	_QW_LOCKED	0xff		/* A writer holds the lock */
-#define	_QW_WMASK	0xff		/* Writer mask		   */
+#ifdef	__LITTLE_ENDIAN
 #define	_QR_SHIFT	8		/* Reader count shift	   */
-#define _QR_BIAS	(1U << _QR_SHIFT)
+#define	_QW_SHIFT	0		/* Writer mode shift	*/
+#else
+#define	_QR_SHIFT	0		/* Reader count shift	   */
+#define	_QW_SHIFT	24		/* Writer mode shift	*/
+#endif
+
+#define	_QW_WAITING	(0x01U << _QW_SHIFT)	/* A writer is waiting	   */
+#define	_QW_LOCKED	(0xffU << _QW_SHIFT)	/* A writer holds the lock */
+#define	_QW_WMASK	(0xffU << _QW_SHIFT)	/* Writer mask		   */
+
+#define	_QR_BIAS	(0x01U << _QR_SHIFT)
 
 /*
  * External function declarations
--- a/kernel/locking/qrwlock.c
+++ b/kernel/locking/qrwlock.c
@@ -22,26 +22,6 @@
 #include <linux/hardirq.h>
 #include <asm/qrwlock.h>
 
-/*
- * This internal data structure is used for optimizing access to some of
- * the subfields within the atomic_t cnts.
- */
-struct __qrwlock {
-	union {
-		atomic_t cnts;
-		struct {
-#ifdef __LITTLE_ENDIAN
-			u8 wmode;	/* Writer mode   */
-			u8 rcnts[3];	/* Reader counts */
-#else
-			u8 rcnts[3];	/* Reader counts */
-			u8 wmode;	/* Writer mode   */
-#endif
-		};
-	};
-	arch_spinlock_t	lock;
-};
-
 /**
  * rspin_until_writer_unlock - inc reader count & spin until writer is gone
  * @lock  : Pointer to queue rwlock structure
@@ -124,10 +104,10 @@ void queued_write_lock_slowpath(struct q
 	 * or wait for a previous writer to go away.
 	 */
 	for (;;) {
-		struct __qrwlock *l = (struct __qrwlock *)lock;
+		u8 *wr = (u8 *)lock;
 
-		if (!READ_ONCE(l->wmode) &&
-		   (cmpxchg_relaxed(&l->wmode, 0, _QW_WAITING) == 0))
+		if (!READ_ONCE(*wr) &&
+		    (cmpxchg_relaxed(wr, 0, _QW_WAITING >> _QW_SHIFT) == 0))
 			break;
 
 		cpu_relax_lowlatency();

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Peter Zijlstra]

On Wed, Jul 13, 2016 at 09:54:23PM +0200, Peter Zijlstra wrote:

> Urgh, I hate this stuff :/

> + * Writer states & reader shift and bias.
> + *
> + *       | +0 | +1 | +2 | +3 |
> + *   ----+----+----+----+----+
> + *    LE | 12 | 34 | 56 | 78 | 0x12345678
> + *   ----+----+----+----+----+
> + *    BE | 78 | 56 | 34 | 12 | 0x12345678
> + *   ----+----+----+----+----+

And of course I got that wrong.. its 0x78563412 in both cases.

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Waiman Long]

On 07/13/2016 03:54 PM, Peter Zijlstra wrote:
> On Mon, Jun 20, 2016 at 02:20:52PM +0800, Pan Xinhui wrote:
>> This patch aims to get rid of endianness in queued_write_unlock(). We
>> want to set  __qrwlock->wmode to NULL, however the address is not
>> &lock->cnts in big endian machine. That causes queued_write_unlock()
>> write NULL to the wrong field of __qrwlock.
>>
>> Actually qrwlock can have same layout, IOW we can remove the #if
>> __little_endian in struct __qrwlock. With such modification, we only
>> need define some _QW* and _QR* with corresponding values in different
>> endian systems.
>>
>> Suggested-by: Will Deacon<will.deacon@arm.com>
>> Signed-off-by: Pan Xinhui<xinhui.pan@linux.vnet.ibm.com>
>> Acked-by: Waiman Long<Waiman.Long@hpe.com>
>> ---
> Urgh, I hate this stuff :/
>
> OK, so I poked at this a bit and I ended up with the below; but now
> qrwlock and qspinlock are inconsistent; although I suspect qspinlock is
> similarly busted wrt endian muck.

Qspinlock is a bit different that the generic unlock code is 
endian-independent. The x86 architectural unlock code, however, is 
little-endian specific. This is not a problem. PPC will certainly needs 
its own unlock code for better performance.

With this patch, there is indeed inconsistency on how qspinlock and 
qrwlock handle their internal data. I guess we could make qrwlock more 
like qspinlock if you want consistency, but I am fine with either ways.

> Not sure what to do..
>
> --- a/include/asm-generic/qrwlock.h
> +++ b/include/asm-generic/qrwlock.h
> @@ -25,13 +25,31 @@
>   #include<asm-generic/qrwlock_types.h>
>
>   /*
> - * Writer states&  reader shift and bias
> + * Writer states&  reader shift and bias.
> + *
> + *       | +0 | +1 | +2 | +3 |
> + *   ----+----+----+----+----+
> + *    LE | 12 | 34 | 56 | 78 | 0x12345678
> + *   ----+----+----+----+----+
> + *    BE | 78 | 56 | 34 | 12 | 0x12345678
> + *   ----+----+----+----+----+
> + *       | wr |      rd      |
> + *       +----+----+----+----+
> + *
>    */
> -#define	_QW_WAITING	1		/* A writer is waiting	   */
> -#define	_QW_LOCKED	0xff		/* A writer holds the lock */
> -#define	_QW_WMASK	0xff		/* Writer mask		   */
> +#ifdef	__LITTLE_ENDIAN
>   #define	_QR_SHIFT	8		/* Reader count shift	   */
> -#define _QR_BIAS	(1U<<  _QR_SHIFT)
> +#define	_QW_SHIFT	0		/* Writer mode shift	*/
> +#else
> +#define	_QR_SHIFT	0		/* Reader count shift	   */
> +#define	_QW_SHIFT	24		/* Writer mode shift	*/
> +#endif
> +
> +#define	_QW_WAITING	(0x01U<<  _QW_SHIFT)	/* A writer is waiting	   */
> +#define	_QW_LOCKED	(0xffU<<  _QW_SHIFT)	/* A writer holds the lock */
> +#define	_QW_WMASK	(0xffU<<  _QW_SHIFT)	/* Writer mask		   */
> +
> +#define	_QR_BIAS	(0x01U<<  _QR_SHIFT)
>   

I like the comment at the top (after you fixed the typo :-) ).

>   /*
>    * External function declarations
> --- a/kernel/locking/qrwlock.c
> +++ b/kernel/locking/qrwlock.c
> @@ -22,26 +22,6 @@
>   #include<linux/hardirq.h>
>   #include<asm/qrwlock.h>
>
> -/*
> - * This internal data structure is used for optimizing access to some of
> - * the subfields within the atomic_t cnts.
> - */
> -struct __qrwlock {
> -	union {
> -		atomic_t cnts;
> -		struct {
> -#ifdef __LITTLE_ENDIAN
> -			u8 wmode;	/* Writer mode   */
> -			u8 rcnts[3];	/* Reader counts */
> -#else
> -			u8 rcnts[3];	/* Reader counts */
> -			u8 wmode;	/* Writer mode   */
> -#endif
> -		};
> -	};
> -	arch_spinlock_t	lock;
> -};
> -
>   /**
>    * rspin_until_writer_unlock - inc reader count&  spin until writer is gone
>    * @lock  : Pointer to queue rwlock structure
> @@ -124,10 +104,10 @@ void queued_write_lock_slowpath(struct q
>   	 * or wait for a previous writer to go away.
>   	 */
>   	for (;;) {
> -		struct __qrwlock *l = (struct __qrwlock *)lock;
> +		u8 *wr = (u8 *)lock;
>
> -		if (!READ_ONCE(l->wmode)&&
> -		   (cmpxchg_relaxed(&l->wmode, 0, _QW_WAITING) == 0))
> +		if (!READ_ONCE(*wr)&&
> +		    (cmpxchg_relaxed(wr, 0, _QW_WAITING>>  _QW_SHIFT) == 0))
>   			break;
>
>   		cpu_relax_lowlatency();

Cheers,
Longman

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[xinhui]

On 2016年07月14日 03:54, Peter Zijlstra wrote:
> On Mon, Jun 20, 2016 at 02:20:52PM +0800, Pan Xinhui wrote:
>> This patch aims to get rid of endianness in queued_write_unlock(). We
>> want to set  __qrwlock->wmode to NULL, however the address is not
>> &lock->cnts in big endian machine. That causes queued_write_unlock()
>> write NULL to the wrong field of __qrwlock.
>>
>> Actually qrwlock can have same layout, IOW we can remove the #if
>> __little_endian in struct __qrwlock. With such modification, we only
>> need define some _QW* and _QR* with corresponding values in different
>> endian systems.
>>
>> Suggested-by: Will Deacon <will.deacon@arm.com>
>> Signed-off-by: Pan Xinhui <xinhui.pan@linux.vnet.ibm.com>
>> Acked-by: Waiman Long <Waiman.Long@hpe.com>
>> ---
>
> Urgh, I hate this stuff :/
>
> OK, so I poked at this a bit and I ended up with the below; but now
> qrwlock and qspinlock are inconsistent; although I suspect qspinlock is
> similarly busted wrt endian muck.
>
> Not sure what to do..
>
Lets talk about the qspinlock.

for x86, We has already assumed that ->locked sit at the low 8 bits, as is
smp_store_release((u8 *)lock, 0);

Then we can do a favor, export ->locked but other fields as reserved.
say

struct __qspinlock_unlcok_interface {/* what name is better?*/
#ifdef __LITTLE_ENDIAN
		u8      locked;
		u8      reserved[3]; /* do not touch it, internally use only  */
#else
		u8      reserved[3];
		u8      locked;
#endif
};

I think it is acceptable. and we can do similar things with qrwlock, too.

any thoughts?


>   /*
> - * Writer states & reader shift and bias
> + * Writer states & reader shift and bias.
> + *
> + *       | +0 | +1 | +2 | +3 |
> + *   ----+----+----+----+----+
> + *    LE | 12 | 34 | 56 | 78 | 0x12345678
> + *   ----+----+----+----+----+
> + *    BE | 78 | 56 | 34 | 12 | 0x12345678
> + *   ----+----+----+----+----+
> + *       | wr |      rd      |
> + *       +----+----+----+----+
> + *
>    */

very clearly. :)

thanks
xinhui

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Peter Zijlstra]

On Thu, Jul 14, 2016 at 03:44:42PM +0800, xinhui wrote:
> >OK, so I poked at this a bit and I ended up with the below; but now
> >qrwlock and qspinlock are inconsistent; although I suspect qspinlock is
> >similarly busted wrt endian muck.
> >
> >Not sure what to do..
> >
> Lets talk about the qspinlock.
> 
> for x86, We has already assumed that ->locked sit at the low 8 bits, as is
> smp_store_release((u8 *)lock, 0);

Right, true on x86 though :-) I noticed your PPC patches have a +3 in
there conditional on __BIG_ENDIAN.

> Then we can do a favor, export ->locked but other fields as reserved.
> say
> 
> struct __qspinlock_unlcok_interface {/* what name is better?*/
> #ifdef __LITTLE_ENDIAN
> 		u8      locked;
> 		u8      reserved[3]; /* do not touch it, internally use only  */
> #else
> 		u8      reserved[3];
> 		u8      locked;
> #endif
> };

Right, maybe, although something like:

static inline u8 *__qspinlock_lock_byte(struct qspinlock *lock)
{
	return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
}

static inline u8 *__qrwlock_write_byte(struct qrwlock *lock)
{
	return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
}

is shorter?


> >  /*
> >+ * Writer states & reader shift and bias.
> >+ *
> >+ *       | +0 | +1 | +2 | +3 |
> >+ *   ----+----+----+----+----+
> >+ *    LE | 12 | 34 | 56 | 78 | 0x12345678
> >+ *   ----+----+----+----+----+
> >+ *    BE | 78 | 56 | 34 | 12 | 0x12345678
> >+ *   ----+----+----+----+----+
> >+ *       | wr |      rd      |
> >+ *       +----+----+----+----+
> >+ *
> >   */
> 
> very clearly. :)

I did one for the qspinlock code too..

diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
index b2caec7315af..9191dc454e96 100644
--- a/kernel/locking/qspinlock.c
+++ b/kernel/locking/qspinlock.c
@@ -120,6 +120,23 @@ static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
  *
  * This internal structure is also used by the set_locked function which
  * is not restricted to _Q_PENDING_BITS == 8.
+ *
+ *       | +0 | +1 | +2 | +3 |
+ *   ----+----+----+----+----+
+ *    LE | 78 | 56 | 34 | 12 |	val = 0x12345678
+ *   ----+----+----+----+----+
+ *    LE | 34 | 12 |		locked_pending = 0x1234
+ *   ----+----+----+----+----+
+ *       | L  | P  |  tail   |
+ *       +----+----+----+----+
+ *
+ *   ----+----+----+----+----+
+ *    BE | 12 | 34 | 56 | 78 |	val = 0x12345678
+ *   ----+----+----+----+----+
+ *    BE           | 12 | 34 |	locked_pending = 0x1234
+ *   ----+----+----+----+----+
+ *       |  tail   | P  | L  |
+ *       +----+----+----+----+
  */
 struct __qspinlock {
 	union {

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Peter Zijlstra]

On Thu, Jul 14, 2016 at 11:37:33AM +0200, Peter Zijlstra wrote:
> static inline u8 *__qspinlock_lock_byte(struct qspinlock *lock)
> {
> 	return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
> }

Bugger, that doesn't actually work. IS_BUILTIN expects the symbol to be
defined to "1" and __BIG_ENDIAN is not (its "4321").

Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[Boqun Feng]

[-- Attachment #1: Type: text/plain, Size: 572 bytes --]

On Thu, Jul 14, 2016 at 11:46:26AM +0200, Peter Zijlstra wrote:
> On Thu, Jul 14, 2016 at 11:37:33AM +0200, Peter Zijlstra wrote:
> > static inline u8 *__qspinlock_lock_byte(struct qspinlock *lock)
> > {
> > 	return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
> > }
> 
> Bugger, that doesn't actually work. IS_BUILTIN expects the symbol to be
> defined to "1" and __BIG_ENDIAN is not (its "4321").
> 
> 

Using IS_BUILTIN(CONFIG_CPU_BIG_ENDIAN) instead? Seems ARM and PPC both
define this properly if the target kernel is a big endian one.

Regards,
Boqun

[-- Attachment #2: signature.asc --]
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Re: [PATCH v3] locking/qrwlock: Let qrwlock has same layout regardless of the endian

[panxinhui]

在 16/7/14 17:37, Peter Zijlstra 写道:
> On Thu, Jul 14, 2016 at 03:44:42PM +0800, xinhui wrote:
>>> OK, so I poked at this a bit and I ended up with the below; but now
>>> qrwlock and qspinlock are inconsistent; although I suspect qspinlock is
>>> similarly busted wrt endian muck.
>>>
>>> Not sure what to do..
>>>
>> Lets talk about the qspinlock.
>>
>> for x86, We has already assumed that ->locked sit at the low 8 bits, as is
>> smp_store_release((u8 *)lock, 0);
>
> Right, true on x86 though :-) I noticed your PPC patches have a +3 in
> there conditional on __BIG_ENDIAN.
>
>> Then we can do a favor, export ->locked but other fields as reserved.
>> say
>>
>> struct __qspinlock_unlcok_interface {/* what name is better?*/
>> #ifdef __LITTLE_ENDIAN
>> 		u8      locked;
>> 		u8      reserved[3]; /* do not touch it, internally use only  */
>> #else
>> 		u8      reserved[3];
>> 		u8      locked;
>> #endif
>> };
>
> Right, maybe, although something like:
>
> static inline u8 *__qspinlock_lock_byte(struct qspinlock *lock)
> {
> 	return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
> }
>
> static inline u8 *__qrwlock_write_byte(struct qrwlock *lock)
> {
> 	return (u8 *)lock + 3 * IS_BUILTIN(__BIG_ENDIAN);
> }
>
> is shorter?
>

yes, looks simpler. I will take them into my patch. thanks


>
>>>  /*
>>> + * Writer states & reader shift and bias.
>>> + *
>>> + *       | +0 | +1 | +2 | +3 |
>>> + *   ----+----+----+----+----+
>>> + *    LE | 12 | 34 | 56 | 78 | 0x12345678
>>> + *   ----+----+----+----+----+
>>> + *    BE | 78 | 56 | 34 | 12 | 0x12345678
>>> + *   ----+----+----+----+----+
>>> + *       | wr |      rd      |
>>> + *       +----+----+----+----+
>>> + *
>>>   */
>>
>> very clearly. :)
>
> I did one for the qspinlock code too..
>

hmm, pretty nice, I think I can include them into my patch too while I am at it.

thanks
xinhui

> diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
> index b2caec7315af..9191dc454e96 100644
> --- a/kernel/locking/qspinlock.c
> +++ b/kernel/locking/qspinlock.c
> @@ -120,6 +120,23 @@ static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
>   *
>   * This internal structure is also used by the set_locked function which
>   * is not restricted to _Q_PENDING_BITS == 8.
> + *
> + *       | +0 | +1 | +2 | +3 |
> + *   ----+----+----+----+----+
> + *    LE | 78 | 56 | 34 | 12 |	val = 0x12345678
> + *   ----+----+----+----+----+
> + *    LE | 34 | 12 |		locked_pending = 0x1234
> + *   ----+----+----+----+----+
> + *       | L  | P  |  tail   |
> + *       +----+----+----+----+
> + *
> + *   ----+----+----+----+----+
> + *    BE | 12 | 34 | 56 | 78 |	val = 0x12345678
> + *   ----+----+----+----+----+
> + *    BE           | 12 | 34 |	locked_pending = 0x1234
> + *   ----+----+----+----+----+
> + *       |  tail   | P  | L  |
> + *       +----+----+----+----+
>   */
>  struct __qspinlock {
>  	union {
>