From: Nadav Amit <namit@vmware.com>
To: Andy Lutomirski <luto@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@intel.com>,
Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>, X86 ML <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>
Subject: Re: [RFC PATCH v2 11/12] x86/mm/tlb: Use async and inline messages for flushing
Date: Fri, 31 May 2019 21:33:10 +0000 [thread overview]
Message-ID: <5F153080-D7A7-4054-AB4A-AEDD5F82E0B9@vmware.com> (raw)
In-Reply-To: <CALCETrU0=BpGy5OQezQ7or33n-EFgBVDNe5g8prSUjL2SoRAwA@mail.gmail.com>
> On May 31, 2019, at 2:14 PM, Andy Lutomirski <luto@kernel.org> wrote:
>
> On Thu, May 30, 2019 at 11:37 PM Nadav Amit <namit@vmware.com> wrote:
>> When we flush userspace mappings, we can defer the TLB flushes, as long
>> the following conditions are met:
>>
>> 1. No tables are freed, since otherwise speculative page walks might
>> cause machine-checks.
>>
>> 2. No one would access userspace before flush takes place. Specifically,
>> NMI handlers and kprobes would avoid accessing userspace.
>
> I think I need to ask the big picture question. When someone calls
> flush_tlb_mm_range() (or the other entry points), if no page tables
> were freed, they want the guarantee that future accesses (initiated
> observably after the flush returns) will not use paging entries that
> were replaced by stores ordered before flush_tlb_mm_range(). We also
> need the guarantee that any effects from any memory access using the
> old paging entries will become globally visible before
> flush_tlb_mm_range().
>
> I'm wondering if receipt of an IPI is enough to guarantee any of this.
> If CPU 1 sets a dirty bit and CPU 2 writes to the APIC to send an IPI
> to CPU 1, at what point is CPU 2 guaranteed to be able to observe the
> dirty bit? An interrupt entry today is fully serializing by the time
> it finishes, but interrupt entries are epicly slow, and I don't know
> if the APIC waits long enough. Heck, what if IRQs are off on the
> remote CPU? There are a handful of places where we touch user memory
> with IRQs off, and it's (sadly) possible for user code to turn off
> IRQs with iopl().
>
> I *think* that Intel has stated recently that SMT siblings are
> guaranteed to stop speculating when you write to the APIC ICR to poke
> them, but SMT is very special.
>
> My general conclusion is that I think the code needs to document what
> is guaranteed and why.
I think I might have managed to confuse you with a bug I made (last minute
bug when I was doing some cleanup). This bug does not affect the performance
much, but it might led you to think that I use the APIC sending as
synchronization.
The idea is not for us to rely on write to ICR as something serializing. The
flow should be as follows:
CPU0 CPU1
flush_tlb_mm_range()
__smp_call_function_many()
[ prepare call_single_data (csd) ]
[ lock csd ]
[ send IPI ]
(*)
[ wait for csd to be unlocked ]
[ interrupt ]
[ copy csd info to stack ]
[ csd unlock ]
[ find csd is unlocked ]
[ continue (**) ]
[ flush TLB ]
At (**) the pages might be recycled, written-back to disk, etc. Note that
during (*), CPU0 might do some local TLB flushes, making it very likely that
CSD will be unlocked by the time it gets there.
As you can see, I don’t rely on any special micro-architectural behavior.
The synchronization is done purely in software.
Does it make more sense now?
next prev parent reply other threads:[~2019-05-31 21:33 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-31 6:36 [RFC PATCH v2 00/12] x86: Flush remote TLBs concurrently and async Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 01/12] smp: Remove smp_call_function() and on_each_cpu() return values Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 02/12] smp: Run functions concurrently in smp_call_function_many() Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 03/12] x86/mm/tlb: Refactor common code into flush_tlb_on_cpus() Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 04/12] x86/mm/tlb: Flush remote and local TLBs concurrently Nadav Amit
2019-05-31 11:48 ` Juergen Gross
2019-05-31 19:44 ` Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 05/12] x86/mm/tlb: Optimize local TLB flushes Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 06/12] KVM: x86: Provide paravirtualized flush_tlb_multi() Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 07/12] smp: Do not mark call_function_data as shared Nadav Amit
2019-05-31 10:17 ` Peter Zijlstra
2019-05-31 17:50 ` Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 08/12] x86/tlb: Privatize cpu_tlbstate Nadav Amit
2019-05-31 18:48 ` Andy Lutomirski
2019-05-31 19:42 ` Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 09/12] x86/apic: Use non-atomic operations when possible Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 10/12] smp: Enable data inlining for inter-processor function call Nadav Amit
2019-05-31 6:36 ` [RFC PATCH v2 11/12] x86/mm/tlb: Use async and inline messages for flushing Nadav Amit
2019-05-31 10:57 ` Peter Zijlstra
2019-05-31 18:29 ` Nadav Amit
2019-05-31 19:20 ` Jann Horn
2019-05-31 20:04 ` Nadav Amit
2019-05-31 20:37 ` Jann Horn
2019-05-31 18:44 ` Andy Lutomirski
2019-05-31 19:31 ` Nadav Amit
2019-05-31 20:13 ` Dave Hansen
2019-05-31 20:37 ` Andy Lutomirski
2019-05-31 20:42 ` Nadav Amit
2019-05-31 21:06 ` Dave Hansen
2019-05-31 21:14 ` Andy Lutomirski
2019-05-31 21:33 ` Nadav Amit [this message]
2019-05-31 21:47 ` Andy Lutomirski
2019-05-31 22:07 ` Nadav Amit
2019-06-07 5:28 ` Nadav Amit
2019-06-07 16:42 ` Andy Lutomirski
2019-05-31 6:36 ` [RFC PATCH v2 12/12] x86/mm/tlb: Reverting the removal of flush_tlb_info from stack Nadav Amit
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