[PATCH V3 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[PATCH V3 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[Piyush Mehta]

This patch series updates the ceva driver to add support for Xilinx GT phy.
This also updates the documentation with the device tree binding required
for working with Xilinx GT phy.

---
Changes in V2:
 - Added backward compatibility with the older sequence of the CEVA controller.
 - Update dt-bindings document: To make phy and reset properties optional.
 - Remove rst_names property.

Changes in V3:
 - Remove phy-names property.
 - Validate backward compatibility with reset controller availability,
   instead of a flag.
---
Piyush Mehta (2):
  dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller
  ata: ahci: ceva: Update the driver to support xilinx GT phy

 .../devicetree/bindings/ata/ahci-ceva.txt          |  4 ++
 drivers/ata/ahci_ceva.c                            | 43 ++++++++++++++++++++--
 2 files changed, 44 insertions(+), 3 deletions(-)

-- 
2.7.4

[PATCH V3 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller

[Piyush Mehta]

This patch updates the documentation for the CEVA controller for adding
the optional properties for 'phys' and 'resets'.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
---
 Documentation/devicetree/bindings/ata/ahci-ceva.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
index 7561cc4..bfb6da0 100644
--- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
@@ -38,6 +38,8 @@ Required properties:
 
 Optional properties:
   - ceva,broken-gen2: limit to gen1 speed instead of gen2.
+  - phys: phandle for the PHY device
+  - resets: phandle to the reset controller for the SATA IP
 
 Examples:
 	ahci@fd0c0000 {
@@ -56,4 +58,6 @@ Examples:
 		ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
 		ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 		ceva,broken-gen2;
+		phys = <&psgtr 1 PHY_TYPE_SATA 1 1>;
+		resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
 	};
-- 
2.7.4

Re: [PATCH V3 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller

[Rob Herring]

On Mon, 08 Feb 2021 23:33:55 +0530, Piyush Mehta wrote:
> This patch updates the documentation for the CEVA controller for adding
> the optional properties for 'phys' and 'resets'.
> 
> Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
> ---
>  Documentation/devicetree/bindings/ata/ahci-ceva.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH V3 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[Piyush Mehta]

SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
which has 4 GT lanes and can be used by 4 peripherals at a time.
SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
the GT lane for the SATA controller, the below sequence is expected.

1. Assert the SATA controller reset.
2. Configure the xilinx GT phy lane for SATA controller (phy_init).
3. De-assert the SATA controller reset.
4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).

The ahci_platform_enable_resources() by default does the phy_init()
and phy_power_on() but the default sequence doesn't work with Xilinx
platforms. Because of this reason, updated the driver to support the
new sequence.

Added cevapriv->rst check, for backward compatibility with the older
sequence. If the reset controller is not available, then the SATA
controller will configure with the older sequences.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
---
 drivers/ata/ahci_ceva.c | 43 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 40 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index b10fd4c..b980218 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include "ahci.h"
 
 /* Vendor Specific Register Offsets */
@@ -87,6 +88,7 @@ struct ceva_ahci_priv {
 	u32 axicc;
 	bool is_cci_enabled;
 	int flags;
+	struct reset_control *rst;
 };
 
 static unsigned int ceva_ahci_read_id(struct ata_device *dev,
@@ -202,13 +204,48 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 
 	cevapriv->ahci_pdev = pdev;
 
+	cevapriv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
+								  NULL);
+	if (IS_ERR(cevapriv->rst)) {
+		if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "failed to get reset: %ld\n",
+				PTR_ERR(cevapriv->rst));
+	}
+
 	hpriv = ahci_platform_get_resources(pdev, 0);
 	if (IS_ERR(hpriv))
 		return PTR_ERR(hpriv);
 
-	rc = ahci_platform_enable_resources(hpriv);
-	if (rc)
-		return rc;
+	if (!cevapriv->rst) {
+		rc = ahci_platform_enable_resources(hpriv);
+		if (rc)
+			return rc;
+	} else {
+		int i;
+
+		rc = ahci_platform_enable_clks(hpriv);
+		if (rc)
+			return rc;
+		/* Assert the controller reset */
+		reset_control_assert(cevapriv->rst);
+
+		for (i = 0; i < hpriv->nports; i++) {
+			rc = phy_init(hpriv->phys[i]);
+			if (rc)
+				return rc;
+		}
+
+		/* De-assert the controller reset */
+		reset_control_deassert(cevapriv->rst);
+
+		for (i = 0; i < hpriv->nports; i++) {
+			rc = phy_power_on(hpriv->phys[i]);
+			if (rc) {
+				phy_exit(hpriv->phys[i]);
+				return rc;
+			}
+		}
+	}
 
 	if (of_property_read_bool(np, "ceva,broken-gen2"))
 		cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
-- 
2.7.4

Re: [PATCH V3 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[Michal Simek]

On 2/8/21 7:03 PM, Piyush Mehta wrote:
> SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy
> which has 4 GT lanes and can be used by 4 peripherals at a time.
> SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure
> the GT lane for the SATA controller, the below sequence is expected.
> 
> 1. Assert the SATA controller reset.
> 2. Configure the xilinx GT phy lane for SATA controller (phy_init).
> 3. De-assert the SATA controller reset.
> 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on).
> 
> The ahci_platform_enable_resources() by default does the phy_init()
> and phy_power_on() but the default sequence doesn't work with Xilinx
> platforms. Because of this reason, updated the driver to support the
> new sequence.
> 
> Added cevapriv->rst check, for backward compatibility with the older
> sequence. If the reset controller is not available, then the SATA
> controller will configure with the older sequences.
> 
> Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
> ---
>  drivers/ata/ahci_ceva.c | 43 ++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 40 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
> index b10fd4c..b980218 100644
> --- a/drivers/ata/ahci_ceva.c
> +++ b/drivers/ata/ahci_ceva.c
> @@ -12,6 +12,7 @@
>  #include <linux/module.h>
>  #include <linux/of_device.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset.h>
>  #include "ahci.h"
>  
>  /* Vendor Specific Register Offsets */
> @@ -87,6 +88,7 @@ struct ceva_ahci_priv {
>  	u32 axicc;
>  	bool is_cci_enabled;
>  	int flags;
> +	struct reset_control *rst;
>  };
>  
>  static unsigned int ceva_ahci_read_id(struct ata_device *dev,
> @@ -202,13 +204,48 @@ static int ceva_ahci_probe(struct platform_device *pdev)
>  
>  	cevapriv->ahci_pdev = pdev;
>  
> +	cevapriv->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
> +								  NULL);
> +	if (IS_ERR(cevapriv->rst)) {
> +		if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER)
> +			dev_err(&pdev->dev, "failed to get reset: %ld\n",
> +				PTR_ERR(cevapriv->rst));
> +	}

nit: This can be handled via dev_err_probe() to simplify this logic here.
It was added by a787e5400a1c ("driver core: add device probe log
helper") but up to Jens if he wants this to be fixed.

> +
>  	hpriv = ahci_platform_get_resources(pdev, 0);
>  	if (IS_ERR(hpriv))
>  		return PTR_ERR(hpriv);
>  
> -	rc = ahci_platform_enable_resources(hpriv);
> -	if (rc)
> -		return rc;
> +	if (!cevapriv->rst) {
> +		rc = ahci_platform_enable_resources(hpriv);
> +		if (rc)
> +			return rc;
> +	} else {
> +		int i;
> +
> +		rc = ahci_platform_enable_clks(hpriv);
> +		if (rc)
> +			return rc;
> +		/* Assert the controller reset */
> +		reset_control_assert(cevapriv->rst);
> +
> +		for (i = 0; i < hpriv->nports; i++) {
> +			rc = phy_init(hpriv->phys[i]);
> +			if (rc)
> +				return rc;
> +		}
> +
> +		/* De-assert the controller reset */
> +		reset_control_deassert(cevapriv->rst);
> +
> +		for (i = 0; i < hpriv->nports; i++) {
> +			rc = phy_power_on(hpriv->phys[i]);
> +			if (rc) {
> +				phy_exit(hpriv->phys[i]);
> +				return rc;
> +			}
> +		}
> +	}
>  
>  	if (of_property_read_bool(np, "ceva,broken-gen2"))
>  		cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
> 

Acked-by: Michal Simek <michal.simek@xilinx.com>

Jens:  Can you please take a look at this patch if you see any other issue?

Thanks,
Michal

Re: [PATCH V3 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy

[Jens Axboe]

On 2/8/21 11:03 AM, Piyush Mehta wrote:
> This patch series updates the ceva driver to add support for Xilinx GT phy.
> This also updates the documentation with the device tree binding required
> for working with Xilinx GT phy.

Applied for 5.13, thanks.

-- 
Jens Axboe