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From: Florian Fainelli <f.fainelli@gmail.com>
To: Dan Murphy <dmurphy@ti.com>,
	andrew@lunn.ch, hkallweit1@gmail.com, bunk@kernel.org
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, grygorii.strashko@ti.com
Subject: Re: [PATCH net-master 1/1] net: phy: dp83867: Add speed optimization feature
Date: Fri, 31 Jan 2020 10:42:05 -0800	[thread overview]
Message-ID: <5c956a5a-cd83-f290-9995-6ea35383f5f0@gmail.com> (raw)
In-Reply-To: <d03b5867-a55b-9abc-014f-69ce156b09f3@ti.com>

On 1/31/20 10:29 AM, Dan Murphy wrote:
> Florian
> 
> On 1/31/20 11:49 AM, Florian Fainelli wrote:
>> On 1/31/20 7:11 AM, Dan Murphy wrote:
>>> Set the speed optimization bit on the DP83867 PHY.
>>> This feature can also be strapped on the 64 pin PHY devices
>>> but the 48 pin devices do not have the strap pin available to enable
>>> this feature in the hardware.  PHY team suggests to have this bit set.
>> OK, but why and how does that optimization work exactly?
> 
> I described this in the cover letter.  And it is explained in the data
> sheet Section 8.4.6.6

Sorry I complete missed that and just focused on the patch, you should
consider not providing a cover letter for a single patch, and especially
not when the cover letter contains more information than the patch
commit message itself.

> 
>>   Departing from
>> the BMSR reads means you possibly are going to introduce bugs and/or
>> incomplete information. For instance, you set phydev->pause and
>> phydev->asym_pause to 0 now, is there no way to extract what the link
>> partner has advertised?
> 
> I was using the marvel.c as my template as it appears to have a separate
> status register as well.
> 
> Instead of setting those bits in the call back I can call the
> genphy_read_status then override the duplex and speed based on the
> physts register like below.  This way link status and pause values can
> be updated and then we can update the speed and duplex settings.
> 
>       ret = genphy_read_status(phydev);
>     if (ret)
>         return ret;
> 
>     if (status < 0)
>         return status;
> 
>     if (status & DP83867_PHYSTS_DUPLEX)
>         phydev->duplex = DUPLEX_FULL;
>     else
>         phydev->duplex = DUPLEX_HALF;
> 
>     if (status & DP83867_PHYSTS_1000)
>         phydev->speed = SPEED_1000;
>     else if (status & DP83867_PHYSTS_100)
>         phydev->speed = SPEED_100;
>     else
>         phydev->speed = SPEED_10;
> 

OK, but what if they disagree, are they consistently latched with
respect to one another?

> 
>>> With this bit set the PHY will auto negotiate and report the link
>>> parameters in the PHYSTS register and not in the BMCR.
>> That should be BMSR, the BMCR is about control, not status.
> 
> OK.
> 
> Dan
> 


-- 
Florian

  reply	other threads:[~2020-01-31 18:42 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-31 15:11 [PATCH net-master 0/1] DP83867 Speed " Dan Murphy
2020-01-31 15:11 ` [PATCH net-master 1/1] net: phy: dp83867: Add speed " Dan Murphy
2020-01-31 17:10   ` Jakub Kicinski
2020-01-31 17:14     ` Dan Murphy
2020-01-31 18:11       ` Jakub Kicinski
2020-01-31 18:36         ` Dan Murphy
2020-01-31 17:49   ` Florian Fainelli
2020-01-31 18:29     ` Dan Murphy
2020-01-31 18:42       ` Florian Fainelli [this message]
2020-01-31 19:14         ` Dan Murphy
2020-01-31 19:29           ` Florian Fainelli
2020-01-31 19:54             ` Dan Murphy
2020-01-31 20:02               ` Florian Fainelli
2020-01-31 20:10                 ` Dan Murphy
2020-01-31 20:56   ` Heiner Kallweit
2020-02-01  1:30     ` Dan Murphy
2020-02-01  4:57       ` Florian Fainelli

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