* [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs
@ 2022-10-26 19:04 Melody Olvera
2022-10-26 19:04 ` [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Melody Olvera
` (5 more replies)
0 siblings, 6 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-26 19:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
This series adds the GCC, RPMh, and PDC clock support required for the
QDU1000 and QRU1000 SoCs along with the devicetree bindings for them.
The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
1000 are new SoCs meant for enabling Open RAN solutions. See more at
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
This patchset is based on the YAML conversion patch [1] submitted already.
[1] https://lore.kernel.org/r/20220103074348.6039-1-luca.weiss@fairphone.com
Changes from v2:
- Revised dt-bindings
- Removed qru compat strings
- Updated some clocks to use clk_branch ops instead of clk_branch2 and HALT_ENABLE
Melody Olvera (4):
dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks
dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
Taniya Das (1):
clk: qcom: Add QDU1000 and QRU1000 GCC support
.../bindings/clock/qcom,gcc-qdu1000.yaml | 77 +
.../bindings/clock/qcom,rpmhcc.yaml | 1 +
.../interrupt-controller/qcom,pdc.yaml | 1 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 13 +
drivers/clk/qcom/gcc-qdu1000.c | 2645 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++
8 files changed, 2916 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
create mode 100644 drivers/clk/qcom/gcc-qdu1000.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h
base-commit: 60eac8672b5b6061ec07499c0f1b79f6d94311ce
--
2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
@ 2022-10-26 19:04 ` Melody Olvera
2022-10-27 15:54 ` Krzysztof Kozlowski
2022-11-07 17:25 ` Bjorn Andersson
2022-10-26 19:04 ` [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 Melody Olvera
` (4 subsequent siblings)
5 siblings, 2 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-26 19:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
Add device tree bindings for global clock controller on QDU1000 and
QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
.../bindings/clock/qcom,gcc-qdu1000.yaml | 77 ++++++++
include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++++++++++++++++++
2 files changed, 247 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
new file mode 100644
index 000000000000..ad460d628ffc
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+maintainers:
+ - Melody Olvera <quic_molvera@quicinc.com>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on QDU1000 and QRU1000
+
+ See also:
+ - include/dt-bindings/clock/qcom,gcc-qdu1000.h
+
+properties:
+ compatible:
+ items:
+ - const: qcom,gcc-qdu1000
+ - const: syscon
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE 0 Pipe clock source
+ - description: PCIE 0 Phy Auxiliary clock source
+ - description: USB3 Phy wrapper pipe clock source
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+ - const: pcie_0_pipe_clk
+ minItems: 2
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-qdu1000", "syscon";
+ reg = <0x00100000 0x001f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/qcom,gcc-qdu1000.h b/include/dt-bindings/clock/qcom,gcc-qdu1000.h
new file mode 100644
index 000000000000..99edb688fef2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qdu1000.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
+
+/* GCC clocks */
+#define GCC_GPLL0 0
+#define GCC_GPLL0_OUT_EVEN 1
+#define GCC_GPLL1 2
+#define GCC_GPLL2 3
+#define GCC_GPLL2_OUT_EVEN 4
+#define GCC_GPLL3 5
+#define GCC_GPLL4 6
+#define GCC_GPLL5 7
+#define GCC_GPLL5_OUT_EVEN 8
+#define GCC_GPLL6 9
+#define GCC_GPLL7 10
+#define GCC_GPLL8 11
+#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12
+#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13
+#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14
+#define GCC_BOOT_ROM_AHB_CLK 15
+#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
+#define GCC_DDRSS_ECPRI_DMA_CLK 18
+#define GCC_ECPRI_AHB_CLK 19
+#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20
+#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21
+#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22
+#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23
+#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24
+#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25
+#define GCC_ECPRI_XO_CLK 26
+#define GCC_ETH_DBG_SNOC_AXI_CLK 27
+#define GCC_GEMNOC_PCIE_QX_CLK 28
+#define GCC_GP1_CLK 29
+#define GCC_GP1_CLK_SRC 30
+#define GCC_GP2_CLK 31
+#define GCC_GP2_CLK_SRC 32
+#define GCC_GP3_CLK 33
+#define GCC_GP3_CLK_SRC 34
+#define GCC_PCIE_0_AUX_CLK 35
+#define GCC_PCIE_0_AUX_CLK_SRC 36
+#define GCC_PCIE_0_CFG_AHB_CLK 37
+#define GCC_PCIE_0_CLKREF_EN 38
+#define GCC_PCIE_0_MSTR_AXI_CLK 39
+#define GCC_PCIE_0_PHY_AUX_CLK 40
+#define GCC_PCIE_0_PHY_RCHNG_CLK 41
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
+#define GCC_PCIE_0_PIPE_CLK 43
+#define GCC_PCIE_0_SLV_AXI_CLK 44
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
+#define GCC_PDM2_CLK 46
+#define GCC_PDM2_CLK_SRC 47
+#define GCC_PDM_AHB_CLK 48
+#define GCC_PDM_XO4_CLK 49
+#define GCC_QMIP_ANOC_PCIE_CLK 50
+#define GCC_QMIP_ECPRI_DMA0_CLK 51
+#define GCC_QMIP_ECPRI_DMA1_CLK 52
+#define GCC_QMIP_ECPRI_GSI_CLK 53
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54
+#define GCC_QUPV3_WRAP0_CORE_CLK 55
+#define GCC_QUPV3_WRAP0_S0_CLK 56
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57
+#define GCC_QUPV3_WRAP0_S1_CLK 58
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59
+#define GCC_QUPV3_WRAP0_S2_CLK 60
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61
+#define GCC_QUPV3_WRAP0_S3_CLK 62
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63
+#define GCC_QUPV3_WRAP0_S4_CLK 64
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65
+#define GCC_QUPV3_WRAP0_S5_CLK 66
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67
+#define GCC_QUPV3_WRAP0_S6_CLK 68
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69
+#define GCC_QUPV3_WRAP0_S7_CLK 70
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72
+#define GCC_QUPV3_WRAP1_CORE_CLK 73
+#define GCC_QUPV3_WRAP1_S0_CLK 74
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75
+#define GCC_QUPV3_WRAP1_S1_CLK 76
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77
+#define GCC_QUPV3_WRAP1_S2_CLK 78
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79
+#define GCC_QUPV3_WRAP1_S3_CLK 80
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81
+#define GCC_QUPV3_WRAP1_S4_CLK 82
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83
+#define GCC_QUPV3_WRAP1_S5_CLK 84
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85
+#define GCC_QUPV3_WRAP1_S6_CLK 86
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87
+#define GCC_QUPV3_WRAP1_S7_CLK 88
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93
+#define GCC_SDCC5_AHB_CLK 94
+#define GCC_SDCC5_APPS_CLK 95
+#define GCC_SDCC5_APPS_CLK_SRC 96
+#define GCC_SDCC5_ICE_CORE_CLK 97
+#define GCC_SDCC5_ICE_CORE_CLK_SRC 98
+#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99
+#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100
+#define GCC_SNOC_CNOC_PCIE_QX_CLK 101
+#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102
+#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103
+#define GCC_TSC_CFG_AHB_CLK 104
+#define GCC_TSC_CLK_SRC 105
+#define GCC_TSC_CNTR_CLK 106
+#define GCC_TSC_ETU_CLK 107
+#define GCC_USB2_CLKREF_EN 108
+#define GCC_USB30_PRIM_MASTER_CLK 109
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113
+#define GCC_USB30_PRIM_SLEEP_CLK 114
+#define GCC_USB3_PRIM_PHY_AUX_CLK 115
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
+#define GCC_SM_BUS_AHB_CLK 119
+#define GCC_SM_BUS_XO_CLK 120
+#define GCC_SM_BUS_XO_CLK_SRC 121
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122
+#define GCC_ETH_100G_C2C_HM_APB_CLK 123
+#define GCC_ETH_100G_FH_HM_APB_0_CLK 124
+#define GCC_ETH_100G_FH_HM_APB_1_CLK 125
+#define GCC_ETH_100G_FH_HM_APB_2_CLK 126
+#define GCC_ETH_DBG_C2C_HM_APB_CLK 127
+#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
+#define GCC_PCIE_0_PIPE_CLK_SRC 129
+#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
+
+/* GCC resets */
+#define GCC_ECPRI_CC_BCR 0
+#define GCC_ECPRI_SS_BCR 1
+#define GCC_ETH_WRAPPER_BCR 2
+#define GCC_PCIE_0_BCR 3
+#define GCC_PCIE_0_LINK_DOWN_BCR 4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
+#define GCC_PCIE_0_PHY_BCR 6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
+#define GCC_PCIE_PHY_CFG_AHB_BCR 8
+#define GCC_PCIE_PHY_COM_BCR 9
+#define GCC_PDM_BCR 10
+#define GCC_QUPV3_WRAPPER_0_BCR 11
+#define GCC_QUPV3_WRAPPER_1_BCR 12
+#define GCC_QUSB2PHY_PRIM_BCR 13
+#define GCC_QUSB2PHY_SEC_BCR 14
+#define GCC_SDCC5_BCR 15
+#define GCC_TCSR_PCIE_BCR 16
+#define GCC_TSC_BCR 17
+#define GCC_USB30_PRIM_BCR 18
+#define GCC_USB3_DP_PHY_PRIM_BCR 19
+#define GCC_USB3_DP_PHY_SEC_BCR 20
+#define GCC_USB3_PHY_PRIM_BCR 21
+#define GCC_USB3_PHY_SEC_BCR 22
+#define GCC_USB3PHY_PHY_PRIM_BCR 23
+#define GCC_USB3PHY_PHY_SEC_BCR 24
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
2022-10-26 19:04 ` [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Melody Olvera
@ 2022-10-26 19:04 ` Melody Olvera
2022-10-27 15:57 ` Krzysztof Kozlowski
2022-11-07 17:36 ` Bjorn Andersson
2022-10-26 19:04 ` [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support Melody Olvera
` (3 subsequent siblings)
5 siblings, 2 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-26 19:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
Add compatible strings for RPMHCC for QDU1000 and QRU1000.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index 437a34b930e3..fccb91e78e49 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
+ - qcom,qdu1000-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
2022-10-26 19:04 ` [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Melody Olvera
2022-10-26 19:04 ` [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 Melody Olvera
@ 2022-10-26 19:04 ` Melody Olvera
2022-11-07 17:32 ` Bjorn Andersson
2022-10-26 19:04 ` [PATCH v3 4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks Melody Olvera
` (2 subsequent siblings)
5 siblings, 1 reply; 27+ messages in thread
From: Melody Olvera @ 2022-10-26 19:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
From: Taniya Das <quic_tdas@quicinc.com>
Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-qdu1000.c | 2645 ++++++++++++++++++++++++++++++++
3 files changed, 2654 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-qdu1000.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 76e6dee450d5..39abab7439ab 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -739,6 +739,14 @@ config SM_GCC_8450
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
+config QDU_GCC_1000
+ tristate "QDU1000/QRU1000 Global Clock Controller"
+ select QCOM_GDSC
+ help
+ Support for the global clock controller on QDU1000 and
+ QRU1000 devices. Say Y if you want to use peripheral
+ devices such as UART, SPI, I2C, USB, SD, PCIe, etc.
+
config SM_GPUCC_6350
tristate "SM6350 Graphics Clock Controller"
select SM_GCC_6350
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e6cecf9e0436..0fc518a83832 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
+obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o
obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
new file mode 100644
index 000000000000..7bd8ebf0ddb5
--- /dev/null
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -0,0 +1,2645 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gcc-qdu1000.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_GCC_GPLL0_OUT_EVEN,
+ P_GCC_GPLL0_OUT_MAIN,
+ P_GCC_GPLL1_OUT_MAIN,
+ P_GCC_GPLL2_OUT_MAIN,
+ P_GCC_GPLL3_OUT_MAIN,
+ P_GCC_GPLL4_OUT_MAIN,
+ P_GCC_GPLL5_OUT_MAIN,
+ P_GCC_GPLL6_OUT_MAIN,
+ P_GCC_GPLL7_OUT_MAIN,
+ P_GCC_GPLL8_OUT_MAIN,
+ P_PCIE_0_PHY_AUX_CLK,
+ P_PCIE_0_PIPE_CLK,
+ P_SLEEP_CLK,
+ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
+};
+
+static struct clk_alpha_pll gcc_gpll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll0",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
+ { 0x1, 2 }
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll0_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll1 = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll1",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = {
+ .offset = 0x1000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll1_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll1.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll2 = {
+ .offset = 0x2000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll2",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = {
+ .offset = 0x2000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll2_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll2.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll3 = {
+ .offset = 0x3000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll3",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll4 = {
+ .offset = 0x4000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll4",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll5 = {
+ .offset = 0x5000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll5",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = {
+ .offset = 0x5000,
+ .post_div_shift = 10,
+ .post_div_table = post_div_table_gcc_gpll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll5_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll5.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll6 = {
+ .offset = 0x6000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll6",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll7 = {
+ .offset = 0x7000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll7",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gcc_gpll8 = {
+ .offset = 0x8000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .enable_reg = 0x62018,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gpll8",
+ .parent_data = &(const struct clk_parent_data){
+ .index = P_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .index = P_SLEEP_CLK },
+ { .hw = &gcc_gpll0_out_even.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL5_OUT_MAIN, 3 },
+ { P_GCC_GPLL4_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll5.clkr.hw },
+ { .hw = &gcc_gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .index = P_BI_TCXO },
+ { .index = P_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL2_OUT_MAIN, 2 },
+ { P_GCC_GPLL5_OUT_MAIN, 3 },
+ { P_GCC_GPLL1_OUT_MAIN, 4 },
+ { P_GCC_GPLL4_OUT_MAIN, 5 },
+ { P_GCC_GPLL3_OUT_MAIN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_4[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll2.clkr.hw },
+ { .hw = &gcc_gpll5.clkr.hw },
+ { .hw = &gcc_gpll1.clkr.hw },
+ { .hw = &gcc_gpll4.clkr.hw },
+ { .hw = &gcc_gpll3.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL2_OUT_MAIN, 2 },
+ { P_GCC_GPLL6_OUT_MAIN, 3 },
+ { P_GCC_GPLL1_OUT_MAIN, 4 },
+ { P_GCC_GPLL4_OUT_MAIN, 5 },
+ { P_GCC_GPLL3_OUT_MAIN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_5[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll2.clkr.hw },
+ { .hw = &gcc_gpll6.clkr.hw },
+ { .hw = &gcc_gpll1.clkr.hw },
+ { .hw = &gcc_gpll4.clkr.hw },
+ { .hw = &gcc_gpll3.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+ { P_PCIE_0_PHY_AUX_CLK, 0 },
+ { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_6[] = {
+ { .index = P_PCIE_0_PHY_AUX_CLK },
+ { .index = P_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_7[] = {
+ { P_PCIE_0_PIPE_CLK, 0 },
+ { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_7[] = {
+ { .index = P_PCIE_0_PIPE_CLK },
+ { .index = P_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_8[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL8_OUT_MAIN, 2 },
+ { P_GCC_GPLL5_OUT_MAIN, 3 },
+ { P_GCC_GPLL4_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_8[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll8.clkr.hw },
+ { .hw = &gcc_gpll5.clkr.hw },
+ { .hw = &gcc_gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_9[] = {
+ { P_BI_TCXO, 0 },
+ { P_GCC_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL2_OUT_MAIN, 2 },
+ { P_GCC_GPLL5_OUT_MAIN, 3 },
+ { P_GCC_GPLL7_OUT_MAIN, 4 },
+ { P_GCC_GPLL4_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_9[] = {
+ { .index = P_BI_TCXO },
+ { .hw = &gcc_gpll0.clkr.hw },
+ { .hw = &gcc_gpll2.clkr.hw },
+ { .hw = &gcc_gpll5.clkr.hw },
+ { .hw = &gcc_gpll7.clkr.hw },
+ { .hw = &gcc_gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_10[] = {
+ { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
+ { P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_10[] = {
+ { .index = P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
+ { .index = P_BI_TCXO },
+};
+
+static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
+ .reg = 0x9d080,
+ .shift = 0,
+ .width = 2,
+ .parent_map = gcc_parent_map_6,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+ .reg = 0x9d064,
+ .shift = 0,
+ .width = 2,
+ .parent_map = gcc_parent_map_7,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_pipe_clk_src",
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
+ .reg = 0x4906c,
+ .shift = 0,
+ .width = 2,
+ .parent_map = gcc_parent_map_10,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_pipe_clk_src",
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = {
+ F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0),
+ F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = {
+ .cmd_rcgr = 0x92020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_aggre_noc_ecpri_dma_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = {
+ F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
+ F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = {
+ .cmd_rcgr = 0x92038,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_5,
+ .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_aggre_noc_ecpri_gsi_clk_src",
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x74004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp1_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x75004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp2_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp3_clk_src = {
+ .cmd_rcgr = 0x76004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp3_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
+ .cmd_rcgr = 0x9d068,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_aux_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
+ .cmd_rcgr = 0x9d04c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_phy_rchng_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+ F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+ .cmd_rcgr = 0x43010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pdm2_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pdm2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
+ F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
+ F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
+ F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
+ F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
+ F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
+ F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s0_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
+ .cmd_rcgr = 0x27154,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s1_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
+ .cmd_rcgr = 0x27288,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
+ .cmd_rcgr = 0x273bc,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s3_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
+ .cmd_rcgr = 0x274f0,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s4_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
+ .cmd_rcgr = 0x27624,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s5_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
+ .cmd_rcgr = 0x27758,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s6_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
+ .cmd_rcgr = 0x2788c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
+ .name = "gcc_qupv3_wrap0_s7_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
+ .cmd_rcgr = 0x279c0,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s0_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
+ .cmd_rcgr = 0x28154,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s1_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
+ .cmd_rcgr = 0x28288,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s2_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
+ .cmd_rcgr = 0x283bc,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s3_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
+ .cmd_rcgr = 0x284f0,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s4_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
+ .cmd_rcgr = 0x28624,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s5_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
+ .cmd_rcgr = 0x28758,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s6_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
+ .cmd_rcgr = 0x2888c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
+ .name = "gcc_qupv3_wrap1_s7_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
+ .cmd_rcgr = 0x289c0,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+ .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = {
+ F(144000, P_BI_TCXO, 16, 3, 25),
+ F(400000, P_BI_TCXO, 12, 1, 4),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3),
+ F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2),
+ F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
+ F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
+ F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+ F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
+ .cmd_rcgr = 0x3b034,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_8,
+ .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc5_apps_clk_src",
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = {
+ F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
+ .cmd_rcgr = 0x3b01c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc5_ice_core_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
+ .cmd_rcgr = 0x5b00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_sm_bus_xo_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = {
+ F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_tsc_clk_src = {
+ .cmd_rcgr = 0x57010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_9,
+ .freq_tbl = ftbl_gcc_tsc_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_tsc_clk_src",
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
+ F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
+ .cmd_rcgr = 0x49028,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb30_prim_master_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x49044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb30_prim_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
+ .cmd_rcgr = 0x49070,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_aux_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
+ .reg = 0x4905c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = {
+ .halt_reg = 0x92008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x92008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x92008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_aggre_noc_ecpri_dma_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = {
+ .halt_reg = 0x9201c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9201c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x9201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_aggre_noc_ecpri_gsi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x48004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = {
+ .halt_reg = 0x3e004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x3e004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3e004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_cfg_noc_ecpri_cc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
+ .halt_reg = 0x8401c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8401c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_prim_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
+ .halt_reg = 0x54030,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x54030,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x54030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ddrss_ecpri_dma_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_ahb_clk = {
+ .halt_reg = 0x3a008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x3a008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x62010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_cc_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x62010,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_cc_gpll1_even_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll1_out_even.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x62010,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_cc_gpll2_even_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll2_out_even.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x62010,
+ .enable_mask = BIT(3),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_cc_gpll3_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll3.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x62010,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_cc_gpll4_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll4.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = {
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x62010,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_cc_gpll5_even_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gpll5_out_even.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ecpri_xo_clk = {
+ .halt_reg = 0x3a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ecpri_xo_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = {
+ .halt_reg = 0x39010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x39010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_eth_100g_c2c_hm_apb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = {
+ .halt_reg = 0x39004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x39004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_eth_100g_fh_hm_apb_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = {
+ .halt_reg = 0x39008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x39008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_eth_100g_fh_hm_apb_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = {
+ .halt_reg = 0x3900c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3900c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_eth_100g_fh_hm_apb_2_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = {
+ .halt_reg = 0x39014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x39014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_eth_dbg_c2c_hm_apb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_eth_dbg_snoc_axi_clk = {
+ .halt_reg = 0x3901c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x3901c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x3901c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_eth_dbg_snoc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gemnoc_pcie_qx_clk = {
+ .halt_reg = 0x5402c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x5402c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gemnoc_pcie_qx_clk",
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x74000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x74000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x75000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x76000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gp3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+ .halt_reg = 0x9d030,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d030,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(29),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+ .halt_reg = 0x9d02c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d02c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(28),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_clkref_en = {
+ .halt_reg = 0x9c004,
+ .halt_bit = 31,
+ .halt_check = BRANCH_HALT_ENABLE,
+ .clkr = {
+ .enable_reg = 0x9c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_clkref_en",
+ .ops = &clk_branch_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+ .halt_reg = 0x9d024,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x9d024,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(27),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_mstr_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_phy_aux_clk = {
+ .halt_reg = 0x9d038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d038,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_0_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
+ .halt_reg = 0x9d048,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d048,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(23),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_phy_rchng_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+ .halt_reg = 0x9d040,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(30),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_0_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+ .halt_reg = 0x9d01c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d01c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_slv_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
+ .halt_reg = 0x9d018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x9d018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_0_slv_q2a_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x4300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pdm2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x43004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x43004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x43004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+ .halt_reg = 0x43008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x43008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pdm_xo4_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_anoc_pcie_clk = {
+ .halt_reg = 0x84044,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x84044,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x84044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qmip_anoc_pcie_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_ecpri_dma0_clk = {
+ .halt_reg = 0x84038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x84038,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x84038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qmip_ecpri_dma0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_ecpri_dma1_clk = {
+ .halt_reg = 0x8403c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8403c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8403c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qmip_ecpri_dma1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qmip_ecpri_gsi_clk = {
+ .halt_reg = 0x84040,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x84040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x84040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qmip_ecpri_gsi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
+ .halt_reg = 0x27018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(9),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_core_clk = {
+ .halt_reg = 0x2700c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(8),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
+ .halt_reg = 0x2714c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
+ .halt_reg = 0x27280,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(11),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
+ .halt_reg = 0x273b4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(12),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
+ .halt_reg = 0x274e8,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(13),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s3_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
+ .halt_reg = 0x2761c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(14),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s4_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
+ .halt_reg = 0x27750,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(15),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s5_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
+ .halt_reg = 0x27884,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(16),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s6_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
+ .halt_reg = 0x279b8,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(17),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap0_s7_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
+ .halt_reg = 0x28018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(18),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_core_2x_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_core_clk = {
+ .halt_reg = 0x2800c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_core_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
+ .halt_reg = 0x2814c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(22),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
+ .halt_reg = 0x28280,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(23),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
+ .halt_reg = 0x283b4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(24),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
+ .halt_reg = 0x284e8,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(25),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s3_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
+ .halt_reg = 0x2861c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(26),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s4_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
+ .halt_reg = 0x28750,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(27),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s5_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
+ .halt_reg = 0x28884,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(28),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s6_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
+ .halt_reg = 0x289b8,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(29),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap1_s7_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x27004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap_0_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
+ .halt_reg = 0x27008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x27008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(7),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap_0_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
+ .halt_reg = 0x28004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x28004,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(20),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap_1_m_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
+ .halt_reg = 0x28008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x28008,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62008,
+ .enable_mask = BIT(21),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qupv3_wrap_1_s_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc5_ahb_clk = {
+ .halt_reg = 0x3b00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3b00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc5_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc5_apps_clk = {
+ .halt_reg = 0x3b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc5_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sdcc5_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc5_ice_core_clk = {
+ .halt_reg = 0x3b010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3b010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc5_ice_core_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sdcc5_ice_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sm_bus_ahb_clk = {
+ .halt_reg = 0x5b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sm_bus_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sm_bus_xo_clk = {
+ .halt_reg = 0x5b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sm_bus_xo_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sm_bus_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = {
+ .halt_reg = 0x9200c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x9200c,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(11),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = {
+ .halt_reg = 0x92010,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x92010,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(12),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = {
+ .halt_reg = 0x84030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x84030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_cnoc_pcie_qx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = {
+ .halt_reg = 0x92014,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x92014,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(19),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie_sf_center_qx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = {
+ .halt_reg = 0x92018,
+ .halt_check = BRANCH_HALT_SKIP,
+ .hwcg_reg = 0x92018,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x62000,
+ .enable_mask = BIT(22),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie_sf_south_qx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_tsc_cfg_ahb_clk = {
+ .halt_reg = 0x5700c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5700c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_tsc_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_tsc_cntr_clk = {
+ .halt_reg = 0x57004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x57004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_tsc_cntr_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_tsc_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_tsc_etu_clk = {
+ .halt_reg = 0x57008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x57008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_tsc_etu_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_tsc_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb2_clkref_en = {
+ .halt_reg = 0x9c008,
+ .halt_bit = 31,
+ .halt_check = BRANCH_HALT_ENABLE,
+ .clkr = {
+ .enable_reg = 0x9c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb2_clkref_en",
+ .ops = &clk_branch_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_master_clk = {
+ .halt_reg = 0x49018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x49018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb30_prim_master_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb30_prim_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
+ .halt_reg = 0x49024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x49024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb30_prim_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_prim_sleep_clk = {
+ .halt_reg = 0x49020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x49020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb30_prim_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
+ .halt_reg = 0x49060,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x49060,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
+ .halt_reg = 0x49064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x49064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_com_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
+ .halt_reg = 0x49068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .hwcg_reg = 0x49068,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x49068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb3_prim_phy_pipe_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *gcc_qdu1000_clocks[] = {
+ [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,
+ [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
+ [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr,
+ [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
+ [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr,
+ [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr,
+ [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr,
+ [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr,
+ [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr,
+ [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr,
+ [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr,
+ [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr,
+ [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr,
+ [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr,
+ [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
+ [GCC_GPLL0] = &gcc_gpll0.clkr,
+ [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
+ [GCC_GPLL1] = &gcc_gpll1.clkr,
+ [GCC_GPLL2] = &gcc_gpll2.clkr,
+ [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr,
+ [GCC_GPLL3] = &gcc_gpll3.clkr,
+ [GCC_GPLL4] = &gcc_gpll4.clkr,
+ [GCC_GPLL5] = &gcc_gpll5.clkr,
+ [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr,
+ [GCC_GPLL6] = &gcc_gpll6.clkr,
+ [GCC_GPLL7] = &gcc_gpll7.clkr,
+ [GCC_GPLL8] = &gcc_gpll8.clkr,
+ [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+ [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
+ [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+ [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
+ [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+ [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
+ [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
+ [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
+ [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+ [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+ [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+ [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr,
+ [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr,
+ [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr,
+ [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr,
+ [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
+ [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
+ [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
+ [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
+ [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
+ [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
+ [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
+ [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
+ [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
+ [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
+ [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
+ [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
+ [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
+ [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
+ [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
+ [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
+ [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
+ [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
+ [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
+ [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
+ [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
+ [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
+ [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
+ [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
+ [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr,
+ [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr,
+ [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr,
+ [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr,
+ [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr,
+ [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr,
+ [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr,
+ [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr,
+ [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr,
+ [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr,
+ [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr,
+ [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr,
+ [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr,
+ [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr,
+ [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr,
+ [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr,
+ [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr,
+ [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr,
+ [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
+ [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
+ [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
+ [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
+ [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
+ [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
+ [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
+ [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
+ [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
+ [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr,
+ [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr,
+ [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr,
+ [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr,
+ [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr,
+ [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
+ [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
+ [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+};
+
+static const struct qcom_reset_map gcc_qdu1000_resets[] = {
+ [GCC_ECPRI_CC_BCR] = { 0x3e000 },
+ [GCC_ECPRI_SS_BCR] = { 0x3a000 },
+ [GCC_ETH_WRAPPER_BCR] = { 0x39000 },
+ [GCC_PCIE_0_BCR] = { 0x9d000 },
+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 },
+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x7c000 },
+ [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
+ [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
+ [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
+ [GCC_PDM_BCR] = { 0x43000 },
+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
+ [GCC_SDCC5_BCR] = { 0x3b000 },
+ [GCC_TSC_BCR] = { 0x57000 },
+ [GCC_USB30_PRIM_BCR] = { 0x49000 },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
+ [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
+};
+
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
+};
+
+static const struct regmap_config gcc_qdu1000_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1f41f0,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_qdu1000_desc = {
+ .config = &gcc_qdu1000_regmap_config,
+ .clks = gcc_qdu1000_clocks,
+ .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),
+ .resets = gcc_qdu1000_resets,
+ .num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
+};
+
+static const struct of_device_id gcc_qdu1000_match_table[] = {
+ { .compatible = "qcom,gcc-qdu1000" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table);
+
+static int gcc_qdu1000_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ int ret;
+
+ regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */
+ regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14));
+
+ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+ ARRAY_SIZE(gcc_dfs_clocks));
+ if (ret)
+ return ret;
+
+ ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n");
+
+ return ret;
+}
+
+static struct platform_driver gcc_qdu1000_driver = {
+ .probe = gcc_qdu1000_probe,
+ .driver = {
+ .name = "gcc-qdu1000",
+ .of_match_table = gcc_qdu1000_match_table,
+ },
+};
+
+static int __init gcc_qdu1000_init(void)
+{
+ return platform_driver_register(&gcc_qdu1000_driver);
+}
+subsys_initcall(gcc_qdu1000_init);
+
+static void __exit gcc_qdu1000_exit(void)
+{
+ platform_driver_unregister(&gcc_qdu1000_driver);
+}
+module_exit(gcc_qdu1000_exit);
+
+MODULE_DESCRIPTION("QTI GCC QDU1000 Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
` (2 preceding siblings ...)
2022-10-26 19:04 ` [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support Melody Olvera
@ 2022-10-26 19:04 ` Melody Olvera
2022-10-26 19:04 ` [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 Melody Olvera
2022-11-08 1:27 ` (subset) [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Bjorn Andersson
5 siblings, 0 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-26 19:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
Add support for RMPh clocks for QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
drivers/clk/qcom/clk-rpmh.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 0471bab82464..1da45a6e2f29 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -644,6 +644,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
.num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
};
+DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1);
+
+static struct clk_hw *qdu1000_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw,
+ [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
+ .clks = qdu1000_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks),
+};
+
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -727,6 +739,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
}
static const struct of_device_id clk_rpmh_match_table[] = {
+ { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
{ .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
` (3 preceding siblings ...)
2022-10-26 19:04 ` [PATCH v3 4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks Melody Olvera
@ 2022-10-26 19:04 ` Melody Olvera
2022-10-27 15:58 ` Krzysztof Kozlowski
2022-10-27 18:22 ` Stephen Boyd
2022-11-08 1:27 ` (subset) [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Bjorn Andersson
5 siblings, 2 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-26 19:04 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
Add compatible fields for QDU1000 and QRU1000 pdcs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index b6f56cf5fbe3..afeed7b8c0fa 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -26,6 +26,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,qdu1000-pdc
- qcom,sc7180-pdc
- qcom,sc7280-pdc
- qcom,sdm845-pdc
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-26 19:04 ` [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Melody Olvera
@ 2022-10-27 15:54 ` Krzysztof Kozlowski
2022-10-27 18:24 ` Stephen Boyd
2022-11-07 17:25 ` Bjorn Andersson
1 sibling, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:54 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Thomas Gleixner,
Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 26/10/2022 15:04, Melody Olvera wrote:
> Add device tree bindings for global clock controller on QDU1000 and
> QRU1000 SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> .../bindings/clock/qcom,gcc-qdu1000.yaml | 77 ++++++++
> include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++++++++++++++++++
> 2 files changed, 247 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
> new file mode 100644
> index 000000000000..ad460d628ffc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +maintainers:
> + - Melody Olvera <quic_molvera@quicinc.com>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on QDU1000 and QRU1000
> +
> + See also:
> + - include/dt-bindings/clock/qcom,gcc-qdu1000.h
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,gcc-qdu1000
> + - const: syscon
> +
> + clocks:
> + items:
> + - description: Board XO source
> + - description: Sleep clock source
> + - description: PCIE 0 Pipe clock source
> + - description: PCIE 0 Phy Auxiliary clock source
> + - description: USB3 Phy wrapper pipe clock source
> + minItems: 2
Why the clocks are optional?
> +
> + clock-names:
> + items:
> + - const: bi_tcxo
> + - const: sleep_clk
> + - const: pcie_0_pipe_clk
> + minItems: 2
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
2022-10-26 19:04 ` [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 Melody Olvera
@ 2022-10-27 15:57 ` Krzysztof Kozlowski
2022-10-28 1:04 ` Melody Olvera
2022-11-07 17:36 ` Bjorn Andersson
1 sibling, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:57 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Thomas Gleixner,
Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 26/10/2022 15:04, Melody Olvera wrote:
> Add compatible strings for RPMHCC for QDU1000 and QRU1000.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
This looks correct except:
1. redundant bindings in subject
2. not cc-ing all maintainers
so still not tag.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-10-26 19:04 ` [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 Melody Olvera
@ 2022-10-27 15:58 ` Krzysztof Kozlowski
2022-10-27 18:22 ` Stephen Boyd
1 sibling, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 15:58 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Thomas Gleixner,
Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 26/10/2022 15:04, Melody Olvera wrote:
> Add compatible fields for QDU1000 and QRU1000 pdcs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Looks ok, except usual stuff to fix...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-10-26 19:04 ` [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 Melody Olvera
2022-10-27 15:58 ` Krzysztof Kozlowski
@ 2022-10-27 18:22 ` Stephen Boyd
2022-10-27 21:31 ` Melody Olvera
1 sibling, 1 reply; 27+ messages in thread
From: Stephen Boyd @ 2022-10-27 18:22 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Krzysztof Kozlowski, Marc Zyngier,
Melody Olvera, Michael Turquette, Rob Herring, Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel,
Melody Olvera
Quoting Melody Olvera (2022-10-26 12:04:41)
> Add compatible fields for QDU1000 and QRU1000 pdcs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
Is there a reason why this patch continues to be included in what is
otherwise a clk driver patch series? Can this patch be sent separately
from the clk patches (and not Cced to clk maintainers/list) in the
future?
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-27 15:54 ` Krzysztof Kozlowski
@ 2022-10-27 18:24 ` Stephen Boyd
2022-10-27 19:35 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Stephen Boyd @ 2022-10-27 18:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Krzysztof Kozlowski, Marc Zyngier, Melody Olvera,
Michael Turquette, Rob Herring, Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
Quoting Krzysztof Kozlowski (2022-10-27 08:54:51)
> On 26/10/2022 15:04, Melody Olvera wrote:
> > +description: |
> > + Qualcomm global clock control module which supports the clocks, resets and
> > + power domains on QDU1000 and QRU1000
> > +
> > + See also:
> > + - include/dt-bindings/clock/qcom,gcc-qdu1000.h
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: qcom,gcc-qdu1000
> > + - const: syscon
> > +
> > + clocks:
> > + items:
> > + - description: Board XO source
> > + - description: Sleep clock source
> > + - description: PCIE 0 Pipe clock source
> > + - description: PCIE 0 Phy Auxiliary clock source
> > + - description: USB3 Phy wrapper pipe clock source
> > + minItems: 2
>
> Why the clocks are optional?
They should not be optional. They're always there.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-27 18:24 ` Stephen Boyd
@ 2022-10-27 19:35 ` Krzysztof Kozlowski
2022-10-27 21:28 ` Melody Olvera
0 siblings, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 19:35 UTC (permalink / raw)
To: Stephen Boyd, Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Marc Zyngier, Melody Olvera, Michael Turquette, Rob Herring,
Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 27/10/2022 14:24, Stephen Boyd wrote:
> Quoting Krzysztof Kozlowski (2022-10-27 08:54:51)
>> On 26/10/2022 15:04, Melody Olvera wrote:
>>> +description: |
>>> + Qualcomm global clock control module which supports the clocks, resets and
>>> + power domains on QDU1000 and QRU1000
>>> +
>>> + See also:
>>> + - include/dt-bindings/clock/qcom,gcc-qdu1000.h
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - const: qcom,gcc-qdu1000
>>> + - const: syscon
>>> +
>>> + clocks:
>>> + items:
>>> + - description: Board XO source
>>> + - description: Sleep clock source
>>> + - description: PCIE 0 Pipe clock source
>>> + - description: PCIE 0 Phy Auxiliary clock source
>>> + - description: USB3 Phy wrapper pipe clock source
>>> + minItems: 2
>>
>> Why the clocks are optional?
>
> They should not be optional. They're always there.
Just to be sure - I refer to last three clocks here as indicated by
minItems:2.
DTS does not define them, so something here is not complete or correct.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-27 19:35 ` Krzysztof Kozlowski
@ 2022-10-27 21:28 ` Melody Olvera
2022-10-27 21:59 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Melody Olvera @ 2022-10-27 21:28 UTC (permalink / raw)
To: Krzysztof Kozlowski, Stephen Boyd, Andy Gross, Bjorn Andersson,
Krzysztof Kozlowski, Marc Zyngier, Michael Turquette,
Rob Herring, Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 10/27/2022 12:35 PM, Krzysztof Kozlowski wrote:
> On 27/10/2022 14:24, Stephen Boyd wrote:
>> Quoting Krzysztof Kozlowski (2022-10-27 08:54:51)
>>> On 26/10/2022 15:04, Melody Olvera wrote:
>>>> +description: |
>>>> + Qualcomm global clock control module which supports the clocks, resets and
>>>> + power domains on QDU1000 and QRU1000
>>>> +
>>>> + See also:
>>>> + - include/dt-bindings/clock/qcom,gcc-qdu1000.h
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + items:
>>>> + - const: qcom,gcc-qdu1000
>>>> + - const: syscon
>>>> +
>>>> + clocks:
>>>> + items:
>>>> + - description: Board XO source
>>>> + - description: Sleep clock source
>>>> + - description: PCIE 0 Pipe clock source
>>>> + - description: PCIE 0 Phy Auxiliary clock source
>>>> + - description: USB3 Phy wrapper pipe clock source
>>>> + minItems: 2
>>> Why the clocks are optional?
>> They should not be optional. They're always there.
> Just to be sure - I refer to last three clocks here as indicated by
> minItems:2.
>
> DTS does not define them, so something here is not complete or correct.
>
DT is incomplete; I don't have that in my current patchset. Will add later when PCIE and
USB nodes are complete.
Thanks,
Melody
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-10-27 18:22 ` Stephen Boyd
@ 2022-10-27 21:31 ` Melody Olvera
2022-10-27 21:38 ` Stephen Boyd
2022-11-07 17:16 ` Bjorn Andersson
0 siblings, 2 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-27 21:31 UTC (permalink / raw)
To: Stephen Boyd, Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Marc Zyngier, Michael Turquette, Rob Herring, Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 10/27/2022 11:22 AM, Stephen Boyd wrote:
> Quoting Melody Olvera (2022-10-26 12:04:41)
>> Add compatible fields for QDU1000 and QRU1000 pdcs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
> Is there a reason why this patch continues to be included in what is
> otherwise a clk driver patch series? Can this patch be sent separately
> from the clk patches (and not Cced to clk maintainers/list) in the
> future?
Sure thing. On reflection, this belongs with the misc support patches.
Thanks,
Melody
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-10-27 21:31 ` Melody Olvera
@ 2022-10-27 21:38 ` Stephen Boyd
2022-11-07 17:16 ` Bjorn Andersson
1 sibling, 0 replies; 27+ messages in thread
From: Stephen Boyd @ 2022-10-27 21:38 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Krzysztof Kozlowski, Marc Zyngier,
Melody Olvera, Michael Turquette, Rob Herring, Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
Quoting Melody Olvera (2022-10-27 14:31:08)
>
>
> On 10/27/2022 11:22 AM, Stephen Boyd wrote:
> > Quoting Melody Olvera (2022-10-26 12:04:41)
> >> Add compatible fields for QDU1000 and QRU1000 pdcs.
> >>
> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> >> ---
> > Is there a reason why this patch continues to be included in what is
> > otherwise a clk driver patch series? Can this patch be sent separately
> > from the clk patches (and not Cced to clk maintainers/list) in the
> > future?
> Sure thing. On reflection, this belongs with the misc support patches.
>
Thanks!
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-27 21:28 ` Melody Olvera
@ 2022-10-27 21:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-27 21:59 UTC (permalink / raw)
To: Melody Olvera, Stephen Boyd, Andy Gross, Bjorn Andersson,
Krzysztof Kozlowski, Marc Zyngier, Michael Turquette,
Rob Herring, Thomas Gleixner
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 27/10/2022 17:28, Melody Olvera wrote:
>>>>> + - description: Board XO source
>>>>> + - description: Sleep clock source
>>>>> + - description: PCIE 0 Pipe clock source
>>>>> + - description: PCIE 0 Phy Auxiliary clock source
>>>>> + - description: USB3 Phy wrapper pipe clock source
>>>>> + minItems: 2
>>>> Why the clocks are optional?
>>> They should not be optional. They're always there.
>> Just to be sure - I refer to last three clocks here as indicated by
>> minItems:2.
>>
>> DTS does not define them, so something here is not complete or correct.
>>
> DT is incomplete; I don't have that in my current patchset. Will add later when PCIE and
> USB nodes are complete.
Bindings should be complete as much as possible, therefore please define
in the DTS stub clocks (fixed clocks) to fill these with a TODO notes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
2022-10-27 15:57 ` Krzysztof Kozlowski
@ 2022-10-28 1:04 ` Melody Olvera
2022-10-28 1:09 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Melody Olvera @ 2022-10-28 1:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 10/27/2022 8:57 AM, Krzysztof Kozlowski wrote:
> On 26/10/2022 15:04, Melody Olvera wrote:
>> Add compatible strings for RPMHCC for QDU1000 and QRU1000.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
> This looks correct except:
> 1. redundant bindings in subject
> 2. not cc-ing all maintainers
>
> so still not tag.
>
>
Not sure what you mean by redundant bindings; should I remove
"QRU1000"? "Compatible strings"? Please advise.
Also, I got maintainers from running get_maintainers.pl on
linux-next/master; is this wrong? Not sure what I'm missing here.
Thanks,
Melody
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
2022-10-28 1:04 ` Melody Olvera
@ 2022-10-28 1:09 ` Krzysztof Kozlowski
2022-10-28 16:54 ` Melody Olvera
0 siblings, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-28 1:09 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Thomas Gleixner,
Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 27/10/2022 21:04, Melody Olvera wrote:
>
>
> On 10/27/2022 8:57 AM, Krzysztof Kozlowski wrote:
>> On 26/10/2022 15:04, Melody Olvera wrote:
>>> Add compatible strings for RPMHCC for QDU1000 and QRU1000.
>>>
>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>> ---
>> This looks correct except:
>> 1. redundant bindings in subject
>> 2. not cc-ing all maintainers
>>
>> so still not tag.
>>
>>
> Not sure what you mean by redundant bindings; should I remove
> "QRU1000"? "Compatible strings"? Please advise.
In the subject please drop second 'bindings' word, because it is
redundant so:
dt-bindings: clock: Add RPMHCC for QDU1000 and QRU1000
or
dt-bindings: clock: Add QDU1000/QRU1000 RPMHCC
>
> Also, I got maintainers from running get_maintainers.pl on
> linux-next/master; is this wrong? Not sure what I'm missing here.
You miss some of Qualcomm maintainers. Maybe more, I did not check every
possible output for every patchset. I just spotted missing Konrad,
because it sticks out. If you copy the output of some commands, be sure
you copy everything. Otherwise, just automate it so there will be no
chances for mistakes.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
2022-10-28 1:09 ` Krzysztof Kozlowski
@ 2022-10-28 16:54 ` Melody Olvera
0 siblings, 0 replies; 27+ messages in thread
From: Melody Olvera @ 2022-10-28 16:54 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier
Cc: Taniya Das, linux-arm-msm, linux-clk, devicetree, linux-kernel
On 10/27/2022 6:09 PM, Krzysztof Kozlowski wrote:
> On 27/10/2022 21:04, Melody Olvera wrote:
>>
>> On 10/27/2022 8:57 AM, Krzysztof Kozlowski wrote:
>>> On 26/10/2022 15:04, Melody Olvera wrote:
>>>> Add compatible strings for RPMHCC for QDU1000 and QRU1000.
>>>>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
>>> This looks correct except:
>>> 1. redundant bindings in subject
>>> 2. not cc-ing all maintainers
>>>
>>> so still not tag.
>>>
>>>
>> Not sure what you mean by redundant bindings; should I remove
>> "QRU1000"? "Compatible strings"? Please advise.
> In the subject please drop second 'bindings' word, because it is
> redundant so:
>
> dt-bindings: clock: Add RPMHCC for QDU1000 and QRU1000
> or
> dt-bindings: clock: Add QDU1000/QRU1000 RPMHCC
Oh ok that makes sense. Sorry about the confusion.
>
>> Also, I got maintainers from running get_maintainers.pl on
>> linux-next/master; is this wrong? Not sure what I'm missing here.
> You miss some of Qualcomm maintainers. Maybe more, I did not check every
> possible output for every patchset. I just spotted missing Konrad,
> because it sticks out. If you copy the output of some commands, be sure
> you copy everything. Otherwise, just automate it so there will be no
> chances for mistakes.
Ah ok no worries. Will make sure my copy-paste is thorough.
Thanks,
Melody
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-10-27 21:31 ` Melody Olvera
2022-10-27 21:38 ` Stephen Boyd
@ 2022-11-07 17:16 ` Bjorn Andersson
2022-11-07 23:20 ` Melody Olvera
1 sibling, 1 reply; 27+ messages in thread
From: Bjorn Andersson @ 2022-11-07 17:16 UTC (permalink / raw)
To: Melody Olvera
Cc: Stephen Boyd, Andy Gross, Krzysztof Kozlowski, Marc Zyngier,
Michael Turquette, Rob Herring, Thomas Gleixner, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On Thu, Oct 27, 2022 at 02:31:08PM -0700, Melody Olvera wrote:
>
>
> On 10/27/2022 11:22 AM, Stephen Boyd wrote:
> > Quoting Melody Olvera (2022-10-26 12:04:41)
> >> Add compatible fields for QDU1000 and QRU1000 pdcs.
> >>
> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> >> ---
> > Is there a reason why this patch continues to be included in what is
> > otherwise a clk driver patch series? Can this patch be sent separately
> > from the clk patches (and not Cced to clk maintainers/list) in the
> > future?
> Sure thing. On reflection, this belongs with the misc support patches.
>
Even better, the "misc" series goes through my tree but this patch is
unrelated. So if you send it on it's own it could just be picked up by
the PDC maintainer (or Rob).
Regards,
Bjorn
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-10-26 19:04 ` [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Melody Olvera
2022-10-27 15:54 ` Krzysztof Kozlowski
@ 2022-11-07 17:25 ` Bjorn Andersson
2022-11-07 23:03 ` Melody Olvera
1 sibling, 1 reply; 27+ messages in thread
From: Bjorn Andersson @ 2022-11-07 17:25 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On Wed, Oct 26, 2022 at 12:04:37PM -0700, Melody Olvera wrote:
> Add device tree bindings for global clock controller on QDU1000 and
> QRU1000 SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> .../bindings/clock/qcom,gcc-qdu1000.yaml | 77 ++++++++
> include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++++++++++++++++++
> 2 files changed, 247 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
> create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
> new file mode 100644
> index 000000000000..ad460d628ffc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +maintainers:
> + - Melody Olvera <quic_molvera@quicinc.com>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on QDU1000 and QRU1000
> +
> + See also:
> + - include/dt-bindings/clock/qcom,gcc-qdu1000.h
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,gcc-qdu1000
> + - const: syscon
> +
> + clocks:
> + items:
> + - description: Board XO source
> + - description: Sleep clock source
> + - description: PCIE 0 Pipe clock source
> + - description: PCIE 0 Phy Auxiliary clock source
> + - description: USB3 Phy wrapper pipe clock source
> + minItems: 2
They should all be required by the binding, but I will accept .dts
files with not yet available sources specified as <0>.
> +
> + clock-names:
Including clock-names in the binding indicates that clocks are indexed
based on these names (which is what we've done for many years now).
As we're transitioning the clock providers to rely solely on the
ordering of clocks, I prefer that we omit the clock-names property, just
to make it clear that clock-names is effectively ignored by Linux.
> + items:
> + - const: bi_tcxo
> + - const: sleep_clk
> + - const: pcie_0_pipe_clk
> + minItems: 2
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + clock-controller@100000 {
> + compatible = "qcom,gcc-qdu1000", "syscon";
> + reg = <0x00100000 0x001f4200>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
This is just an example, so please make up some plausible sources for
the remaining clocks.
Regards,
Bjorn
> + clock-names = "bi_tcxo", "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/qcom,gcc-qdu1000.h b/include/dt-bindings/clock/qcom,gcc-qdu1000.h
> new file mode 100644
> index 000000000000..99edb688fef2
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-qdu1000.h
> @@ -0,0 +1,170 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
> +
> +/* GCC clocks */
> +#define GCC_GPLL0 0
> +#define GCC_GPLL0_OUT_EVEN 1
> +#define GCC_GPLL1 2
> +#define GCC_GPLL2 3
> +#define GCC_GPLL2_OUT_EVEN 4
> +#define GCC_GPLL3 5
> +#define GCC_GPLL4 6
> +#define GCC_GPLL5 7
> +#define GCC_GPLL5_OUT_EVEN 8
> +#define GCC_GPLL6 9
> +#define GCC_GPLL7 10
> +#define GCC_GPLL8 11
> +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12
> +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13
> +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14
> +#define GCC_BOOT_ROM_AHB_CLK 15
> +#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16
> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
> +#define GCC_DDRSS_ECPRI_DMA_CLK 18
> +#define GCC_ECPRI_AHB_CLK 19
> +#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20
> +#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21
> +#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22
> +#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23
> +#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24
> +#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25
> +#define GCC_ECPRI_XO_CLK 26
> +#define GCC_ETH_DBG_SNOC_AXI_CLK 27
> +#define GCC_GEMNOC_PCIE_QX_CLK 28
> +#define GCC_GP1_CLK 29
> +#define GCC_GP1_CLK_SRC 30
> +#define GCC_GP2_CLK 31
> +#define GCC_GP2_CLK_SRC 32
> +#define GCC_GP3_CLK 33
> +#define GCC_GP3_CLK_SRC 34
> +#define GCC_PCIE_0_AUX_CLK 35
> +#define GCC_PCIE_0_AUX_CLK_SRC 36
> +#define GCC_PCIE_0_CFG_AHB_CLK 37
> +#define GCC_PCIE_0_CLKREF_EN 38
> +#define GCC_PCIE_0_MSTR_AXI_CLK 39
> +#define GCC_PCIE_0_PHY_AUX_CLK 40
> +#define GCC_PCIE_0_PHY_RCHNG_CLK 41
> +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
> +#define GCC_PCIE_0_PIPE_CLK 43
> +#define GCC_PCIE_0_SLV_AXI_CLK 44
> +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
> +#define GCC_PDM2_CLK 46
> +#define GCC_PDM2_CLK_SRC 47
> +#define GCC_PDM_AHB_CLK 48
> +#define GCC_PDM_XO4_CLK 49
> +#define GCC_QMIP_ANOC_PCIE_CLK 50
> +#define GCC_QMIP_ECPRI_DMA0_CLK 51
> +#define GCC_QMIP_ECPRI_DMA1_CLK 52
> +#define GCC_QMIP_ECPRI_GSI_CLK 53
> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54
> +#define GCC_QUPV3_WRAP0_CORE_CLK 55
> +#define GCC_QUPV3_WRAP0_S0_CLK 56
> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57
> +#define GCC_QUPV3_WRAP0_S1_CLK 58
> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59
> +#define GCC_QUPV3_WRAP0_S2_CLK 60
> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61
> +#define GCC_QUPV3_WRAP0_S3_CLK 62
> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63
> +#define GCC_QUPV3_WRAP0_S4_CLK 64
> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65
> +#define GCC_QUPV3_WRAP0_S5_CLK 66
> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67
> +#define GCC_QUPV3_WRAP0_S6_CLK 68
> +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69
> +#define GCC_QUPV3_WRAP0_S7_CLK 70
> +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71
> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72
> +#define GCC_QUPV3_WRAP1_CORE_CLK 73
> +#define GCC_QUPV3_WRAP1_S0_CLK 74
> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75
> +#define GCC_QUPV3_WRAP1_S1_CLK 76
> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77
> +#define GCC_QUPV3_WRAP1_S2_CLK 78
> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79
> +#define GCC_QUPV3_WRAP1_S3_CLK 80
> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81
> +#define GCC_QUPV3_WRAP1_S4_CLK 82
> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83
> +#define GCC_QUPV3_WRAP1_S5_CLK 84
> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85
> +#define GCC_QUPV3_WRAP1_S6_CLK 86
> +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87
> +#define GCC_QUPV3_WRAP1_S7_CLK 88
> +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89
> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90
> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91
> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92
> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93
> +#define GCC_SDCC5_AHB_CLK 94
> +#define GCC_SDCC5_APPS_CLK 95
> +#define GCC_SDCC5_APPS_CLK_SRC 96
> +#define GCC_SDCC5_ICE_CORE_CLK 97
> +#define GCC_SDCC5_ICE_CORE_CLK_SRC 98
> +#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99
> +#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100
> +#define GCC_SNOC_CNOC_PCIE_QX_CLK 101
> +#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102
> +#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103
> +#define GCC_TSC_CFG_AHB_CLK 104
> +#define GCC_TSC_CLK_SRC 105
> +#define GCC_TSC_CNTR_CLK 106
> +#define GCC_TSC_ETU_CLK 107
> +#define GCC_USB2_CLKREF_EN 108
> +#define GCC_USB30_PRIM_MASTER_CLK 109
> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
> +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113
> +#define GCC_USB30_PRIM_SLEEP_CLK 114
> +#define GCC_USB3_PRIM_PHY_AUX_CLK 115
> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
> +#define GCC_SM_BUS_AHB_CLK 119
> +#define GCC_SM_BUS_XO_CLK 120
> +#define GCC_SM_BUS_XO_CLK_SRC 121
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122
> +#define GCC_ETH_100G_C2C_HM_APB_CLK 123
> +#define GCC_ETH_100G_FH_HM_APB_0_CLK 124
> +#define GCC_ETH_100G_FH_HM_APB_1_CLK 125
> +#define GCC_ETH_100G_FH_HM_APB_2_CLK 126
> +#define GCC_ETH_DBG_C2C_HM_APB_CLK 127
> +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
> +#define GCC_PCIE_0_PIPE_CLK_SRC 129
> +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
> +
> +/* GCC resets */
> +#define GCC_ECPRI_CC_BCR 0
> +#define GCC_ECPRI_SS_BCR 1
> +#define GCC_ETH_WRAPPER_BCR 2
> +#define GCC_PCIE_0_BCR 3
> +#define GCC_PCIE_0_LINK_DOWN_BCR 4
> +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
> +#define GCC_PCIE_0_PHY_BCR 6
> +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
> +#define GCC_PCIE_PHY_CFG_AHB_BCR 8
> +#define GCC_PCIE_PHY_COM_BCR 9
> +#define GCC_PDM_BCR 10
> +#define GCC_QUPV3_WRAPPER_0_BCR 11
> +#define GCC_QUPV3_WRAPPER_1_BCR 12
> +#define GCC_QUSB2PHY_PRIM_BCR 13
> +#define GCC_QUSB2PHY_SEC_BCR 14
> +#define GCC_SDCC5_BCR 15
> +#define GCC_TCSR_PCIE_BCR 16
> +#define GCC_TSC_BCR 17
> +#define GCC_USB30_PRIM_BCR 18
> +#define GCC_USB3_DP_PHY_PRIM_BCR 19
> +#define GCC_USB3_DP_PHY_SEC_BCR 20
> +#define GCC_USB3_PHY_PRIM_BCR 21
> +#define GCC_USB3_PHY_SEC_BCR 22
> +#define GCC_USB3PHY_PHY_PRIM_BCR 23
> +#define GCC_USB3PHY_PHY_SEC_BCR 24
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25
> +
> +#endif
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support
2022-10-26 19:04 ` [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support Melody Olvera
@ 2022-11-07 17:32 ` Bjorn Andersson
2022-11-07 23:19 ` Melody Olvera
0 siblings, 1 reply; 27+ messages in thread
From: Bjorn Andersson @ 2022-11-07 17:32 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On Wed, Oct 26, 2022 at 12:04:39PM -0700, Melody Olvera wrote:
> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
> new file mode 100644
> index 000000000000..7bd8ebf0ddb5
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-qdu1000.c
> @@ -0,0 +1,2645 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "reset.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_GCC_GPLL0_OUT_EVEN,
> + P_GCC_GPLL0_OUT_MAIN,
> + P_GCC_GPLL1_OUT_MAIN,
> + P_GCC_GPLL2_OUT_MAIN,
> + P_GCC_GPLL3_OUT_MAIN,
> + P_GCC_GPLL4_OUT_MAIN,
> + P_GCC_GPLL5_OUT_MAIN,
> + P_GCC_GPLL6_OUT_MAIN,
> + P_GCC_GPLL7_OUT_MAIN,
> + P_GCC_GPLL8_OUT_MAIN,
> + P_PCIE_0_PHY_AUX_CLK,
> + P_PCIE_0_PIPE_CLK,
> + P_SLEEP_CLK,
> + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
> +};
[..]
> +static const struct clk_parent_data gcc_parent_data_1[] = {
> + { .index = P_BI_TCXO },
> + { .hw = &gcc_gpll0.clkr.hw },
> + { .index = P_SLEEP_CLK },
.index here refers to the index in the clocks property in DT.
I think it's okay to reuse the parent-enum, but the entries within must
then match the order defined in the DT binding. So you need to ensure
that the first N entires in the enum matches the binding.
Perhaps it's cleaner to just carry a separate enum for the clocks order,
as we've done in the other drivers?
If nothing else it makes it clear that one number space is arbitrary and
internal to the driver and the other is ABI.
> + { .hw = &gcc_gpll0_out_even.clkr.hw },
> +};
> +
[..]
> +static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
> + .reg = 0x9d080,
> + .shift = 0,
> + .width = 2,
> + .parent_map = gcc_parent_map_6,
> + .clkr = {
> + .hw.init = &(const struct clk_init_data){
Sorry for being picky, but I do like when there's a space between the
')' and '{' in these lines...
> + .name = "gcc_pcie_0_phy_aux_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_regmap_mux_closest_ops,
> + },
> + },
> +};
Regards,
Bjorn
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
2022-10-26 19:04 ` [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 Melody Olvera
2022-10-27 15:57 ` Krzysztof Kozlowski
@ 2022-11-07 17:36 ` Bjorn Andersson
1 sibling, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2022-11-07 17:36 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On Wed, Oct 26, 2022 at 12:04:38PM -0700, Melody Olvera wrote:
> Add compatible strings for RPMHCC for QDU1000 and QRU1000.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
This is independent of the GCC binding/driver, so I fixed up the
$subject per Krzysztof's feedback and picked the two patches.
But like the PDC, it's better to post independent things separately.
Thanks,
Bjorn
> ---
> Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
> index 437a34b930e3..fccb91e78e49 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
> @@ -17,6 +17,7 @@ description: |
> properties:
> compatible:
> enum:
> + - qcom,qdu1000-rpmh-clk
> - qcom,sc7180-rpmh-clk
> - qcom,sc7280-rpmh-clk
> - qcom,sc8180x-rpmh-clk
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings
2022-11-07 17:25 ` Bjorn Andersson
@ 2022-11-07 23:03 ` Melody Olvera
0 siblings, 0 replies; 27+ messages in thread
From: Melody Olvera @ 2022-11-07 23:03 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On 11/7/2022 9:25 AM, Bjorn Andersson wrote:
> On Wed, Oct 26, 2022 at 12:04:37PM -0700, Melody Olvera wrote:
>> Add device tree bindings for global clock controller on QDU1000 and
>> QRU1000 SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> .../bindings/clock/qcom,gcc-qdu1000.yaml | 77 ++++++++
>> include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++++++++++++++++++
>> 2 files changed, 247 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
>> new file mode 100644
>> index 000000000000..ad460d628ffc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
>> +
>> +allOf:
>> + - $ref: qcom,gcc.yaml#
>> +
>> +maintainers:
>> + - Melody Olvera <quic_molvera@quicinc.com>
>> +
>> +description: |
>> + Qualcomm global clock control module which supports the clocks, resets and
>> + power domains on QDU1000 and QRU1000
>> +
>> + See also:
>> + - include/dt-bindings/clock/qcom,gcc-qdu1000.h
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,gcc-qdu1000
>> + - const: syscon
>> +
>> + clocks:
>> + items:
>> + - description: Board XO source
>> + - description: Sleep clock source
>> + - description: PCIE 0 Pipe clock source
>> + - description: PCIE 0 Phy Auxiliary clock source
>> + - description: USB3 Phy wrapper pipe clock source
>> + minItems: 2
> They should all be required by the binding, but I will accept .dts
> files with not yet available sources specified as <0>.
Yeah I'll add these clocks.
>
>> +
>> + clock-names:
> Including clock-names in the binding indicates that clocks are indexed
> based on these names (which is what we've done for many years now).
>
> As we're transitioning the clock providers to rely solely on the
> ordering of clocks, I prefer that we omit the clock-names property, just
> to make it clear that clock-names is effectively ignored by Linux.
Sounds good.
>
>> + items:
>> + - const: bi_tcxo
>> + - const: sleep_clk
>> + - const: pcie_0_pipe_clk
>> + minItems: 2
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + '#reset-cells':
>> + const: 1
>> +
>> + '#power-domain-cells':
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - '#clock-cells'
>> + - '#reset-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> + clock-controller@100000 {
>> + compatible = "qcom,gcc-qdu1000", "syscon";
>> + reg = <0x00100000 0x001f4200>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
> This is just an example, so please make up some plausible sources for
> the remaining clocks.
Yeah the remaining clocks can go under this source as well.
Thanks,
Melody
>> + clock-names = "bi_tcxo", "sleep_clk";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> diff --git a/include/dt-bindings/clock/qcom,gcc-qdu1000.h b/include/dt-bindings/clock/qcom,gcc-qdu1000.h
>> new file mode 100644
>> index 000000000000..99edb688fef2
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gcc-qdu1000.h
>> @@ -0,0 +1,170 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>> +/*
>> + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
>> +#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
>> +
>> +/* GCC clocks */
>> +#define GCC_GPLL0 0
>> +#define GCC_GPLL0_OUT_EVEN 1
>> +#define GCC_GPLL1 2
>> +#define GCC_GPLL2 3
>> +#define GCC_GPLL2_OUT_EVEN 4
>> +#define GCC_GPLL3 5
>> +#define GCC_GPLL4 6
>> +#define GCC_GPLL5 7
>> +#define GCC_GPLL5_OUT_EVEN 8
>> +#define GCC_GPLL6 9
>> +#define GCC_GPLL7 10
>> +#define GCC_GPLL8 11
>> +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12
>> +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13
>> +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14
>> +#define GCC_BOOT_ROM_AHB_CLK 15
>> +#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16
>> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
>> +#define GCC_DDRSS_ECPRI_DMA_CLK 18
>> +#define GCC_ECPRI_AHB_CLK 19
>> +#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20
>> +#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21
>> +#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22
>> +#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23
>> +#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24
>> +#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25
>> +#define GCC_ECPRI_XO_CLK 26
>> +#define GCC_ETH_DBG_SNOC_AXI_CLK 27
>> +#define GCC_GEMNOC_PCIE_QX_CLK 28
>> +#define GCC_GP1_CLK 29
>> +#define GCC_GP1_CLK_SRC 30
>> +#define GCC_GP2_CLK 31
>> +#define GCC_GP2_CLK_SRC 32
>> +#define GCC_GP3_CLK 33
>> +#define GCC_GP3_CLK_SRC 34
>> +#define GCC_PCIE_0_AUX_CLK 35
>> +#define GCC_PCIE_0_AUX_CLK_SRC 36
>> +#define GCC_PCIE_0_CFG_AHB_CLK 37
>> +#define GCC_PCIE_0_CLKREF_EN 38
>> +#define GCC_PCIE_0_MSTR_AXI_CLK 39
>> +#define GCC_PCIE_0_PHY_AUX_CLK 40
>> +#define GCC_PCIE_0_PHY_RCHNG_CLK 41
>> +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
>> +#define GCC_PCIE_0_PIPE_CLK 43
>> +#define GCC_PCIE_0_SLV_AXI_CLK 44
>> +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
>> +#define GCC_PDM2_CLK 46
>> +#define GCC_PDM2_CLK_SRC 47
>> +#define GCC_PDM_AHB_CLK 48
>> +#define GCC_PDM_XO4_CLK 49
>> +#define GCC_QMIP_ANOC_PCIE_CLK 50
>> +#define GCC_QMIP_ECPRI_DMA0_CLK 51
>> +#define GCC_QMIP_ECPRI_DMA1_CLK 52
>> +#define GCC_QMIP_ECPRI_GSI_CLK 53
>> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54
>> +#define GCC_QUPV3_WRAP0_CORE_CLK 55
>> +#define GCC_QUPV3_WRAP0_S0_CLK 56
>> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57
>> +#define GCC_QUPV3_WRAP0_S1_CLK 58
>> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59
>> +#define GCC_QUPV3_WRAP0_S2_CLK 60
>> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61
>> +#define GCC_QUPV3_WRAP0_S3_CLK 62
>> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63
>> +#define GCC_QUPV3_WRAP0_S4_CLK 64
>> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65
>> +#define GCC_QUPV3_WRAP0_S5_CLK 66
>> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67
>> +#define GCC_QUPV3_WRAP0_S6_CLK 68
>> +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69
>> +#define GCC_QUPV3_WRAP0_S7_CLK 70
>> +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71
>> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72
>> +#define GCC_QUPV3_WRAP1_CORE_CLK 73
>> +#define GCC_QUPV3_WRAP1_S0_CLK 74
>> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75
>> +#define GCC_QUPV3_WRAP1_S1_CLK 76
>> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77
>> +#define GCC_QUPV3_WRAP1_S2_CLK 78
>> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79
>> +#define GCC_QUPV3_WRAP1_S3_CLK 80
>> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81
>> +#define GCC_QUPV3_WRAP1_S4_CLK 82
>> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83
>> +#define GCC_QUPV3_WRAP1_S5_CLK 84
>> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85
>> +#define GCC_QUPV3_WRAP1_S6_CLK 86
>> +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87
>> +#define GCC_QUPV3_WRAP1_S7_CLK 88
>> +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89
>> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90
>> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91
>> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92
>> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93
>> +#define GCC_SDCC5_AHB_CLK 94
>> +#define GCC_SDCC5_APPS_CLK 95
>> +#define GCC_SDCC5_APPS_CLK_SRC 96
>> +#define GCC_SDCC5_ICE_CORE_CLK 97
>> +#define GCC_SDCC5_ICE_CORE_CLK_SRC 98
>> +#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99
>> +#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100
>> +#define GCC_SNOC_CNOC_PCIE_QX_CLK 101
>> +#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102
>> +#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103
>> +#define GCC_TSC_CFG_AHB_CLK 104
>> +#define GCC_TSC_CLK_SRC 105
>> +#define GCC_TSC_CNTR_CLK 106
>> +#define GCC_TSC_ETU_CLK 107
>> +#define GCC_USB2_CLKREF_EN 108
>> +#define GCC_USB30_PRIM_MASTER_CLK 109
>> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
>> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
>> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
>> +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113
>> +#define GCC_USB30_PRIM_SLEEP_CLK 114
>> +#define GCC_USB3_PRIM_PHY_AUX_CLK 115
>> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
>> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
>> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
>> +#define GCC_SM_BUS_AHB_CLK 119
>> +#define GCC_SM_BUS_XO_CLK 120
>> +#define GCC_SM_BUS_XO_CLK_SRC 121
>> +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122
>> +#define GCC_ETH_100G_C2C_HM_APB_CLK 123
>> +#define GCC_ETH_100G_FH_HM_APB_0_CLK 124
>> +#define GCC_ETH_100G_FH_HM_APB_1_CLK 125
>> +#define GCC_ETH_100G_FH_HM_APB_2_CLK 126
>> +#define GCC_ETH_DBG_C2C_HM_APB_CLK 127
>> +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
>> +#define GCC_PCIE_0_PIPE_CLK_SRC 129
>> +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
>> +
>> +/* GCC resets */
>> +#define GCC_ECPRI_CC_BCR 0
>> +#define GCC_ECPRI_SS_BCR 1
>> +#define GCC_ETH_WRAPPER_BCR 2
>> +#define GCC_PCIE_0_BCR 3
>> +#define GCC_PCIE_0_LINK_DOWN_BCR 4
>> +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
>> +#define GCC_PCIE_0_PHY_BCR 6
>> +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
>> +#define GCC_PCIE_PHY_CFG_AHB_BCR 8
>> +#define GCC_PCIE_PHY_COM_BCR 9
>> +#define GCC_PDM_BCR 10
>> +#define GCC_QUPV3_WRAPPER_0_BCR 11
>> +#define GCC_QUPV3_WRAPPER_1_BCR 12
>> +#define GCC_QUSB2PHY_PRIM_BCR 13
>> +#define GCC_QUSB2PHY_SEC_BCR 14
>> +#define GCC_SDCC5_BCR 15
>> +#define GCC_TCSR_PCIE_BCR 16
>> +#define GCC_TSC_BCR 17
>> +#define GCC_USB30_PRIM_BCR 18
>> +#define GCC_USB3_DP_PHY_PRIM_BCR 19
>> +#define GCC_USB3_DP_PHY_SEC_BCR 20
>> +#define GCC_USB3_PHY_PRIM_BCR 21
>> +#define GCC_USB3_PHY_SEC_BCR 22
>> +#define GCC_USB3PHY_PHY_PRIM_BCR 23
>> +#define GCC_USB3PHY_PHY_SEC_BCR 24
>> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25
>> +
>> +#endif
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support
2022-11-07 17:32 ` Bjorn Andersson
@ 2022-11-07 23:19 ` Melody Olvera
0 siblings, 0 replies; 27+ messages in thread
From: Melody Olvera @ 2022-11-07 23:19 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Thomas Gleixner, Marc Zyngier, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On 11/7/2022 9:32 AM, Bjorn Andersson wrote:
> On Wed, Oct 26, 2022 at 12:04:39PM -0700, Melody Olvera wrote:
>> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
>> new file mode 100644
>> index 000000000000..7bd8ebf0ddb5
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-qdu1000.c
>> @@ -0,0 +1,2645 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h>
>> +
>> +#include "clk-alpha-pll.h"
>> +#include "clk-branch.h"
>> +#include "clk-rcg.h"
>> +#include "clk-regmap.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "clk-regmap-phy-mux.h"
>> +#include "reset.h"
>> +
>> +enum {
>> + P_BI_TCXO,
>> + P_GCC_GPLL0_OUT_EVEN,
>> + P_GCC_GPLL0_OUT_MAIN,
>> + P_GCC_GPLL1_OUT_MAIN,
>> + P_GCC_GPLL2_OUT_MAIN,
>> + P_GCC_GPLL3_OUT_MAIN,
>> + P_GCC_GPLL4_OUT_MAIN,
>> + P_GCC_GPLL5_OUT_MAIN,
>> + P_GCC_GPLL6_OUT_MAIN,
>> + P_GCC_GPLL7_OUT_MAIN,
>> + P_GCC_GPLL8_OUT_MAIN,
>> + P_PCIE_0_PHY_AUX_CLK,
>> + P_PCIE_0_PIPE_CLK,
>> + P_SLEEP_CLK,
>> + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
>> +};
> [..]
>> +static const struct clk_parent_data gcc_parent_data_1[] = {
>> + { .index = P_BI_TCXO },
>> + { .hw = &gcc_gpll0.clkr.hw },
>> + { .index = P_SLEEP_CLK },
> .index here refers to the index in the clocks property in DT.
>
> I think it's okay to reuse the parent-enum, but the entries within must
> then match the order defined in the DT binding. So you need to ensure
> that the first N entires in the enum matches the binding.
>
> Perhaps it's cleaner to just carry a separate enum for the clocks order,
> as we've done in the other drivers?
>
> If nothing else it makes it clear that one number space is arbitrary and
> internal to the driver and the other is ABI.
Yeah that makes plenty of sense. Will update the driver with a separate enum.
>
>> + { .hw = &gcc_gpll0_out_even.clkr.hw },
>> +};
>> +
> [..]
>> +static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
>> + .reg = 0x9d080,
>> + .shift = 0,
>> + .width = 2,
>> + .parent_map = gcc_parent_map_6,
>> + .clkr = {
>> + .hw.init = &(const struct clk_init_data){
> Sorry for being picky, but I do like when there's a space between the
> ')' and '{' in these lines...
No worries. Will fix.
>
>> + .name = "gcc_pcie_0_phy_aux_clk_src",
>> + .parent_data = gcc_parent_data_6,
>> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
>> + .ops = &clk_regmap_mux_closest_ops,
>> + },
>> + },
>> +};
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000
2022-11-07 17:16 ` Bjorn Andersson
@ 2022-11-07 23:20 ` Melody Olvera
0 siblings, 0 replies; 27+ messages in thread
From: Melody Olvera @ 2022-11-07 23:20 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Stephen Boyd, Andy Gross, Krzysztof Kozlowski, Marc Zyngier,
Michael Turquette, Rob Herring, Thomas Gleixner, Taniya Das,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On 11/7/2022 9:16 AM, Bjorn Andersson wrote:
> On Thu, Oct 27, 2022 at 02:31:08PM -0700, Melody Olvera wrote:
>>
>> On 10/27/2022 11:22 AM, Stephen Boyd wrote:
>>> Quoting Melody Olvera (2022-10-26 12:04:41)
>>>> Add compatible fields for QDU1000 and QRU1000 pdcs.
>>>>
>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>>>> ---
>>> Is there a reason why this patch continues to be included in what is
>>> otherwise a clk driver patch series? Can this patch be sent separately
>>> from the clk patches (and not Cced to clk maintainers/list) in the
>>> future?
>> Sure thing. On reflection, this belongs with the misc support patches.
>>
> Even better, the "misc" series goes through my tree but this patch is
> unrelated. So if you send it on it's own it could just be picked up by
> the PDC maintainer (or Rob).
>
>
Sure thing. I'll just send each on their own.
Thanks,
Melody
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: (subset) [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
` (4 preceding siblings ...)
2022-10-26 19:04 ` [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 Melody Olvera
@ 2022-11-08 1:27 ` Bjorn Andersson
5 siblings, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2022-11-08 1:27 UTC (permalink / raw)
To: quic_molvera, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt,
agross, maz, tglx
Cc: devicetree, linux-clk, quic_tdas, linux-kernel, linux-arm-msm
On Wed, 26 Oct 2022 12:04:36 -0700, Melody Olvera wrote:
> This series adds the GCC, RPMh, and PDC clock support required for the
> QDU1000 and QRU1000 SoCs along with the devicetree bindings for them.
>
> The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
> 1000 are new SoCs meant for enabling Open RAN solutions. See more at
> https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
>
> [...]
Applied, thanks!
[2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000
commit: 70d9f589918aaadd6d5547ecb27355b7b69fc32c
[4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks
commit: 05e5c125b120c75b9313af0a6dc8c4f5a71e8e7c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2022-11-08 1:29 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-26 19:04 [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Melody Olvera
2022-10-26 19:04 ` [PATCH v3 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Melody Olvera
2022-10-27 15:54 ` Krzysztof Kozlowski
2022-10-27 18:24 ` Stephen Boyd
2022-10-27 19:35 ` Krzysztof Kozlowski
2022-10-27 21:28 ` Melody Olvera
2022-10-27 21:59 ` Krzysztof Kozlowski
2022-11-07 17:25 ` Bjorn Andersson
2022-11-07 23:03 ` Melody Olvera
2022-10-26 19:04 ` [PATCH v3 2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 Melody Olvera
2022-10-27 15:57 ` Krzysztof Kozlowski
2022-10-28 1:04 ` Melody Olvera
2022-10-28 1:09 ` Krzysztof Kozlowski
2022-10-28 16:54 ` Melody Olvera
2022-11-07 17:36 ` Bjorn Andersson
2022-10-26 19:04 ` [PATCH v3 3/5] clk: qcom: Add QDU1000 and QRU1000 GCC support Melody Olvera
2022-11-07 17:32 ` Bjorn Andersson
2022-11-07 23:19 ` Melody Olvera
2022-10-26 19:04 ` [PATCH v3 4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks Melody Olvera
2022-10-26 19:04 ` [PATCH v3 5/5] dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 Melody Olvera
2022-10-27 15:58 ` Krzysztof Kozlowski
2022-10-27 18:22 ` Stephen Boyd
2022-10-27 21:31 ` Melody Olvera
2022-10-27 21:38 ` Stephen Boyd
2022-11-07 17:16 ` Bjorn Andersson
2022-11-07 23:20 ` Melody Olvera
2022-11-08 1:27 ` (subset) [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Bjorn Andersson
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