* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
[not found] ` <82cc5e6900138e13ed9d75c6d2a42c6d7afc1959.camel@mediatek.com>
@ 2022-04-22 2:32 ` Jason-JH Lin
2022-04-22 12:31 ` Matthias Brugger
0 siblings, 1 reply; 14+ messages in thread
From: Jason-JH Lin @ 2022-04-22 2:32 UTC (permalink / raw)
To: CK Hu, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Fei Shao <fshao@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 87
> > ++++++++++++++++++++++++++++++--
> > 1 file changed, 84 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..729ee88035ed 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> > #define MT8183_MUTEX0_MOD0 0x30
> > #define MT8183_MUTEX0_SOF0 0x2c
> >
> > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > +#define MT8195_DISP_MUTEX0_SOF 0x2c
>
> This is identical to mt8183, so use mt8183 one instead of creating
> new
> one.
>
> Regards,
> CK
>
I'll fix this in the next version.
Regards,
Jason-JH.Lin.
> >
> >
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > + .mutex_mod = mt8195_mutex_mod,
> > + .mutex_sof = mt8195_mutex_sof,
> > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> >
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
[not found] ` <20220419094143.9561-2-jason-jh.lin@mediatek.com>
@ 2022-04-22 12:28 ` Matthias Brugger
2022-04-24 8:47 ` Jason-JH Lin
0 siblings, 1 reply; 14+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:28 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
I'm not very happy with the approach of testing against the reg property to
decide which version of the two mmsys devices we are probing. I think a better
approach would be, if we would have added some mediatek specific ID to the
device tree binding (or use a two compatibles?).
But as we are at v20 I think it wouldn't be fair to ask for such an instrusive
change. So I'll take this patch now, but maybe we can discuss if we can't do
better in a follow-up patch. Especially I don't think it's a good approach to
check for the io_start in the DRM driver. Couldn't we pass the information about
which of the two mmsys blocks we are calling from through the mediatek-drm
platform device spefic data?
I also had a look into the vdosys1 series to better understand why we need to do
things as we do them. But honestly I wasn't able to really understand the
implication of the patch that adds 'multi mmsys support' [1]. For this looks
like a several patches that got squashed into one. But as I don't have to
maintain that it is not my call to complain, the patch has the needed reviews.
For this patch, now applied to v5.18-next/soc
Thanks for all people implicated.
Regards,
Matthias
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> - https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..13ab0ab64396
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,370 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSI1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..548efed8dc1c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -17,6 +17,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .clk_driver = "clk-mt2712-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> .clk_driver = "clk-mt6779-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6779_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> .clk_driver = "clk-mt6797-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6797_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> .clk_driver = "clk-mt8167-mm",
> .routes = mt8167_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .clk_driver = "clk-mt8186-mm",
> .routes = mmsys_mt8186_routing_table,
> @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8186_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .io_start = 0x1c01a000,
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .io_start = 0x1c100000,
> + .clk_driver = "clk-mt8195-vdo1",
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 2,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8365_mmsys_driver_data,
> + },
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + phys_addr_t io_start;
> };
>
> +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> + const struct mtk_mmsys_match_data *match)
> +{
> + int i;
> +
> + for (i = 0; i < match->num_drv_data; i++)
> + if (mmsys->io_start == match->drv_data[i]->io_start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct platform_device *clks;
> struct platform_device *drm;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_mmsys *mmsys;
> + struct resource *res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - mmsys->data = of_device_get_match_data(&pdev->dev);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Couldn't get mmsys resource\n");
> + return -EINVAL;
> + }
> + mmsys->io_start = res->start;
> +
> + match_data = of_device_get_match_data(dev);
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return ret;
> + }
> + mmsys->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + mmsys->data = match_data->drv_data[0];
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> static const struct of_device_id of_match_mtk_mmsys[] = {
> {
> .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> + .data = &mt2701_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> + .data = &mt2712_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> + .data = &mt6779_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> + .data = &mt6797_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data,
> + .data = &mt8167_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> + .data = &mt8173_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> + .data = &mt8183_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8186-mmsys",
> - .data = &mt8186_mmsys_driver_data,
> + .data = &mt8186_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data,
> + .data = &mt8192_mmsys_match_data,
> + },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8365-mmsys",
> - .data = &mt8365_mmsys_driver_data,
> + .data = &mt8365_mmsys_match_data,
> },
> { }
> };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 77f37f8c715b..f01ba206481d 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> };
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> /*
> * Routes in mt8173, mt2701, mt2712 are different. That means
> * in the same register address, it controls different input/output
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..cff5c9adbf46 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
[not found] ` <20220419094143.9561-3-jason-jh.lin@mediatek.com>
[not found] ` <82cc5e6900138e13ed9d75c6d2a42c6d7afc1959.camel@mediatek.com>
@ 2022-04-22 12:29 ` Matthias Brugger
1 sibling, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:29 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
Applied thanks!
Matthias
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -96,6 +99,20 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -132,9 +149,21 @@
> #define MT8167_MUTEX_SOF_DPI1 3
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
>
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
> +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
>
> struct mtk_mutex {
> int id;
> @@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> @@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> };
>
> +/*
> + * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
> + * select the EOF source and configure the EOF plus timing from the
> + * module that provides the timing signal.
> + * So that MUTEX can not only send a STREAM_DONE event to GCE
> + * but also detect the error at end of frame(EAEOF) when EOF signal
> + * arrives.
> + */
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DPI1:
> sof_id = MUTEX_SOF_DPI1;
> break;
> + case DDP_COMPONENT_DP_INTF0:
> + sof_id = MUTEX_SOF_DP_INTF0;
> + break;
> default:
> if (mtx->data->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> @@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DSI3:
> case DDP_COMPONENT_DPI0:
> case DDP_COMPONENT_DPI1:
> + case DDP_COMPONENT_DP_INTF0:
> writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> mtx->regs +
> DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
> @@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-22 2:32 ` [PATCH v20 2/8] soc: mediatek: add mtk-mutex " Jason-JH Lin
@ 2022-04-22 12:31 ` Matthias Brugger
2022-04-24 8:48 ` Jason-JH Lin
0 siblings, 1 reply; 14+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:31 UTC (permalink / raw)
To: Jason-JH Lin, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 22/04/2022 04:32, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
>> Hi, Jason:
>>
>> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
>>> Add mtk-mutex support for mt8195 vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Acked-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>> Tested-by: Fei Shao <fshao@chromium.org>
>>> ---
>>> drivers/soc/mediatek/mtk-mutex.c | 87
>>> ++++++++++++++++++++++++++++++--
>>> 1 file changed, 84 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index aaf8fc1abb43..729ee88035ed 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -17,6 +17,9 @@
>>> #define MT8183_MUTEX0_MOD0 0x30
>>> #define MT8183_MUTEX0_SOF0 0x2c
>>>
>>> +#define MT8195_DISP_MUTEX0_MOD0 0x30
>>> +#define MT8195_DISP_MUTEX0_SOF 0x2c
>>
>> This is identical to mt8183, so use mt8183 one instead of creating
>> new
>> one.
>>
>> Regards,
>> CK
>>
> I'll fix this in the next version.
Please send this as a follow-up fix on top of:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next/soc
Regards,
Matthias
>
> Regards,
> Jason-JH.Lin.
>>>
>>>
>>> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
>>> + .mutex_mod = mt8195_mutex_mod,
>>> + .mutex_sof = mt8195_mutex_sof,
>>> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
>>> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
>>> +};
>>> +
>>>
>>
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
[not found] ` <20220419094143.9561-7-jason-jh.lin@mediatek.com>
@ 2022-04-22 12:32 ` Matthias Brugger
0 siblings, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:32 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Applied, thanks!
> ---
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
> drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
> drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 8 files changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index 2772ef5e3934..f7a35b3656bb 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
> @@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
> MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
> }, {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 0c021f4b76d2..ff6be1703469 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
> MT8183_OVL1_2L_MOUT_EN_RDMA1
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
> MT8183_DITHER0_MOUT_IN_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> index c72ccf86ea28..eb1ad9c37a9c 100644
> --- a/drivers/soc/mediatek/mt8186-mmsys.h
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> MT8186_RDMA0_SOUT_TO_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> MT8186_DITHER0_MOUT_TO_DSI0,
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> MT8186_DSI0_FROM_DITHER0
> },
> diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
> index 6aae0b12b6ff..a016d80b4bc1 100644
> --- a/drivers/soc/mediatek/mt8192-mmsys.h
> +++ b/drivers/soc/mediatek/mt8192-mmsys.h
> @@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
> MT8192_OVL2_2L_MOUT_EN_RDMA4
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
> MT8192_DITHER0_MOUT_IN_DSI0
> }, {
> @@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> MT8192_AAL0_SEL_IN_CCORR0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> MT8192_DSI0_SEL_IN_DITHER0
> }, {
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 13ab0ab64396..abfe94a30248 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> }, {
> @@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> }, {
> @@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
> index 690e3fe2dee0..24129a6c25f8 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
> MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
> },
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 729ee88035ed..9184684baf1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
> [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> @@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> @@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> @@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> @@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> - [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index cff5c9adbf46..59117d970daf 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
[not found] ` <20220419094143.9561-9-jason-jh.lin@mediatek.com>
@ 2022-04-22 12:42 ` Matthias Brugger
2022-05-01 22:54 ` Chun-Kuang Hu
0 siblings, 1 reply; 14+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:42 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Chun-Kuang, I think it would make sense to take that through your tree as it
depends on the previous patches.
I provide you a stable tag so that you can take it:
v5.18-next-vdso0-stable-tag
Regards,
Matthias
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 59117d970daf..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-22 12:28 ` [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Matthias Brugger
@ 2022-04-24 8:47 ` Jason-JH Lin
0 siblings, 0 replies; 14+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:47 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:28 +0200, Matthias Brugger wrote:
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for 2 vdosys.
> > 2. Add io_start into each driver data of mt8195 vdosys.
> > 3. Add get match data function to identify mmsys by io_start.
> > 4. Add mt8195 routing table settings of vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
>
> I'm not very happy with the approach of testing against the reg
> property to
> decide which version of the two mmsys devices we are probing. I think
> a better
> approach would be, if we would have added some mediatek specific ID
> to the
> device tree binding (or use a two compatibles?).
>
We uses two compatibles in previous version(before v16) of this series.
https://patchwork.kernel.org/project/linux-mediatek/patch/20220307032859.3275-5-jason-jh.lin@mediatek.com/
Since we received the comment of VPPSYS from Rob:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220117055254.9777-15-roy-cw.yeh@mediatek.com/#24707362
we're trying to figure out the way to use the same compatible for
different mmsys.
> But as we are at v20 I think it wouldn't be fair to ask for such an
> instrusive
> change. So I'll take this patch now, but maybe we can discuss if we
> can't do
> better in a follow-up patch. Especially I don't think it's a good
> approach to
> check for the io_start in the DRM driver. Couldn't we pass the
> information about
> which of the two mmsys blocks we are calling from through the
> mediatek-drm
> platform device spefic data?
>
But we can't find a suitable property to identify the different mmsys
directly.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domain.
Since each mmsys has its own clock, I have tried to differentiate
vdosys0, vdosys1 by the clock names:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/
But it seems not robust enough.
Then we refer to this io_start solution, the idea from Angelo:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
I'm not sure if there is another more suitable idea to fit in this
problem.
But I believe, if using different compatibles for each mmsys is
acceptable, then we can keep the original compatible method for
mediatek-drm and mmsys, and also make these works easier.
If you have any ideas to simplify it, please help us :-)
Thanks for your reviews again.
Regards,
Jason-JH.Lin
> I also had a look into the vdosys1 series to better understand why we
> need to do
> things as we do them. But honestly I wasn't able to really understand
> the
> implication of the patch that adds 'multi mmsys support' [1]. For
> this looks
> like a several patches that got squashed into one. But as I don't
> have to
> maintain that it is not my call to complain, the patch has the needed
> reviews.
>
> For this patch, now applied to v5.18-next/soc
>
> Thanks for all people implicated.
>
> Regards,
> Matthias
>
> [1]
>
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRVLWEf_p$
>
>
> > ---
> > Based on series [1]
> >
> > [1] MediaTek MT8195 display binding
> > -
> > https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRXN1cxii$
> >
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> > drivers/soc/mediatek/mtk-mmsys.h | 6 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> > 4 files changed, 528 insertions(+), 11 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..13ab0ab64396
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,370 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN 0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK
> > (1, 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK
> > GENMASK(4, 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK
> > GENMASK(5, 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK
> > GENMASK(8, 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK
> > GENMASK(9, 9)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_MASK
> > GENMASK(16, 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_MASK
> > GENMASK(17, 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK
> > (20, 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK
> > (21, 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK
> > (22, 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > (0 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK
> > (2, 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK
> > (4, 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_MASK
> > GENMASK(10, 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK
> > (11, 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > (0 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK
> > (17, 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > + {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > + }
> > +};
> > +
> > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..548efed8dc1c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -17,6 +17,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2701_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt2712_mmsys_driver_data = {
> > .clk_driver = "clk-mt2712-mm",
> > .routes = mmsys_default_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2712_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6779_mmsys_driver_data = {
> > .clk_driver = "clk-mt6779-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6779_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6797_mmsys_driver_data = {
> > .clk_driver = "clk-mt6797-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6797_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8167_mmsys_driver_data = {
> > .clk_driver = "clk-mt8167-mm",
> > .routes = mt8167_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8167_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .clk_driver = "clk-mt8173-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8173_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8183_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .clk_driver = "clk-mt8186-mm",
> > .routes = mmsys_mt8186_routing_table,
> > @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8186_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .clk_driver = "clk-mt8192-mm",
> > .routes = mmsys_mt8192_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8192_mmsys_driver_data,
> > + },
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .io_start = 0x1c01a000,
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .io_start = 0x1c100000,
> > + .clk_driver = "clk-mt8195-vdo1",
> > +};
> > +
> > +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > + .num_drv_data = 2,
> > + .drv_data = {
> > + &mt8195_vdosys0_driver_data,
> > + &mt8195_vdosys1_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8365_mmsys_driver_data,
> > + },
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + phys_addr_t io_start;
> > };
> >
> > +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > + const struct
> > mtk_mmsys_match_data *match)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < match->num_drv_data; i++)
> > + if (mmsys->io_start == match->drv_data[i]->io_start)
> > + return i;
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct platform_device *clks;
> > struct platform_device *drm;
> > + const struct mtk_mmsys_match_data *match_data;
> > struct mtk_mmsys *mmsys;
> > + struct resource *res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > - mmsys->data = of_device_get_match_data(&pdev->dev);
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "Couldn't get mmsys resource\n");
> > + return -EINVAL;
> > + }
> > + mmsys->io_start = res->start;
> > +
> > + match_data = of_device_get_match_data(dev);
> > + if (match_data->num_drv_data > 1) {
> > + /* This SoC has multiple mmsys channels */
> > + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> > + if (ret < 0) {
> > + dev_err(dev, "Couldn't get match driver
> > data\n");
> > + return ret;
> > + }
> > + mmsys->data = match_data->drv_data[ret];
> > + } else {
> > + dev_dbg(dev, "Using single mmsys channel\n");
> > + mmsys->data = match_data->drv_data[0];
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > static const struct of_device_id of_match_mtk_mmsys[] = {
> > {
> > .compatible = "mediatek,mt2701-mmsys",
> > - .data = &mt2701_mmsys_driver_data,
> > + .data = &mt2701_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt2712-mmsys",
> > - .data = &mt2712_mmsys_driver_data,
> > + .data = &mt2712_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6779-mmsys",
> > - .data = &mt6779_mmsys_driver_data,
> > + .data = &mt6779_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6797-mmsys",
> > - .data = &mt6797_mmsys_driver_data,
> > + .data = &mt6797_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8167-mmsys",
> > - .data = &mt8167_mmsys_driver_data,
> > + .data = &mt8167_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8173-mmsys",
> > - .data = &mt8173_mmsys_driver_data,
> > + .data = &mt8173_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8183-mmsys",
> > - .data = &mt8183_mmsys_driver_data,
> > + .data = &mt8183_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8186-mmsys",
> > - .data = &mt8186_mmsys_driver_data,
> > + .data = &mt8186_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8192-mmsys",
> > - .data = &mt8192_mmsys_driver_data,
> > + .data = &mt8192_mmsys_match_data,
> > + },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + .data = &mt8195_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > - .data = &mt8365_mmsys_driver_data,
> > + .data = &mt8365_mmsys_match_data,
> > },
> > { }
> > };
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 77f37f8c715b..f01ba206481d 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> > };
> >
> > struct mtk_mmsys_driver_data {
> > + const resource_size_t io_start;
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > const u16 sw0_rst_offset;
> > };
> >
> > +struct mtk_mmsys_match_data {
> > + unsigned short num_drv_data;
> > + const struct mtk_mmsys_driver_data *drv_data[];
> > +};
> > +
> > /*
> > * Routes in mt8173, mt2701, mt2712 are different. That means
> > * in the same register address, it controls different
> > input/output
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..cff5c9adbf46 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
c--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-22 12:31 ` Matthias Brugger
@ 2022-04-24 8:48 ` Jason-JH Lin
0 siblings, 0 replies; 14+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:48 UTC (permalink / raw)
To: Matthias Brugger, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:31 +0200, Matthias Brugger wrote:
>
> On 22/04/2022 04:32, Jason-JH Lin wrote:
> > Hi CK,
> >
> > Thanks for the reviews.
> >
> > On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> > > Hi, Jason:
> > >
> > > On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > > > Add mtk-mutex support for mt8195 vdosys0.
> > > >
> > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > Acked-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Tested-by: Fei Shao <fshao@chromium.org>
> > > > ---
> > > > drivers/soc/mediatek/mtk-mutex.c | 87
> > > > ++++++++++++++++++++++++++++++--
> > > > 1 file changed, 84 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > > b/drivers/soc/mediatek/mtk-mutex.c
> > > > index aaf8fc1abb43..729ee88035ed 100644
> > > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > > @@ -17,6 +17,9 @@
> > > > #define MT8183_MUTEX0_MOD0 0x30
> > > > #define MT8183_MUTEX0_SOF0 0x2c
> > > >
> > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > > > +#define MT8195_DISP_MUTEX0_SOF 0x2c
> > >
> > > This is identical to mt8183, so use mt8183 one instead of
> > > creating
> > > new
> > > one.
> > >
> > > Regards,
> > > CK
> > >
> >
> > I'll fix this in the next version.
>
> Please send this as a follow-up fix on top of:
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next*soc__;Lw!!CTRNKA9wMg0ARbw!0QzNDaejnt54R86SL628fJ9p2BKTOmYBnoz6uPz9X8WsHXeQi3rqPAXmPFRBcw1vEtUu$
>
>
> Regards,
> Matthias
>
OK, I'll send the fix-up patch soon.
Regards,
Jason-JH.Lin
> >
> > Regards,
> > Jason-JH.Lin.
> > > >
> > > >
> > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data =
> > > > {
> > > > + .mutex_mod = mt8195_mutex_mod,
> > > > + .mutex_sof = mt8195_mutex_sof,
> > > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > > > +};
> > > > +
> > > >
> > >
> > >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-04-22 12:42 ` [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum Matthias Brugger
@ 2022-05-01 22:54 ` Chun-Kuang Hu
2022-05-13 7:42 ` Matthias Brugger
0 siblings, 1 reply; 14+ messages in thread
From: Chun-Kuang Hu @ 2022-05-01 22:54 UTC (permalink / raw)
To: Matthias Brugger
Cc: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>
>
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> > mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>
> Chun-Kuang, I think it would make sense to take that through your tree as it
> depends on the previous patches.
>
> I provide you a stable tag so that you can take it:
> v5.18-next-vdso0-stable-tag
After I take this tag, I find one checkpatch warning:
WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
un-documented -- check ./Documentation/devicetree/bindings/
#670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
+ .compatible = "mediatek,mt8195-mmsys",
I think this tag lost one binding patch, it's better that this tag has
no this warning.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > ---
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 59117d970daf..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
> > DDP_COMPONENT_DITHER1,
> > DDP_COMPONENT_DP_INTF0,
> > DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-05-01 22:54 ` Chun-Kuang Hu
@ 2022-05-13 7:42 ` Matthias Brugger
2022-05-14 22:45 ` Chun-Kuang Hu
0 siblings, 1 reply; 14+ messages in thread
From: Matthias Brugger @ 2022-05-13 7:42 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>
>>
>>
>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> Chun-Kuang, I think it would make sense to take that through your tree as it
>> depends on the previous patches.
>>
>> I provide you a stable tag so that you can take it:
>> v5.18-next-vdso0-stable-tag
>
> After I take this tag, I find one checkpatch warning:
>
> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> un-documented -- check ./Documentation/devicetree/bindings/
> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> + .compatible = "mediatek,mt8195-mmsys",
>
> I think this tag lost one binding patch, it's better that this tag has
> no this warning.
>
Sorry for the late reply I was sick.
The warning is, because the stable branch misses commit:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
So it's not a real issue and will go away once our branches land in upstream.
Is it OK for you to ignore the issue?
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> ---
>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 59117d970daf..fb719fd1281c 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_CCORR,
>>> DDP_COMPONENT_COLOR0,
>>> DDP_COMPONENT_COLOR1,
>>> - DDP_COMPONENT_DITHER,
>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>> + DDP_COMPONENT_DITHER0,
>>> DDP_COMPONENT_DITHER1,
>>> DDP_COMPONENT_DP_INTF0,
>>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-05-13 7:42 ` Matthias Brugger
@ 2022-05-14 22:45 ` Chun-Kuang Hu
2022-05-17 10:29 ` Matthias Brugger
0 siblings, 1 reply; 14+ messages in thread
From: Chun-Kuang Hu @ 2022-05-14 22:45 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, jason-jh.lin, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>
> Hi Chun-Kuang,
>
> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> > Hi, Matthias:
> >
> > Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
> >>
> >>
> >>
> >> On 19/04/2022 11:41, jason-jh.lin wrote:
> >>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> >>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >>>
> >>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>
> >> Chun-Kuang, I think it would make sense to take that through your tree as it
> >> depends on the previous patches.
> >>
> >> I provide you a stable tag so that you can take it:
> >> v5.18-next-vdso0-stable-tag
> >
> > After I take this tag, I find one checkpatch warning:
> >
> > WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> > un-documented -- check ./Documentation/devicetree/bindings/
> > #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> > + .compatible = "mediatek,mt8195-mmsys",
> >
> > I think this tag lost one binding patch, it's better that this tag has
> > no this warning.
> >
>
> Sorry for the late reply I was sick.
> The warning is, because the stable branch misses commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>
> So it's not a real issue and will go away once our branches land in upstream.
> Is it OK for you to ignore the issue?
It's OK for me, but the patch would go through different maintainer's
tree and I'm not sure it's OK for all of them. So I would wait for the
necessary patch land in upstream.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > Regards,
> > Chun-Kuang.
> >
> >>
> >> Regards,
> >> Matthias
> >>
> >>> ---
> >>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> >>> 1 file changed, 1 insertion(+), 2 deletions(-)
> >>>
> >>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> index 59117d970daf..fb719fd1281c 100644
> >>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> >>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> >>> DDP_COMPONENT_CCORR,
> >>> DDP_COMPONENT_COLOR0,
> >>> DDP_COMPONENT_COLOR1,
> >>> - DDP_COMPONENT_DITHER,
> >>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >>> + DDP_COMPONENT_DITHER0,
> >>> DDP_COMPONENT_DITHER1,
> >>> DDP_COMPONENT_DP_INTF0,
> >>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-05-14 22:45 ` Chun-Kuang Hu
@ 2022-05-17 10:29 ` Matthias Brugger
0 siblings, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2022-05-17 10:29 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
On 15/05/2022 00:45, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>>
>> Hi Chun-Kuang,
>>
>> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
>>> Hi, Matthias:
>>>
>>> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>>>
>>>>
>>>>
>>>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>>>
>>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>>
>>>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>>>
>>>> Chun-Kuang, I think it would make sense to take that through your tree as it
>>>> depends on the previous patches.
>>>>
>>>> I provide you a stable tag so that you can take it:
>>>> v5.18-next-vdso0-stable-tag
>>>
>>> After I take this tag, I find one checkpatch warning:
>>>
>>> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
>>> un-documented -- check ./Documentation/devicetree/bindings/
>>> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
>>> + .compatible = "mediatek,mt8195-mmsys",
>>>
>>> I think this tag lost one binding patch, it's better that this tag has
>>> no this warning.
>>>
>>
>> Sorry for the late reply I was sick.
>> The warning is, because the stable branch misses commit:
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>>
>> So it's not a real issue and will go away once our branches land in upstream.
>> Is it OK for you to ignore the issue?
>
> It's OK for me, but the patch would go through different maintainer's
> tree and I'm not sure it's OK for all of them. So I would wait for the
> necessary patch land in upstream.
>
Ok makes sense. Sorry for the bad coordination from my side on this.
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> Regards,
>>> Chun-Kuang.
>>>
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>>> ---
>>>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> index 59117d970daf..fb719fd1281c 100644
>>>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>>>> DDP_COMPONENT_CCORR,
>>>>> DDP_COMPONENT_COLOR0,
>>>>> DDP_COMPONENT_COLOR1,
>>>>> - DDP_COMPONENT_DITHER,
>>>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>>>> + DDP_COMPONENT_DITHER0,
>>>>> DDP_COMPONENT_DITHER1,
>>>>> DDP_COMPONENT_DP_INTF0,
>>>>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
[not found] <20220419094143.9561-1-jason-jh.lin@mediatek.com>
` (3 preceding siblings ...)
[not found] ` <20220419094143.9561-9-jason-jh.lin@mediatek.com>
@ 2022-05-25 9:50 ` AngeloGioacchino Del Regno
2022-05-25 13:18 ` Jason-JH Lin
4 siblings, 1 reply; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-25 9:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Il 19/04/22 11:41, jason-jh.lin ha scritto:
> From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
>
Hello Jason,
this series does not apply cleanly anymore on next-20220525, can you please
rebase and resend?
I hope that with a bit of coordination, we can get the entire display stack
finally upstreamed in v5.19... it's been quite a while... :-)
Cheers,
Angelo
> Change in v20:
> - split binding patch to another series 'MediaTek MT8195 display binding':
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> - fix io_start type from u32 to resource_size_t
> - fix some commit message for DITHER enum
>
> Change in v19:
> - fix checking condition for the return vaule of platform resource
> - drm/mediatek fix build waning for [-Wunused-const-variable]
>
> Change in v18:
> - change get driver data by io_start and wrap mmsys driver data into
> mmsys match data structure to support identifying multi mmsys driver
> data with the same compatible name
> - change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
>
> Change in v17:
> - change compatible name from 2 vdosys to 1 mmsys
> - add get driver data by clk name function to get corresponding
> driver data for mt8195 vdosys0
> - add all routing table setting for mt8195 vdosys0
> - remove useless mutex define
>
> Change in v16:
> - rebase on linu-next tag: 'next-20220303'
> - rebase on series: 'Fix MediaTek display dt-bindings issues'
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
> to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
> such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
> rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
> the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (8):
> soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> drm/mediatek: add DSC support for mediatek-drm
> drm/mediatek: add MERGE support for mediatek-drm
> drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
> drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
> soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
>
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 18 files changed, 1098 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
2022-05-25 9:50 ` [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195 AngeloGioacchino Del Regno
@ 2022-05-25 13:18 ` Jason-JH Lin
0 siblings, 0 replies; 14+ messages in thread
From: Jason-JH Lin @ 2022-05-25 13:18 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Hello Angelo,
OK, I'll rebase on next-20220525 and resend soon.
Regards,
Jason-JH.Lin
On Wed, 2022-05-25 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 19/04/22 11:41, jason-jh.lin ha scritto:
> > From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
> >
>
> Hello Jason,
>
> this series does not apply cleanly anymore on next-20220525, can you
> please
> rebase and resend?
>
> I hope that with a bit of coordination, we can get the entire display
> stack
> finally upstreamed in v5.19... it's been quite a while... :-)
>
> Cheers,
> Angelo
>
> > Change in v20:
> > - split binding patch to another series 'MediaTek MT8195 display
> > binding':
> >
> > https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> > - fix io_start type from u32 to resource_size_t
> > - fix some commit message for DITHER enum
snip...
^ permalink raw reply [flat|nested] 14+ messages in thread
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[not found] ` <20220419094143.9561-2-jason-jh.lin@mediatek.com>
2022-04-22 12:28 ` [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 Matthias Brugger
2022-04-24 8:47 ` Jason-JH Lin
[not found] ` <20220419094143.9561-3-jason-jh.lin@mediatek.com>
[not found] ` <82cc5e6900138e13ed9d75c6d2a42c6d7afc1959.camel@mediatek.com>
2022-04-22 2:32 ` [PATCH v20 2/8] soc: mediatek: add mtk-mutex " Jason-JH Lin
2022-04-22 12:31 ` Matthias Brugger
2022-04-24 8:48 ` Jason-JH Lin
2022-04-22 12:29 ` Matthias Brugger
[not found] ` <20220419094143.9561-7-jason-jh.lin@mediatek.com>
2022-04-22 12:32 ` [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum " Matthias Brugger
[not found] ` <20220419094143.9561-9-jason-jh.lin@mediatek.com>
2022-04-22 12:42 ` [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum Matthias Brugger
2022-05-01 22:54 ` Chun-Kuang Hu
2022-05-13 7:42 ` Matthias Brugger
2022-05-14 22:45 ` Chun-Kuang Hu
2022-05-17 10:29 ` Matthias Brugger
2022-05-25 9:50 ` [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195 AngeloGioacchino Del Regno
2022-05-25 13:18 ` Jason-JH Lin
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