From: Roger Lu <roger.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Enric Balletbo Serra <eballetbo@gmail.com>,
Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
YT Lee <yt.lee@mediatek.com>,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [PATCH v16 2/7] arm64: dts: mt8183: add svs device information
Date: Mon, 3 Jan 2022 14:08:15 +0800 [thread overview]
Message-ID: <63e17e727d8290a5ebd8c4c5cd8f2383fc1164cc.camel@mediatek.com> (raw)
In-Reply-To: <20cf2c1e-d55b-5780-8c6e-4d8beaca5a65@gmail.com>
Hi Matthias,
On Thu, 2021-12-30 at 13:54 +0100, Matthias Brugger wrote:
>
> On 28/04/2021 08:54, Roger Lu wrote:
> > add compitable/reg/irq/clock/efuse setting in svs node
> >
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index 80519a145f13..441d617ece43 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -657,6 +657,18 @@
> > status = "disabled";
> > };
> >
> > + svs: svs@1100b000 {
> > + compatible = "mediatek,mt8183-svs";
> > + reg = <0 0x1100b000 0 0x1000>;
> > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg CLK_INFRA_THERM>;
> > + clock-names = "main";
> > + nvmem-cells = <&svs_calibration>,
> > + <&thermal_calibration>;
> > + nvmem-cell-names = "svs-calibration-data",
> > + "t-calibration-data";
> > + };
> > +
> > pwm0: pwm@1100e000 {
> > compatible = "mediatek,mt8183-disp-pwm";
> > reg = <0 0x1100e000 0 0x1000>;
> > @@ -941,9 +953,15 @@
> > reg = <0 0x11f10000 0 0x1000>;
> > #address-cells = <1>;
> > #size-cells = <1>;
>
> Please add a new line between the different calibartion data, to improve
> readability.
No problem and thanks for the review.
> Regards,
> Matthias
>
> > + thermal_calibration: calib@180 {
> > + reg = <0x180 0xc>;
> > + };
> > mipi_tx_calibration: calib@190 {
> > reg = <0x190 0xc>;
> > };
> > + svs_calibration: calib@580 {
> > + reg = <0x580 0x64>;
> > + };
> > };
> >
> > u3phy: usb-phy@11f40000 {
> >
next prev parent reply other threads:[~2022-01-03 6:08 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 6:54 [PATCH v16 0/7] soc: mediatek: SVS: introduce MTK SVS Roger Lu
2021-04-28 6:54 ` [PATCH v16 1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2021-04-28 6:54 ` [PATCH v16 2/7] arm64: dts: mt8183: add svs device information Roger Lu
2021-10-20 15:20 ` AngeloGioacchino Del Regno
2021-12-24 7:33 ` Roger Lu
2021-12-30 12:54 ` Matthias Brugger
2022-01-03 6:08 ` Roger Lu [this message]
2021-04-28 6:54 ` [PATCH v16 3/7] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2021-05-06 4:51 ` Guenter Roeck
2021-05-14 3:10 ` Roger Lu
2021-05-14 3:33 ` Guenter Roeck
2021-05-14 5:58 ` Roger Lu
2021-10-21 8:46 ` AngeloGioacchino Del Regno
2021-12-24 9:27 ` Roger Lu
2021-12-24 9:34 ` AngeloGioacchino Del Regno
2021-04-28 6:54 ` [PATCH v16 4/7] soc: mediatek: SVS: add debug commands Roger Lu
2021-10-21 8:52 ` AngeloGioacchino Del Regno
2021-12-24 9:38 ` Roger Lu
2021-04-28 6:54 ` [PATCH v16 5/7] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2021-04-28 6:54 ` [PATCH v16 6/7] arm64: dts: mt8192: add svs device information Roger Lu
2021-10-20 15:16 ` AngeloGioacchino Del Regno
2021-12-24 9:42 ` Roger Lu
2021-10-20 15:18 ` AngeloGioacchino Del Regno
2021-04-28 6:54 ` [PATCH v16 7/7] soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
2021-05-14 3:20 ` YT Lee
2021-10-21 9:08 ` AngeloGioacchino Del Regno
2021-12-30 13:18 ` [PATCH v16 0/7] soc: mediatek: SVS: introduce MTK SVS Matthias Brugger
2022-01-03 7:43 ` Roger Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=63e17e727d8290a5ebd8c4c5cd8f2383fc1164cc.camel@mediatek.com \
--to=roger.lu@mediatek.com \
--cc=Angus.Lin@mediatek.com \
--cc=Charles.Yang@mediatek.com \
--cc=HenryC.Chen@mediatek.com \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=Xiaoqing.Liu@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@google.com \
--cc=eballetbo@gmail.com \
--cc=fan.chen@mediatek.com \
--cc=khilman@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pm@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=matthias.bgg@gmail.com \
--cc=nm@ti.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=yt.lee@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).