From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Roger Lu <roger.lu@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Enric Balletbo Serra <eballetbo@gmail.com>,
Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
YT Lee <yt.lee@mediatek.com>,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v16 6/7] arm64: dts: mt8192: add svs device information
Date: Wed, 20 Oct 2021 17:18:45 +0200 [thread overview]
Message-ID: <dec2190e-ce5a-3192-73b4-f4aae772bf2d@collabora.com> (raw)
In-Reply-To: <20210428065440.3704-7-roger.lu@mediatek.com>
Il 28/04/21 08:54, Roger Lu ha scritto:
> add compitable/reg/irq/clock/efuse/reset setting in svs node
>
> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
Hello Roger,
thanks for this series! However, there is an issue with this patch:
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index fe24cc66ff7a..e9816a56d87b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -270,6 +270,14 @@
> compatible = "mediatek,mt8192-infracfg", "syscon";
> reg = <0 0x10001000 0 0x1000>;
> #clock-cells = <1>;
> +
> + infracfg_rst: reset-controller {
> + compatible = "mediatek,infra-reset", "ti,syscon-reset";
> + #reset-cells = <1>;
> + ti,reset-bits = <
> + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: svs */
You are using macros here, which are defined in dt-bindings/reset/ti-syscon.h
hovever, you are not including this header in this devicetree, so it's not
compiling.
Please fix it.
> + >;
> + };
> };
>
> pericfg: syscon@10003000 {
> @@ -564,6 +572,20 @@
> status = "disabled";
> };
>
> + svs: svs@1100b000 {
> + compatible = "mediatek,mt8192-svs";
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg CLK_INFRA_THERM>;
> + clock-names = "main";
> + nvmem-cells = <&svs_calibration>,
> + <&lvts_e_data1>;
> + nvmem-cell-names = "svs-calibration-data",
> + "t-calibration-data";
> + resets = <&infracfg_rst 0>;
> + reset-names = "svs_rst";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
> @@ -681,6 +703,18 @@
> #clock-cells = <1>;
> };
>
> + efuse: efuse@11c10000 {
> + compatible = "mediatek,efuse";
> + reg = <0 0x11c10000 0 0x1000>;
> +
arch/arm64/boot/dts/mediatek/mt8192.dtsi:510.5-24: Warning (reg_format):
/soc/efuse@11c10000/data1:reg: property has invalid length (8 bytes)
(#address-cells == 2, #size-cells == 1)
arch/arm64/boot/dts/mediatek/mt8192.dtsi:513.5-24: Warning (reg_format):
/soc/efuse@11c10000/calib@580:reg: property has invalid length (8 bytes)
(#address-cells == 2, #size-cells == 1)
In short, you should add here:
#address-cells = <1>;
#size-cells = <1>;
> + lvts_e_data1: data1 {
> + reg = <0x1C0 0x58>;
> + };
> + svs_calibration: calib@580 {
> + reg = <0x580 0x68>;
> + };
> + };
> +
> i2c3: i2c3@11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
>
P.S.: Sorry for the double email, the previous one got sent with the wrong
address.
Regards,
- Angelo
next prev parent reply other threads:[~2021-10-20 15:18 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 6:54 [PATCH v16 0/7] soc: mediatek: SVS: introduce MTK SVS Roger Lu
2021-04-28 6:54 ` [PATCH v16 1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2021-04-28 6:54 ` [PATCH v16 2/7] arm64: dts: mt8183: add svs device information Roger Lu
2021-10-20 15:20 ` AngeloGioacchino Del Regno
2021-12-24 7:33 ` Roger Lu
2021-12-30 12:54 ` Matthias Brugger
2022-01-03 6:08 ` Roger Lu
2021-04-28 6:54 ` [PATCH v16 3/7] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2021-05-06 4:51 ` Guenter Roeck
2021-05-14 3:10 ` Roger Lu
2021-05-14 3:33 ` Guenter Roeck
2021-05-14 5:58 ` Roger Lu
2021-10-21 8:46 ` AngeloGioacchino Del Regno
2021-12-24 9:27 ` Roger Lu
2021-12-24 9:34 ` AngeloGioacchino Del Regno
2021-04-28 6:54 ` [PATCH v16 4/7] soc: mediatek: SVS: add debug commands Roger Lu
2021-10-21 8:52 ` AngeloGioacchino Del Regno
2021-12-24 9:38 ` Roger Lu
2021-04-28 6:54 ` [PATCH v16 5/7] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2021-04-28 6:54 ` [PATCH v16 6/7] arm64: dts: mt8192: add svs device information Roger Lu
2021-10-20 15:16 ` AngeloGioacchino Del Regno
2021-12-24 9:42 ` Roger Lu
2021-10-20 15:18 ` AngeloGioacchino Del Regno [this message]
2021-04-28 6:54 ` [PATCH v16 7/7] soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
2021-05-14 3:20 ` YT Lee
2021-10-21 9:08 ` AngeloGioacchino Del Regno
2021-12-30 13:18 ` [PATCH v16 0/7] soc: mediatek: SVS: introduce MTK SVS Matthias Brugger
2022-01-03 7:43 ` Roger Lu
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