[PATCH v1 0/5] Add SPI Driver to HPE GXP Architecture

[PATCH v1 0/5] Add SPI Driver to HPE GXP Architecture

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash and bios part.

Nick Hawkins (5):
  spi: spi-gxp: Add support for HPE GXP SoCs
  spi: dt-bindings: add documentation for hpe,gxp-spifi
  ARM: dts: hpe: Add spi driver node
  ARM: configs: multi_v7_defconfig: Enable HPE GXP SPI driver
  MAINTAINERS: add spi support to GXP

 .../bindings/spi/hpe,gxp-spifi.yaml           |  56 +++
 MAINTAINERS                                   |   2 +
 arch/arm/boot/dts/hpe-bmc-dl360gen10.dts      |  58 +++
 arch/arm/boot/dts/hpe-gxp.dtsi                |  21 +-
 arch/arm/configs/multi_v7_defconfig           |   1 +
 drivers/spi/Kconfig                           |   7 +
 drivers/spi/Makefile                          |   1 +
 drivers/spi/spi-gxp.c                         | 355 ++++++++++++++++++
 8 files changed, 500 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
 create mode 100644 drivers/spi/spi-gxp.c

-- 
2.17.1

[PATCH v1 1/5] spi: spi-gxp: Add support for HPE GXP SoCs

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash and bios part.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 drivers/spi/Kconfig   |   7 +
 drivers/spi/Makefile  |   1 +
 drivers/spi/spi-gxp.c | 355 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 363 insertions(+)
 create mode 100644 drivers/spi/spi-gxp.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3b1044ebc400..543e4a5b5ffa 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -371,6 +371,13 @@ config SPI_FSL_QUADSPI
 	  This controller does not support generic SPI messages. It only
 	  supports the high-level SPI memory interface.
 
+config SPI_GXP
+	tristate "GXP SPI driver"
+	depends on ARCH_HPE || COMPILE_TEST
+	help
+	 This enables support for the driver for GXP bus attached SPI
+	 controllers.
+
 config SPI_HISI_KUNPENG
 	tristate "HiSilicon SPI Controller for Kunpeng SoCs"
 	depends on (ARM64 && ACPI) || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 0f44eb6083a5..ca5f204017ee 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_SPI_FSL_LPSPI)		+= spi-fsl-lpspi.o
 obj-$(CONFIG_SPI_FSL_QUADSPI)		+= spi-fsl-qspi.o
 obj-$(CONFIG_SPI_FSL_SPI)		+= spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO)			+= spi-gpio.o
+obj-$(CONFIG_SPI_GXP)			+= spi-gxp.o
 obj-$(CONFIG_SPI_HISI_KUNPENG)		+= spi-hisi-kunpeng.o
 obj-$(CONFIG_SPI_HISI_SFC_V3XX)		+= spi-hisi-sfc-v3xx.o
 obj-$(CONFIG_SPI_IMG_SPFI)		+= spi-img-spfi.o
diff --git a/drivers/spi/spi-gxp.c b/drivers/spi/spi-gxp.c
new file mode 100644
index 000000000000..85e800718d8a
--- /dev/null
+++ b/drivers/spi/spi-gxp.c
@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: GPL-2.0=or-later
+/* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */
+
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define GXP_SPI0_MAX_CHIPSELECT		2
+#define GXP_SPI_SLEEP_TIME 1
+#define GXP_SPI_TIMEOUT (130 * 1000000 / GXP_SPI_SLEEP_TIME)
+
+#define MANUAL_MODE		0
+#define DIRECT_MODE		1
+#define SPILDAT_LEN		256
+
+#define OFFSET_SPIMCFG		0x0
+#define OFFSET_SPIMCTRL		0x4
+#define OFFSET_SPICMD		0x5
+#define OFFSET_SPIDCNT		0x6
+#define OFFSET_SPIADDR		0x8
+#define OFFSET_SPIINTSTS	0xc
+
+#define SPIMCTRL_START		0x01
+#define SPIMCTRL_BUSY		0x02
+#define SPIMCTRL_DIR		0x08
+
+struct gxp_spi;
+
+struct gxp_spi_chip {
+	struct gxp_spi *spifi;
+	u32 cs;
+};
+
+struct gxp_spi_data {
+	u32 max_cs;
+	u32 mode_bits;
+};
+
+struct gxp_spi {
+	const struct gxp_spi_data *data;
+	void __iomem *reg_base;
+	void __iomem *dat_base;
+	void __iomem *dir_base;
+	struct device *dev;
+	struct gxp_spi_chip chips[GXP_SPI0_MAX_CHIPSELECT];
+};
+
+static void gxp_spi_set_mode(struct gxp_spi *spifi, int mode)
+{
+	u8 value;
+	void __iomem *reg_base = spifi->reg_base;
+
+	value = readb(reg_base + OFFSET_SPIMCTRL);
+
+	if (mode == MANUAL_MODE) {
+		writeb(0x55, reg_base + OFFSET_SPICMD);
+		writeb(0xaa, reg_base + OFFSET_SPICMD);
+		value &= ~0x30;
+	} else {
+		value |= 0x30;
+	}
+	writeb(value, reg_base + OFFSET_SPIMCTRL);
+}
+
+static int gxp_spi_read_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+	int ret = 0;
+	struct gxp_spi *spifi = chip->spifi;
+	void __iomem *reg_base = spifi->reg_base;
+	u32 value;
+	int cs;
+
+	cs = chip->cs;
+
+	value = readl(reg_base + OFFSET_SPIMCFG);
+	value &= ~(1 << 24);
+	value |= (cs << 24);
+	value &= ~(0x07 << 16);
+	value &= ~(0x1f << 19);
+	writel(value, reg_base + OFFSET_SPIMCFG);
+
+	writel(0, reg_base + OFFSET_SPIADDR);
+
+	writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
+
+	writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
+
+	value = readb(reg_base + OFFSET_SPIMCTRL);
+	value &= ~SPIMCTRL_DIR;
+	value |= SPIMCTRL_START;
+
+	writeb(value, reg_base + OFFSET_SPIMCTRL);
+
+	ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
+				 !(value & SPIMCTRL_BUSY),
+				 GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
+	if (ret) {
+		dev_warn(spifi->dev, "read reg busy time out\n");
+		return ret;
+	}
+
+	memcpy_fromio(op->data.buf.in, spifi->dat_base, op->data.nbytes);
+	return ret;
+}
+
+static int gxp_spi_write_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+	int ret = 0;
+	struct gxp_spi *spifi = chip->spifi;
+	void __iomem *reg_base = spifi->reg_base;
+	u32 value;
+	int cs;
+
+	cs = chip->cs;
+
+	value = readl(reg_base + OFFSET_SPIMCFG);
+	value &= ~(1 << 24);
+	value |= (cs << 24);
+	value &= ~(0x07 << 16);
+	value &= ~(0x1f << 19);
+	writel(value, reg_base + OFFSET_SPIMCFG);
+
+	writel(0, reg_base + OFFSET_SPIADDR);
+
+	writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
+
+	memcpy_toio(spifi->dat_base, op->data.buf.in, op->data.nbytes);
+
+	writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
+
+	value = readb(reg_base + OFFSET_SPIMCTRL);
+	value |= SPIMCTRL_DIR;
+	value |= SPIMCTRL_START;
+
+	writeb(value, reg_base + OFFSET_SPIMCTRL);
+
+	ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
+				 !(value & SPIMCTRL_BUSY),
+				 GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
+	if (ret)
+		dev_warn(spifi->dev, "write reg busy time out\n");
+
+	return ret;
+}
+
+static ssize_t gxp_spi_read(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+	int cs;
+	struct gxp_spi *spifi = chip->spifi;
+	u32 offset = op->addr.val;
+
+	cs = chip->cs;
+
+	if (cs == 0)
+		offset += 0x4000000;
+
+	memcpy_fromio(op->data.buf.in, spifi->dir_base + offset, op->data.nbytes);
+
+	return 0;
+}
+
+static ssize_t gxp_spi_write(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
+{
+	struct gxp_spi *spifi = chip->spifi;
+	void __iomem *reg_base = spifi->reg_base;
+	u32 write_len;
+	u32 value;
+	int cs;
+	int ret = 0;
+
+	cs = chip->cs;
+
+	write_len = op->data.nbytes;
+	if (write_len > SPILDAT_LEN)
+		write_len = SPILDAT_LEN;
+
+	value = readl(reg_base + OFFSET_SPIMCFG);
+	value &= ~(1 << 24);
+	value |= (cs << 24);
+	value &= ~(0x07 << 16);
+	value |= (op->addr.nbytes << 16);
+	value &= ~(0x1f << 19);
+	writel(value, reg_base + OFFSET_SPIMCFG);
+
+	writel(op->addr.val, reg_base + OFFSET_SPIADDR);
+
+	writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
+
+	writew(write_len, reg_base + OFFSET_SPIDCNT);
+
+	memcpy_toio(spifi->dat_base, op->data.buf.in, write_len);
+
+	value = readb(reg_base + OFFSET_SPIMCTRL);
+	value |= SPIMCTRL_DIR;
+	value |= SPIMCTRL_START;
+
+	writeb(value, reg_base + OFFSET_SPIMCTRL);
+
+	ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
+				 !(value & SPIMCTRL_BUSY),
+				 GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
+	if (ret) {
+		dev_warn(spifi->dev, "write busy time out\n");
+		return ret;
+	}
+
+	return write_len;
+}
+
+static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+	struct gxp_spi *spifi = spi_controller_get_devdata(mem->spi->master);
+	struct gxp_spi_chip *chip = &spifi->chips[mem->spi->chip_select];
+
+	int ret = 0;
+
+	if (op->data.dir == SPI_MEM_DATA_IN) {
+		if (!op->addr.nbytes)
+			ret = gxp_spi_read_reg(chip, op);
+		else
+			ret = gxp_spi_read(chip, op);
+	} else {
+		if (!op->addr.nbytes)
+			ret = gxp_spi_write_reg(chip, op);
+		else
+			ret = gxp_spi_write(chip, op);
+	}
+
+	return ret;
+}
+
+static int gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+	int ret;
+
+	ret = do_gxp_exec_mem_op(mem, op);
+	if (ret)
+		dev_err(&mem->spi->dev, "operation failed: %d", ret);
+
+	return ret;
+}
+
+static const struct spi_controller_mem_ops gxp_spi_mem_ops = {
+	.exec_op = gxp_exec_mem_op,
+};
+
+static int gxp_spi_setup(struct spi_device *spi)
+{
+	struct gxp_spi *spifi = spi_controller_get_devdata(spi->master);
+	unsigned int cs = spi->chip_select;
+	struct gxp_spi_chip *chip = &spifi->chips[cs];
+
+	chip->spifi = spifi;
+	chip->cs = cs;
+
+	gxp_spi_set_mode(spifi, MANUAL_MODE);
+
+	return 0;
+}
+
+static int gxp_spifi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	const struct gxp_spi_data *data;
+	struct spi_controller *ctlr;
+	struct gxp_spi *spifi;
+	struct resource *res;
+	int ret;
+
+	data = of_device_get_match_data(&pdev->dev);
+	if (!data) {
+		dev_err(&pdev->dev, "of_dev_get_match_data failed\n");
+		return -ENOMEM;
+	}
+
+	ctlr = devm_spi_alloc_master(dev, sizeof(*spifi));
+	if (!ctlr) {
+		dev_err(&pdev->dev, "spi_alloc_master failed\n");
+		return -ENOMEM;
+	}
+
+	spifi = spi_controller_get_devdata(ctlr);
+	if (!spifi) {
+		dev_err(&pdev->dev, "spi_controller_get_data failed\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, spifi);
+	spifi->data = data;
+	spifi->dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	spifi->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(spifi->reg_base))
+		return PTR_ERR(spifi->reg_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	spifi->dat_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(spifi->dat_base))
+		return PTR_ERR(spifi->dat_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	spifi->dir_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(spifi->dir_base))
+		return PTR_ERR(spifi->dir_base);
+
+	ctlr->mode_bits = data->mode_bits;
+	ctlr->bus_num = pdev->id;
+	ctlr->mem_ops = &gxp_spi_mem_ops;
+	ctlr->setup = gxp_spi_setup;
+	ctlr->num_chipselect = data->max_cs;
+	ctlr->dev.of_node = dev->of_node;
+
+	ret = devm_spi_register_controller(dev, ctlr);
+	if (ret) {
+		dev_err(&pdev->dev, "spi_register_controller failed\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int gxp_spifi_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct gxp_spi_data gxp_spifi_data = {
+	.max_cs	= 2,
+	.mode_bits = 0,
+};
+
+static const struct of_device_id gxp_spifi_match[] = {
+	{.compatible = "hpe,gxp-spifi", .data = &gxp_spifi_data },
+	{ /* null */ }
+};
+MODULE_DEVICE_TABLE(of, gxp_spifi_match);
+
+static struct platform_driver gxp_spifi_driver = {
+	.probe = gxp_spifi_probe,
+	.remove = gxp_spifi_remove,
+	.driver = {
+		.name = "gxp-spifi",
+		.of_match_table = gxp_spifi_match,
+	},
+};
+module_platform_driver(gxp_spifi_driver);
+
+MODULE_DESCRIPTION("HPE GXP SPI Flash Interface driver");
+MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>");
+MODULE_LICENSE("GPL");
-- 
2.17.1

[PATCH v1 2/5] spi: dt-bindings: add documentation for hpe,gxp-spifi

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Create documentation for the hpe,gxp-spifi binding to support access to
the SPI parts

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 .../bindings/spi/hpe,gxp-spifi.yaml           | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml

diff --git a/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml b/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
new file mode 100644
index 000000000000..015130ecf971
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/hpe,gxp-spifi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HPE GXP spi controller flash interface
+
+maintainers:
+  - Nick Hawkins <nick.hawkins@hpe.com>
+  - Jean-Marie Verdun <verdun@hpe.com>
+
+allOf:
+  - $ref: "spi-controller.yaml#"
+
+properties:
+  compatible:
+    const: hpe,gxp-spifi
+
+  reg:
+    items:
+      - description: cfg registers
+      - description: data registers
+      - description: mapped memory
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+
+    spi@200 {
+        compatible = "hpe,gxp-spifi";
+        reg = <0x200 0x80>, <0xc000 0x100>, <0x38000000 0x800000>;
+        interrupts = <20>;
+        interrupt-parrent = <&vic0>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        flash@0 {
+                reg = < 0 >;
+                compatible = "jedec,spi-nor";
+        };
+
+        flash@1 {
+                reg = < 1 >;
+                compatible = "jedec,spi-nor";
+        };
+    };
-- 
2.17.1

[PATCH v1 3/5] ARM: dts: hpe: Add spi driver node

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add support for the SPI flash interface on the GXP SoC.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 arch/arm/boot/dts/hpe-bmc-dl360gen10.dts | 58 ++++++++++++++++++++++++
 arch/arm/boot/dts/hpe-gxp.dtsi           | 21 ++++++++-
 2 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
index 3a7382ce40ef..d49dcef95c5c 100644
--- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
+++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
@@ -24,3 +24,61 @@
 		reg = <0x40000000 0x20000000>;
 	};
 };
+
+&spifi {
+	status = "okay";
+	flash@0 {
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u-boot@0 {
+				label = "u-boot";
+				reg = <0x0 0x60000>;
+			};
+
+			u-boot-env@60000 {
+				label = "u-boot-env";
+				reg = <0x60000 0x20000>;
+			};
+
+			kernel@80000 {
+				label = "kernel";
+				reg = <0x80000 0x4c0000>;
+			};
+
+			rofs@540000 {
+				label = "rofs";
+				reg = <0x540000 0x1740000>;
+			};
+
+			rwfs@1c80000 {
+				label = "rwfs";
+				reg = <0x1c80000 0x250000>;
+			};
+
+			section@1ed0000{
+				label = "section";
+				reg = <0x1ed0000 0x130000>;
+			};
+		};
+	};
+	flash@1 {
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			host-prime@0 {
+				label = "host-prime";
+				reg = <0x0 0x02000000>;
+			};
+
+			host-second@2000000 {
+				label = "host-second";
+				reg = <0x02000000 0x02000000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi
index cf735b3c4f35..f28349bdeee1 100644
--- a/arch/arm/boot/dts/hpe-gxp.dtsi
+++ b/arch/arm/boot/dts/hpe-gxp.dtsi
@@ -56,9 +56,28 @@
 			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0xc0000000 0x30000000>;
+			ranges = <0x0 0xc0000000 0x40000000>;
 			dma-ranges;
 
+			spifi: spi@200 {
+				compatible = "hpe,gxp-spifi";
+				reg = <0x200 0x80>, <0xc000 0x100>, <0x38000000 0x8000000>;
+				interrupts = <20>;
+				interrupt-parent = <&vic0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				flash@0 {
+					reg = <0>;
+					compatible = "jedec,spi-nor";
+				};
+
+				flash@1 {
+					reg = <1>;
+					compatible = "jedec,spi-nor";
+				};
+			};
+
 			vic0: interrupt-controller@eff0000 {
 				compatible = "arm,pl192-vic";
 				reg = <0xeff0000 0x1000>;
-- 
2.17.1

[PATCH v1 4/5] ARM: configs: multi_v7_defconfig: Enable HPE GXP SPI driver

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Enable the SPI driver on the HPE GXP BMC.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index ce9826bce29b..9dd827a6c3bc 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -443,6 +443,7 @@ CONFIG_SPI_CADENCE=y
 CONFIG_SPI_DAVINCI=y
 CONFIG_SPI_FSL_QUADSPI=m
 CONFIG_SPI_GPIO=m
+CONFIG_SPI_GXP=y
 CONFIG_SPI_FSL_DSPI=m
 CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_ORION=y
-- 
2.17.1

[PATCH v1 5/5] MAINTAINERS: add spi support to GXP

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add the spi driver and dt-binding documentation

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d..f87728549ecf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2140,11 +2140,13 @@ M:	Jean-Marie Verdun <verdun@hpe.com>
 M:	Nick Hawkins <nick.hawkins@hpe.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/hpe,gxp.yaml
+F:	Documentation/devicetree/bindings/spi/hpe,gxp-spi.yaml
 F:	Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
 F:	arch/arm/boot/dts/hpe-bmc*
 F:	arch/arm/boot/dts/hpe-gxp*
 F:	arch/arm/mach-hpe/
 F:	drivers/clocksource/timer-gxp.c
+F:	drivers/spi/spi-gxp.c
 F:	drivers/watchdog/gxp-wdt.c
 
 ARM/IGEP MACHINE SUPPORT
-- 
2.17.1

Re: [PATCH v1 2/5] spi: dt-bindings: add documentation for hpe,gxp-spifi

[Rob Herring]

On Wed, 20 Jul 2022 15:11:55 -0500, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Create documentation for the hpe,gxp-spifi binding to support access to
> the SPI parts
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
>  .../bindings/spi/hpe,gxp-spifi.yaml           | 56 +++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.example.dtb: spi@200: Unevaluated properties are not allowed ('interrupt-parrent' was unexpected)
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH v1 1/5] spi: spi-gxp: Add support for HPE GXP SoCs

[Krzysztof Kozlowski]

On 20/07/2022 22:11, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> The GXP supports 3 separate SPI interfaces to accommodate the system
> flash, core flash, and other functions. The SPI engine supports variable
> clock frequency, selectable 3-byte or 4-byte addressing and a
> configurable x1, x2, and x4 command/address/data modes. The memory
> buffer for reading and writing ranges between 256 bytes and 8KB. This
> driver supports access to the core flash and bios part.
> 

(...)

> +static int gxp_spifi_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	const struct gxp_spi_data *data;
> +	struct spi_controller *ctlr;
> +	struct gxp_spi *spifi;
> +	struct resource *res;
> +	int ret;
> +
> +	data = of_device_get_match_data(&pdev->dev);
> +	if (!data) {
> +		dev_err(&pdev->dev, "of_dev_get_match_data failed\n");

Is it even possible to happen? I don't think so, so definitely not worth
log message.

> +		return -ENOMEM;
> +	}
> +
> +	ctlr = devm_spi_alloc_master(dev, sizeof(*spifi));
> +	if (!ctlr) {
> +		dev_err(&pdev->dev, "spi_alloc_master failed\n");

Aren't you duplicating core messages?

> +		return -ENOMEM;
> +	}
> +
> +	spifi = spi_controller_get_devdata(ctlr);
> +	if (!spifi) {

Is it even possible?

> +		dev_err(&pdev->dev, "spi_controller_get_data failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	platform_set_drvdata(pdev, spifi);
> +	spifi->data = data;
> +	spifi->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	spifi->reg_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spifi->reg_base))
> +		return PTR_ERR(spifi->reg_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +	spifi->dat_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spifi->dat_base))
> +		return PTR_ERR(spifi->dat_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> +	spifi->dir_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spifi->dir_base))
> +		return PTR_ERR(spifi->dir_base);
> +
> +	ctlr->mode_bits = data->mode_bits;
> +	ctlr->bus_num = pdev->id;
> +	ctlr->mem_ops = &gxp_spi_mem_ops;
> +	ctlr->setup = gxp_spi_setup;
> +	ctlr->num_chipselect = data->max_cs;
> +	ctlr->dev.of_node = dev->of_node;
> +
> +	ret = devm_spi_register_controller(dev, ctlr);
> +	if (ret) {
> +		dev_err(&pdev->dev, "spi_register_controller failed\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int gxp_spifi_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}

It's empty, why do you need it?


Best regards,
Krzysztof

Re: [PATCH v1 2/5] spi: dt-bindings: add documentation for hpe,gxp-spifi

[Krzysztof Kozlowski]

On 20/07/2022 22:11, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Create documentation for the hpe,gxp-spifi binding to support access to
> the SPI parts
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
>  .../bindings/spi/hpe,gxp-spifi.yaml           | 56 +++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml b/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
> new file mode 100644
> index 000000000000..015130ecf971
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/hpe,gxp-spifi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HPE GXP spi controller flash interface
> +
> +maintainers:
> +  - Nick Hawkins <nick.hawkins@hpe.com>
> +  - Jean-Marie Verdun <verdun@hpe.com>
> +
> +allOf:
> +  - $ref: "spi-controller.yaml#"
> +
> +properties:
> +  compatible:
> +    const: hpe,gxp-spifi
> +
> +  reg:
> +    items:
> +      - description: cfg registers
> +      - description: data registers
> +      - description: mapped memory
> +  interrupts:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +
> +    spi@200 {
> +        compatible = "hpe,gxp-spifi";
> +        reg = <0x200 0x80>, <0xc000 0x100>, <0x38000000 0x800000>;
> +        interrupts = <20>;
> +        interrupt-parrent = <&vic0>;

Wrong property.

> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        flash@0 {
> +                reg = < 0 >;

Wrong indentation, no spaces for <.


Best regards,
Krzysztof

Re: [PATCH v1 4/5] ARM: configs: multi_v7_defconfig: Enable HPE GXP SPI driver

[Krzysztof Kozlowski]

On 20/07/2022 22:11, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Enable the SPI driver on the HPE GXP BMC.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
>  arch/arm/configs/multi_v7_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index ce9826bce29b..9dd827a6c3bc 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -443,6 +443,7 @@ CONFIG_SPI_CADENCE=y
>  CONFIG_SPI_DAVINCI=y
>  CONFIG_SPI_FSL_QUADSPI=m
>  CONFIG_SPI_GPIO=m
> +CONFIG_SPI_GXP=y

Module, so =m


Best regards,
Krzysztof

Re: [PATCH v1 1/5] spi: spi-gxp: Add support for HPE GXP SoCs

[Christophe JAILLET]

Hi,

a few nitpicks below, should there be a v2.

Le 20/07/2022 à 22:11, nick.hawkins-ZPxbGqLxI0U@public.gmane.org a écrit :
> From: Nick Hawkins <nick.hawkins-ZPxbGqLxI0U@public.gmane.org>
> 
> The GXP supports 3 separate SPI interfaces to accommodate the system
> flash, core flash, and other functions. The SPI engine supports variable
> clock frequency, selectable 3-byte or 4-byte addressing and a
> configurable x1, x2, and x4 command/address/data modes. The memory
> buffer for reading and writing ranges between 256 bytes and 8KB. This
> driver supports access to the core flash and bios part.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins-ZPxbGqLxI0U@public.gmane.org>
> ---
>   drivers/spi/Kconfig   |   7 +
>   drivers/spi/Makefile  |   1 +
>   drivers/spi/spi-gxp.c | 355 ++++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 363 insertions(+)
>   create mode 100644 drivers/spi/spi-gxp.c
> 

[...]

> diff --git a/drivers/spi/spi-gxp.c b/drivers/spi/spi-gxp.c
> new file mode 100644
> index 000000000000..85e800718d8a
> --- /dev/null
> +++ b/drivers/spi/spi-gxp.c
> @@ -0,0 +1,355 @@
> +// SPDX-License-Identifier: GPL-2.0=or-later
> +/* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */
> +
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/spi/spi.h>
> +#include <linux/spi/spi.h>

Same include twice.

> +#include <linux/spi/spi-mem.h>
> +

[...]

> +static int gxp_spi_read_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
> +{
> +	int ret = 0;

Useless initialization.

> +	struct gxp_spi *spifi = chip->spifi;
> +	void __iomem *reg_base = spifi->reg_base;
> +	u32 value;
> +	int cs;
> +
> +	cs = chip->cs;

Could be set in the initialization, as for the 2 other variables.
(if it makes sense)

> +
> +	value = readl(reg_base + OFFSET_SPIMCFG);
> +	value &= ~(1 << 24);
> +	value |= (cs << 24);
> +	value &= ~(0x07 << 16);
> +	value &= ~(0x1f << 19);
> +	writel(value, reg_base + OFFSET_SPIMCFG);
> +
> +	writel(0, reg_base + OFFSET_SPIADDR);
> +
> +	writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
> +
> +	writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
> +
> +	value = readb(reg_base + OFFSET_SPIMCTRL);
> +	value &= ~SPIMCTRL_DIR;
> +	value |= SPIMCTRL_START;
> +
> +	writeb(value, reg_base + OFFSET_SPIMCTRL);
> +
> +	ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
> +				 !(value & SPIMCTRL_BUSY),
> +				 GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
> +	if (ret) {
> +		dev_warn(spifi->dev, "read reg busy time out\n");
> +		return ret;
> +	}
> +
> +	memcpy_fromio(op->data.buf.in, spifi->dat_base, op->data.nbytes);
> +	return ret;
> +}
> +
> +static int gxp_spi_write_reg(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
> +{
> +	int ret = 0;

Useless initialization.

> +	struct gxp_spi *spifi = chip->spifi;
> +	void __iomem *reg_base = spifi->reg_base;
> +	u32 value;
> +	int cs;
> +
> +	cs = chip->cs;

Could be set in the initialization, as for the 2 other variables.
(if it makes sense)

> +
> +	value = readl(reg_base + OFFSET_SPIMCFG);
> +	value &= ~(1 << 24);
> +	value |= (cs << 24);
> +	value &= ~(0x07 << 16);
> +	value &= ~(0x1f << 19);
> +	writel(value, reg_base + OFFSET_SPIMCFG);
> +
> +	writel(0, reg_base + OFFSET_SPIADDR);
> +
> +	writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
> +
> +	memcpy_toio(spifi->dat_base, op->data.buf.in, op->data.nbytes);
> +
> +	writew(op->data.nbytes, reg_base + OFFSET_SPIDCNT);
> +
> +	value = readb(reg_base + OFFSET_SPIMCTRL);
> +	value |= SPIMCTRL_DIR;
> +	value |= SPIMCTRL_START;
> +
> +	writeb(value, reg_base + OFFSET_SPIMCTRL);
> +
> +	ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
> +				 !(value & SPIMCTRL_BUSY),
> +				 GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
> +	if (ret)
> +		dev_warn(spifi->dev, "write reg busy time out\n");
> +
> +	return ret;
> +}
> +
> +static ssize_t gxp_spi_read(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
> +{
> +	int cs;
> +	struct gxp_spi *spifi = chip->spifi;
> +	u32 offset = op->addr.val;
> +
> +	cs = chip->cs;

Could be set in the initialization, as for the 2 other variables.
(if it makes sense)

> +
> +	if (cs == 0)
> +		offset += 0x4000000;
> +
> +	memcpy_fromio(op->data.buf.in, spifi->dir_base + offset, op->data.nbytes);
> +
> +	return 0;
> +}
> +
> +static ssize_t gxp_spi_write(struct gxp_spi_chip *chip, const struct spi_mem_op *op)
> +{
> +	struct gxp_spi *spifi = chip->spifi;
> +	void __iomem *reg_base = spifi->reg_base;
> +	u32 write_len;
> +	u32 value;
> +	int cs;
> +	int ret = 0;

Useless initialization.

> +
> +	cs = chip->cs;

Could be set in the initialization, as for the 2 other variables.
(if it makes sense)

> +
> +	write_len = op->data.nbytes;
> +	if (write_len > SPILDAT_LEN)
> +		write_len = SPILDAT_LEN;
> +
> +	value = readl(reg_base + OFFSET_SPIMCFG);
> +	value &= ~(1 << 24);
> +	value |= (cs << 24);
> +	value &= ~(0x07 << 16);
> +	value |= (op->addr.nbytes << 16);
> +	value &= ~(0x1f << 19);
> +	writel(value, reg_base + OFFSET_SPIMCFG);
> +
> +	writel(op->addr.val, reg_base + OFFSET_SPIADDR);
> +
> +	writeb(op->cmd.opcode, reg_base + OFFSET_SPICMD);
> +
> +	writew(write_len, reg_base + OFFSET_SPIDCNT);
> +
> +	memcpy_toio(spifi->dat_base, op->data.buf.in, write_len);
> +
> +	value = readb(reg_base + OFFSET_SPIMCTRL);
> +	value |= SPIMCTRL_DIR;
> +	value |= SPIMCTRL_START;
> +
> +	writeb(value, reg_base + OFFSET_SPIMCTRL);
> +
> +	ret = readb_poll_timeout(reg_base + OFFSET_SPIMCTRL, value,
> +				 !(value & SPIMCTRL_BUSY),
> +				 GXP_SPI_SLEEP_TIME, GXP_SPI_TIMEOUT);
> +	if (ret) {
> +		dev_warn(spifi->dev, "write busy time out\n");
> +		return ret;
> +	}
> +
> +	return write_len;
> +}
> +
> +static int do_gxp_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
> +{
> +	struct gxp_spi *spifi = spi_controller_get_devdata(mem->spi->master);
> +	struct gxp_spi_chip *chip = &spifi->chips[mem->spi->chip_select];

Useless empty line.

> +
> +	int ret = 0;

Useless initialization. (But I'm not sure the compiler is smart enough 
to see it)

> +
> +	if (op->data.dir == SPI_MEM_DATA_IN) {
> +		if (!op->addr.nbytes)
> +			ret = gxp_spi_read_reg(chip, op);
> +		else
> +			ret = gxp_spi_read(chip, op);
> +	} else {
> +		if (!op->addr.nbytes)
> +			ret = gxp_spi_write_reg(chip, op);
> +		else
> +			ret = gxp_spi_write(chip, op);
> +	}
> +
> +	return ret;
> +}

[...]

> +static int gxp_spifi_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	const struct gxp_spi_data *data;
> +	struct spi_controller *ctlr;
> +	struct gxp_spi *spifi;
> +	struct resource *res;
> +	int ret;
> +
> +	data = of_device_get_match_data(&pdev->dev);
> +	if (!data) {
> +		dev_err(&pdev->dev, "of_dev_get_match_data failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	ctlr = devm_spi_alloc_master(dev, sizeof(*spifi));
> +	if (!ctlr) {
> +		dev_err(&pdev->dev, "spi_alloc_master failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	spifi = spi_controller_get_devdata(ctlr);
> +	if (!spifi) {
> +		dev_err(&pdev->dev, "spi_controller_get_data failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	platform_set_drvdata(pdev, spifi);
> +	spifi->data = data;
> +	spifi->dev = dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	spifi->reg_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spifi->reg_base))
> +		return PTR_ERR(spifi->reg_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +	spifi->dat_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spifi->dat_base))
> +		return PTR_ERR(spifi->dat_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> +	spifi->dir_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(spifi->dir_base))
> +		return PTR_ERR(spifi->dir_base);
> +
> +	ctlr->mode_bits = data->mode_bits;
> +	ctlr->bus_num = pdev->id;
> +	ctlr->mem_ops = &gxp_spi_mem_ops;
> +	ctlr->setup = gxp_spi_setup;
> +	ctlr->num_chipselect = data->max_cs;
> +	ctlr->dev.of_node = dev->of_node;
> +
> +	ret = devm_spi_register_controller(dev, ctlr);
> +	if (ret) {
> +		dev_err(&pdev->dev, "spi_register_controller failed\n");
> +		return ret;

Could be return dev_err_probe(), but it is mostly a matter of taste, I 
guess.

CJ