[PATCH V5 1/7] i2c: tegra: clean up macros

[PATCH V5 1/7] i2c: tegra: clean up macros

[Bitan Biswas]

Clean up macros by:
1) removing unused macros
2) replace constants by macro BIT()

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/i2c/busses/i2c-tegra.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 1dbba39..00692d8 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -54,20 +54,15 @@
 #define I2C_INT_STATUS				0x068
 #define I2C_INT_BUS_CLR_DONE			BIT(11)
 #define I2C_INT_PACKET_XFER_COMPLETE		BIT(7)
-#define I2C_INT_ALL_PACKETS_XFER_COMPLETE	BIT(6)
-#define I2C_INT_TX_FIFO_OVERFLOW		BIT(5)
-#define I2C_INT_RX_FIFO_UNDERFLOW		BIT(4)
 #define I2C_INT_NO_ACK				BIT(3)
 #define I2C_INT_ARBITRATION_LOST		BIT(2)
 #define I2C_INT_TX_FIFO_DATA_REQ		BIT(1)
 #define I2C_INT_RX_FIFO_DATA_REQ		BIT(0)
 #define I2C_CLK_DIVISOR				0x06c
 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT	16
-#define I2C_CLK_MULTIPLIER_STD_FAST_MODE	8
 
 #define DVC_CTRL_REG1				0x000
 #define DVC_CTRL_REG1_INTR_EN			BIT(10)
-#define DVC_CTRL_REG2				0x004
 #define DVC_CTRL_REG3				0x008
 #define DVC_CTRL_REG3_SW_PROG			BIT(26)
 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN		BIT(30)
@@ -75,24 +70,21 @@
 #define DVC_STATUS_I2C_DONE_INTR		BIT(30)
 
 #define I2C_ERR_NONE				0x00
-#define I2C_ERR_NO_ACK				0x01
-#define I2C_ERR_ARBITRATION_LOST		0x02
-#define I2C_ERR_UNKNOWN_INTERRUPT		0x04
+#define I2C_ERR_NO_ACK				BIT(0)
+#define I2C_ERR_ARBITRATION_LOST		BIT(1)
+#define I2C_ERR_UNKNOWN_INTERRUPT		BIT(2)
 
 #define PACKET_HEADER0_HEADER_SIZE_SHIFT	28
 #define PACKET_HEADER0_PACKET_ID_SHIFT		16
 #define PACKET_HEADER0_CONT_ID_SHIFT		12
 #define PACKET_HEADER0_PROTOCOL_I2C		BIT(4)
 
-#define I2C_HEADER_HIGHSPEED_MODE		BIT(22)
 #define I2C_HEADER_CONT_ON_NAK			BIT(21)
-#define I2C_HEADER_SEND_START_BYTE		BIT(20)
 #define I2C_HEADER_READ				BIT(19)
 #define I2C_HEADER_10BIT_ADDR			BIT(18)
 #define I2C_HEADER_IE_ENABLE			BIT(17)
 #define I2C_HEADER_REPEAT_START			BIT(16)
 #define I2C_HEADER_CONTINUE_XFER		BIT(15)
-#define I2C_HEADER_MASTER_ADDR_SHIFT		12
 #define I2C_HEADER_SLAVE_ADDR_SHIFT		1
 
 #define I2C_BUS_CLEAR_CNFG			0x084
@@ -106,8 +98,6 @@
 
 #define I2C_CONFIG_LOAD				0x08C
 #define I2C_MSTR_CONFIG_LOAD			BIT(0)
-#define I2C_SLV_CONFIG_LOAD			BIT(1)
-#define I2C_TIMEOUT_CONFIG_LOAD			BIT(2)
 
 #define I2C_CLKEN_OVERRIDE			0x090
 #define I2C_MST_CORE_CLKEN_OVR			BIT(0)
@@ -133,7 +123,6 @@
 #define I2C_STANDARD_MODE			100000
 #define I2C_FAST_MODE				400000
 #define I2C_FAST_PLUS_MODE			1000000
-#define I2C_HS_MODE				3500000
 
 /* Packet header size in bytes */
 #define I2C_PACKET_HEADER_SIZE			12
-- 
2.7.4

[PATCH V5 2/7] i2c: tegra: remove unnecessary variable init

[Bitan Biswas]

Remove variable initializations in functions that
are followed by assignments before use

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/i2c/busses/i2c-tegra.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 00692d8..f7116b7 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -689,7 +689,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
 	u32 val;
 	int err;
 	u32 clk_divisor, clk_multiplier;
-	u32 tsu_thd = 0;
+	u32 tsu_thd;
 	u8 tlow, thigh;
 
 	err = pm_runtime_get_sync(i2c_dev->dev);
@@ -1218,7 +1218,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 {
 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 	int i;
-	int ret = 0;
+	int ret;
 
 	ret = pm_runtime_get_sync(i2c_dev->dev);
 	if (ret < 0) {
@@ -1489,7 +1489,7 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 	void __iomem *base;
 	phys_addr_t base_phys;
 	int irq;
-	int ret = 0;
+	int ret;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	base_phys = res->start;
-- 
2.7.4

[PATCH V5 3/7] i2c: tegra: fix alignment and spacing violations

[Bitan Biswas]

Fix checkpatch.pl alignment and blank line check(s) in i2c-tegra.c

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/i2c/busses/i2c-tegra.c | 35 +++++++++++++++++++----------------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index f7116b7..2d381de 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -295,7 +295,7 @@ static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
  * to the I2C block inside the DVC block
  */
 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
-	unsigned long reg)
+					unsigned long reg)
 {
 	if (i2c_dev->is_dvc)
 		reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
@@ -303,7 +303,7 @@ static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 }
 
 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
-	unsigned long reg)
+		       unsigned long reg)
 {
 	writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 
@@ -318,13 +318,13 @@ static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 }
 
 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
-	unsigned long reg, int len)
+			unsigned long reg, int len)
 {
 	writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 }
 
 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
-	unsigned long reg, int len)
+		       unsigned long reg, int len)
 {
 	readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 }
@@ -669,10 +669,11 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 		i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 		if (in_interrupt())
 			err = readl_poll_timeout_atomic(addr, val, val == 0,
-					1000, I2C_CONFIG_LOAD_TIMEOUT);
+							1000,
+							I2C_CONFIG_LOAD_TIMEOUT);
 		else
-			err = readl_poll_timeout(addr, val, val == 0,
-					1000, I2C_CONFIG_LOAD_TIMEOUT);
+			err = readl_poll_timeout(addr, val, val == 0, 1000,
+						 I2C_CONFIG_LOAD_TIMEOUT);
 
 		if (err) {
 			dev_warn(i2c_dev->dev,
@@ -1013,7 +1014,8 @@ static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
 }
 
 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
-	struct i2c_msg *msg, enum msg_end_type end_state)
+			      struct i2c_msg *msg,
+			      enum msg_end_type end_state)
 {
 	u32 packet_header;
 	u32 int_mask;
@@ -1150,9 +1152,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 		if (err)
 			return err;
 
-		time_left = wait_for_completion_timeout(
-						&i2c_dev->dma_complete,
-						msecs_to_jiffies(xfer_time));
+		time_left = wait_for_completion_timeout(&i2c_dev->dma_complete,
+							msecs_to_jiffies(xfer_time));
 		if (time_left == 0) {
 			dev_err(i2c_dev->dev, "DMA transfer timeout\n");
 			dmaengine_terminate_sync(i2c_dev->msg_read ?
@@ -1214,7 +1215,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 }
 
 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
-	int num)
+			  int num)
 {
 	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 	int i;
@@ -1260,14 +1261,15 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
 {
 	struct device_node *np = i2c_dev->dev->of_node;
 	int ret;
+	bool multi_mode;
 
 	ret = of_property_read_u32(np, "clock-frequency",
-			&i2c_dev->bus_clk_rate);
+				   &i2c_dev->bus_clk_rate);
 	if (ret)
 		i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 
-	i2c_dev->is_multimaster_mode = of_property_read_bool(np,
-			"multi-master");
+	multi_mode = of_property_read_bool(np, "multi-master");
+	i2c_dev->is_multimaster_mode = multi_mode;
 }
 
 static const struct i2c_algorithm tegra_i2c_algo = {
@@ -1611,7 +1613,7 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 	}
 
 	ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
-			tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
+			       tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 		goto release_dma;
@@ -1704,6 +1706,7 @@ static const struct dev_pm_ops tegra_i2c_pm = {
 	SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
 			   NULL)
 };
+
 #define TEGRA_I2C_PM	(&tegra_i2c_pm)
 #else
 #define TEGRA_I2C_PM	NULL
-- 
2.7.4

[PATCH V5 4/7] i2c: tegra: add spinlock definition comment

[Bitan Biswas]

Fix checkpatch.pl CHECK as follows:
CHECK: spinlock_t definition without comment
+       spinlock_t xfer_lock;

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/i2c/busses/i2c-tegra.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 2d381de..bececa6 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -269,6 +269,7 @@ struct tegra_i2c_dev {
 	u32 bus_clk_rate;
 	u16 clk_divisor_non_hs_mode;
 	bool is_multimaster_mode;
+	/* xfer_lock: lock to serialize transfer submission and processing */
 	spinlock_t xfer_lock;
 	struct dma_chan *tx_dma_chan;
 	struct dma_chan *rx_dma_chan;
-- 
2.7.4

[PATCH V5 5/7] i2c: tegra: fix msleep warning

[Bitan Biswas]

Fix checkpatch.pl WARNING for delay of approximately 1msec
in flush i2c FIFO polling loop by using usleep_range(1000, 2000):
WARNING: msleep < 20ms can sleep for up to 20ms; see ...
Documentation/timers/timers-howto.txt
+               msleep(1);

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/i2c/busses/i2c-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index bececa6..4dfb4c1 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -476,7 +476,7 @@ static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 			dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 			return -ETIMEDOUT;
 		}
-		msleep(1);
+		usleep_range(1000, 2000);
 	}
 	return 0;
 }
-- 
2.7.4

[PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Bitan Biswas]

Fix expression for residual bytes(less than word) transfer
in I2C PIO mode RX/TX.

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
---
 drivers/i2c/busses/i2c-tegra.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 4dfb4c1..0596c12 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -514,7 +514,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 	 * If there is a partial word at the end of buf, handle it manually to
 	 * prevent overwriting past the end of buf
 	 */
-	if (rx_fifo_avail > 0 && buf_remaining > 0) {
+	if (rx_fifo_avail > 0 &&
+	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
 		BUG_ON(buf_remaining > 3);
 		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 		val = cpu_to_le32(val);
@@ -557,11 +558,10 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 			words_to_transfer = tx_fifo_avail;
 
 		/*
-		 * Update state before writing to FIFO.  If this casues us
+		 * Update state before writing to FIFO.  If this causes us
 		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
 		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
-		 * not maskable).  We need to make sure that the isr sees
-		 * buf_remaining as 0 and doesn't call us back re-entrantly.
+		 * not maskable).
 		 */
 		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 		tx_fifo_avail -= words_to_transfer;
@@ -580,7 +580,8 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 	 * prevent reading past the end of buf, which could cross a page
 	 * boundary and fault.
 	 */
-	if (tx_fifo_avail > 0 && buf_remaining > 0) {
+	if (tx_fifo_avail > 0 &&
+	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
 		BUG_ON(buf_remaining > 3);
 		memcpy(&val, buf, buf_remaining);
 		val = le32_to_cpu(val);
-- 
2.7.4

[PATCH V5 7/7] i2c: tegra: remove BUG, BUG_ON

[Bitan Biswas]

Remove redundant BUG_ON calls or replace with WARN_ON_ONCE
as needed. Remove BUG() and make Rx and Tx case handling
similar. Add WARN_ON_ONCE check for non-zero rx_fifo_avail
in tegra_i2c_empty_rx_fifo() and return new error
I2C_ERR_UNEXPECTED_STATUS.

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
---
 drivers/i2c/busses/i2c-tegra.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 0596c12..2c8f051 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -73,6 +73,7 @@
 #define I2C_ERR_NO_ACK				BIT(0)
 #define I2C_ERR_ARBITRATION_LOST		BIT(1)
 #define I2C_ERR_UNKNOWN_INTERRUPT		BIT(2)
+#define I2C_ERR_UNEXPECTED_STATUS		BIT(3)
 
 #define PACKET_HEADER0_HEADER_SIZE_SHIFT	28
 #define PACKET_HEADER0_PACKET_ID_SHIFT		16
@@ -516,15 +517,15 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 	 */
 	if (rx_fifo_avail > 0 &&
 	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
-		BUG_ON(buf_remaining > 3);
 		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 		val = cpu_to_le32(val);
 		memcpy(buf, &val, buf_remaining);
 		buf_remaining = 0;
 		rx_fifo_avail--;
 	}
+	if (WARN_ON_ONCE(rx_fifo_avail))
+		return -EINVAL;
 
-	BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 	i2c_dev->msg_buf_remaining = buf_remaining;
 	i2c_dev->msg_buf = buf;
 
@@ -582,7 +583,6 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 	 */
 	if (tx_fifo_avail > 0 &&
 	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
-		BUG_ON(buf_remaining > 3);
 		memcpy(&val, buf, buf_remaining);
 		val = le32_to_cpu(val);
 
@@ -848,10 +848,16 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 
 	if (!i2c_dev->is_curr_dma_xfer) {
 		if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
-			if (i2c_dev->msg_buf_remaining)
-				tegra_i2c_empty_rx_fifo(i2c_dev);
-			else
-				BUG();
+			if (i2c_dev->msg_buf_remaining) {
+				if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
+					i2c_dev->msg_err |=
+						I2C_ERR_UNEXPECTED_STATUS;
+					goto err;
+				}
+			} else {
+				tegra_i2c_mask_irq(i2c_dev,
+						   I2C_INT_RX_FIFO_DATA_REQ);
+			}
 		}
 
 		if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
@@ -877,7 +883,10 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 	if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 		if (i2c_dev->is_curr_dma_xfer)
 			i2c_dev->msg_buf_remaining = 0;
-		BUG_ON(i2c_dev->msg_buf_remaining);
+		if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
+			i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
+			goto err;
+		}
 		complete(&i2c_dev->msg_complete);
 	}
 	goto done;
-- 
2.7.4

Re: [PATCH V5 7/7] i2c: tegra: remove BUG, BUG_ON

[Dmitry Osipenko]

11.06.2019 13:51, Bitan Biswas пишет:
> Remove redundant BUG_ON calls or replace with WARN_ON_ONCE
> as needed. Remove BUG() and make Rx and Tx case handling
> similar. Add WARN_ON_ONCE check for non-zero rx_fifo_avail
> in tegra_i2c_empty_rx_fifo() and return new error
> I2C_ERR_UNEXPECTED_STATUS.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> ---

Please see my answer to v4.

Re: [PATCH V5 1/7] i2c: tegra: clean up macros

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 295 bytes --]

On Tue, Jun 11, 2019 at 03:51:08AM -0700, Bitan Biswas wrote:
> Clean up macros by:
> 1) removing unused macros
> 2) replace constants by macro BIT()
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH V5 2/7] i2c: tegra: remove unnecessary variable init

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 299 bytes --]

On Tue, Jun 11, 2019 at 03:51:09AM -0700, Bitan Biswas wrote:
> Remove variable initializations in functions that
> are followed by assignments before use
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH V5 3/7] i2c: tegra: fix alignment and spacing violations

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 274 bytes --]

On Tue, Jun 11, 2019 at 03:51:10AM -0700, Bitan Biswas wrote:
> Fix checkpatch.pl alignment and blank line check(s) in i2c-tegra.c
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH V5 4/7] i2c: tegra: add spinlock definition comment

[Wolfram Sang]

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On Tue, Jun 11, 2019 at 03:51:11AM -0700, Bitan Biswas wrote:
> Fix checkpatch.pl CHECK as follows:
> CHECK: spinlock_t definition without comment
> +       spinlock_t xfer_lock;
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH V5 5/7] i2c: tegra: fix msleep warning

[Wolfram Sang]

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On Tue, Jun 11, 2019 at 03:51:12AM -0700, Bitan Biswas wrote:
> Fix checkpatch.pl WARNING for delay of approximately 1msec
> in flush i2c FIFO polling loop by using usleep_range(1000, 2000):
> WARNING: msleep < 20ms can sleep for up to 20ms; see ...
> Documentation/timers/timers-howto.txt
> +               msleep(1);
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>

Applied to for-next, thanks!


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Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Wolfram Sang]

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On Tue, Jun 11, 2019 at 03:51:13AM -0700, Bitan Biswas wrote:
> Fix expression for residual bytes(less than word) transfer
> in I2C PIO mode RX/TX.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>

I applied patches 1-5 to my for-next tree now. No need to resend them
anymore, you can focus on the remaining patches now.

Question: The nominal maintainer for this driver is

        Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA I2C DRIVER)

I wonder if he is still around and interested?

That aside, thanks a lot Dmitry for the review of this series!


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Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Dmitry Osipenko]

11.06.2019 13:51, Bitan Biswas пишет:
> Fix expression for residual bytes(less than word) transfer
> in I2C PIO mode RX/TX.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> ---
>  drivers/i2c/busses/i2c-tegra.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 4dfb4c1..0596c12 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -514,7 +514,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
>  	 * If there is a partial word at the end of buf, handle it manually to
>  	 * prevent overwriting past the end of buf
>  	 */
> -	if (rx_fifo_avail > 0 && buf_remaining > 0) {
> +	if (rx_fifo_avail > 0 &&
> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {

The buf_remaining >= BYTES_PER_FIFO_WORD is not possible to happen
because there are three possible cases:

1) buf_remaining > rx_fifo_avail * 4:

	In this case rx_fifo_avail = 0

2) buf_remaining < rx_fifo_avail * 4;

	In this case buf_remaining is always < 4 because
	words_to_transfer is a buf_remaining rounded down to 4
	and then divided by 4. Hence:

	buf_remaining -= (buf_remaining / 4) * 4 always results
	into buf_remaining < 4.

3) buf_remaining == rx_fifo_avail * 4:

	In this case rx_fifo_avail = 0 and buf_remaining = 0.

Case 2 should never happen and means that something gone wrong.

>  		BUG_ON(buf_remaining > 3);
>  		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
>  		val = cpu_to_le32(val);
> @@ -557,11 +558,10 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>  			words_to_transfer = tx_fifo_avail;
>  
>  		/*
> -		 * Update state before writing to FIFO.  If this casues us
> +		 * Update state before writing to FIFO.  If this causes us
>  		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>  		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
> -		 * not maskable).  We need to make sure that the isr sees
> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
> +		 * not maskable).
>  		 */
>  		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>  		tx_fifo_avail -= words_to_transfer;
> @@ -580,7 +580,8 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>  	 * prevent reading past the end of buf, which could cross a page
>  	 * boundary and fault.
>  	 */
> -	if (tx_fifo_avail > 0 && buf_remaining > 0) {
> +	if (tx_fifo_avail > 0 &&
> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
>  		BUG_ON(buf_remaining > 3);
>  		memcpy(&val, buf, buf_remaining);
>  		val = le32_to_cpu(val);
> 

Same as for RX.

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Dmitry Osipenko]

11.06.2019 13:51, Bitan Biswas пишет:
> Fix expression for residual bytes(less than word) transfer
> in I2C PIO mode RX/TX.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> ---

[snip]

>  		/*
> -		 * Update state before writing to FIFO.  If this casues us
> +		 * Update state before writing to FIFO.  If this causes us
>  		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>  		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
> -		 * not maskable).  We need to make sure that the isr sees
> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
> +		 * not maskable).
>  		 */
>  		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;

Looks like the comment could be removed altogether because it doesn't
make sense since interrupt handler is under xfer_lock which is kept
locked during of tegra_i2c_xfer_msg().

Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
but then what I2C_INT_PACKET_XFER_COMPLETE masking does?

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Bitan Biswas]

On 6/12/19 6:55 AM, Dmitry Osipenko wrote:
> 11.06.2019 13:51, Bitan Biswas пишет:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>> ---
>>   drivers/i2c/busses/i2c-tegra.c | 11 ++++++-----
>>   1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>> index 4dfb4c1..0596c12 100644
>> --- a/drivers/i2c/busses/i2c-tegra.c
>> +++ b/drivers/i2c/busses/i2c-tegra.c
>> @@ -514,7 +514,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
>>   	 * If there is a partial word at the end of buf, handle it manually to
>>   	 * prevent overwriting past the end of buf
>>   	 */
>> -	if (rx_fifo_avail > 0 && buf_remaining > 0) {
>> +	if (rx_fifo_avail > 0 &&
>> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
> 
> The buf_remaining >= BYTES_PER_FIFO_WORD is not possible to happen
> because there are three possible cases:
> 
> 1) buf_remaining > rx_fifo_avail * 4:
> 
> 	In this case rx_fifo_avail = 0
> 
> 2) buf_remaining < rx_fifo_avail * 4;
> 
> 	In this case buf_remaining is always < 4 because
> 	words_to_transfer is a buf_remaining rounded down to 4
> 	and then divided by 4. Hence:
> 
> 	buf_remaining -= (buf_remaining / 4) * 4 always results
> 	into buf_remaining < 4.
> 
> 3) buf_remaining == rx_fifo_avail * 4:
> 
> 	In this case rx_fifo_avail = 0 and buf_remaining = 0.
> 
> Case 2 should never happen and means that something gone wrong.
> 
Yes I now agree with you. The first condition "rx_fifo_avail > 0" 
failure will take care and prevent need for additional checks.

>>   		BUG_ON(buf_remaining > 3);
>>   		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
>>   		val = cpu_to_le32(val);
>> @@ -557,11 +558,10 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>>   			words_to_transfer = tx_fifo_avail;
>>   
>>   		/*
>> -		 * Update state before writing to FIFO.  If this casues us
>> +		 * Update state before writing to FIFO.  If this causes us
>>   		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>>   		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>> -		 * not maskable).  We need to make sure that the isr sees
>> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
>> +		 * not maskable).
>>   		 */
>>   		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>   		tx_fifo_avail -= words_to_transfer;
>> @@ -580,7 +580,8 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>>   	 * prevent reading past the end of buf, which could cross a page
>>   	 * boundary and fault.
>>   	 */
>> -	if (tx_fifo_avail > 0 && buf_remaining > 0) {
>> +	if (tx_fifo_avail > 0 &&
>> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
>>   		BUG_ON(buf_remaining > 3);
>>   		memcpy(&val, buf, buf_remaining);
>>   		val = le32_to_cpu(val);
>>
> 
> Same as for RX.
> 
Yes shall discard this patch from the next update.

-Thanks,
  Bitan

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Bitan Biswas]

On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
> 11.06.2019 13:51, Bitan Biswas пишет:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>> ---
> 
> [snip]
> 
>>   		/*
>> -		 * Update state before writing to FIFO.  If this casues us
>> +		 * Update state before writing to FIFO.  If this causes us
>>   		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>>   		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>> -		 * not maskable).  We need to make sure that the isr sees
>> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
>> +		 * not maskable).
>>   		 */
>>   		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
> 
> Looks like the comment could be removed altogether because it doesn't
> make sense since interrupt handler is under xfer_lock which is kept
> locked during of tegra_i2c_xfer_msg().
I would push a separate patch to remove this comment because of 
xfer_lock in ISR now.

> 
> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
> 
I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips 
newer than Tegra30 allows one to not see interrupt after Packet transfer 
complete. With the xfer_lock in ISR the scenario discussed in comment 
can be ignored.

-regards,
  Bitan

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Bitan Biswas]

On 6/12/19 3:24 AM, Wolfram Sang wrote:
> On Tue, Jun 11, 2019 at 03:51:13AM -0700, Bitan Biswas wrote:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> 
> I applied patches 1-5 to my for-next tree now. No need to resend them
> anymore, you can focus on the remaining patches now.
> 
> Question: The nominal maintainer for this driver is
> 
>          Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA I2C DRIVER)
> 
> I wonder if he is still around and interested?
> 
> That aside, thanks a lot Dmitry for the review of this series!
> 
Thanks Wolfram. I shall work on remaining patches.

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Laxman Dewangan]

On Wednesday 12 June 2019 03:54 PM, Wolfram Sang wrote:
> On Tue, Jun 11, 2019 at 03:51:13AM -0700, Bitan Biswas wrote:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> I applied patches 1-5 to my for-next tree now. No need to resend them
> anymore, you can focus on the remaining patches now.
>
> Question: The nominal maintainer for this driver is
>
>          Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA I2C DRIVER)
>
> I wonder if he is still around and interested?
>
> That aside, thanks a lot Dmitry for the review of this series!
>
Most of patches are coming from the downstream as part of upstream 
effort. Hence not reviewing explicitly.

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Dmitry Osipenko]

13.06.2019 14:30, Bitan Biswas пишет:
> 
> 
> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>> 11.06.2019 13:51, Bitan Biswas пишет:
>>> Fix expression for residual bytes(less than word) transfer
>>> in I2C PIO mode RX/TX.
>>>
>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>> ---
>>
>> [snip]
>>
>>>           /*
>>> -         * Update state before writing to FIFO.  If this casues us
>>> +         * Update state before writing to FIFO.  If this causes us
>>>            * to finish writing all bytes (AKA buf_remaining goes to
>>> 0) we
>>>            * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>> -         * not maskable).  We need to make sure that the isr sees
>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>> +         * not maskable).
>>>            */
>>>           buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>
>> Looks like the comment could be removed altogether because it doesn't
>> make sense since interrupt handler is under xfer_lock which is kept
>> locked during of tegra_i2c_xfer_msg().
> I would push a separate patch to remove this comment because of
> xfer_lock in ISR now.
> 
>>
>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>
> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
> newer than Tegra30 allows one to not see interrupt after Packet transfer
> complete. With the xfer_lock in ISR the scenario discussed in comment
> can be ignored.

Also note that xfer_lock could be removed and replaced with a just
irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
about IRQ not firing during of the preparation process.

It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
IRQ's could be simply unmasked during the driver's probe, in that case
it may worth to add a kind of "in-progress" flag to catch erroneous
interrupts.

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Wolfram Sang]

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> Most of patches are coming from the downstream as part of upstream effort.
> Hence not reviewing explicitly.

It would help me a lot if you could ack the patches, then, once you are
fine with them. I am really relying on driver maintainers these days. An
ack or rev from them is kinda required and speeds up things
significantly.


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Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Bitan Biswas]

On 6/13/19 5:28 AM, Dmitry Osipenko wrote:
> 13.06.2019 14:30, Bitan Biswas пишет:
>>
>>
>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>>> 11.06.2019 13:51, Bitan Biswas пишет:
>>>> Fix expression for residual bytes(less than word) transfer
>>>> in I2C PIO mode RX/TX.
>>>>
>>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>>> ---
>>>
>>> [snip]
>>>
>>>>            /*
>>>> -         * Update state before writing to FIFO.  If this casues us
>>>> +         * Update state before writing to FIFO.  If this causes us
>>>>             * to finish writing all bytes (AKA buf_remaining goes to
>>>> 0) we
>>>>             * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>>> -         * not maskable).  We need to make sure that the isr sees
>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>>> +         * not maskable).
>>>>             */
>>>>            buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>>
>>> Looks like the comment could be removed altogether because it doesn't
>>> make sense since interrupt handler is under xfer_lock which is kept
>>> locked during of tegra_i2c_xfer_msg().
>> I would push a separate patch to remove this comment because of
>> xfer_lock in ISR now.
>>
>>>
>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>>
>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
>> newer than Tegra30 allows one to not see interrupt after Packet transfer
>> complete. With the xfer_lock in ISR the scenario discussed in comment
>> can be ignored.
> 
> Also note that xfer_lock could be removed and replaced with a just
> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
> about IRQ not firing during of the preparation process.
This should need sufficient testing hence let us do it in a different 
series.

> 
> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
> IRQ's could be simply unmasked during the driver's probe, in that case
> it may worth to add a kind of "in-progress" flag to catch erroneous
> interrupts.
> 
TX interrupt needs special handling if this change is done. Hence I 
think it should be taken up after sufficient testing in a separate patch.

-regards,
  Bitan

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Dmitry Osipenko]

14.06.2019 12:50, Bitan Biswas пишет:
> 
> 
> On 6/13/19 5:28 AM, Dmitry Osipenko wrote:
>> 13.06.2019 14:30, Bitan Biswas пишет:
>>>
>>>
>>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>>>> 11.06.2019 13:51, Bitan Biswas пишет:
>>>>> Fix expression for residual bytes(less than word) transfer
>>>>> in I2C PIO mode RX/TX.
>>>>>
>>>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>>>> ---
>>>>
>>>> [snip]
>>>>
>>>>>            /*
>>>>> -         * Update state before writing to FIFO.  If this casues us
>>>>> +         * Update state before writing to FIFO.  If this causes us
>>>>>             * to finish writing all bytes (AKA buf_remaining goes to
>>>>> 0) we
>>>>>             * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>>>> -         * not maskable).  We need to make sure that the isr sees
>>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>>>> +         * not maskable).
>>>>>             */
>>>>>            buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>>>
>>>> Looks like the comment could be removed altogether because it doesn't
>>>> make sense since interrupt handler is under xfer_lock which is kept
>>>> locked during of tegra_i2c_xfer_msg().
>>> I would push a separate patch to remove this comment because of
>>> xfer_lock in ISR now.
>>>
>>>>
>>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>>>
>>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
>>> newer than Tegra30 allows one to not see interrupt after Packet transfer
>>> complete. With the xfer_lock in ISR the scenario discussed in comment
>>> can be ignored.
>>
>> Also note that xfer_lock could be removed and replaced with a just
>> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
>> about IRQ not firing during of the preparation process.
> This should need sufficient testing hence let us do it in a different series.

I don't think that there is much to test here since obviously it should work.

>>
>> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
>> IRQ's could be simply unmasked during the driver's probe, in that case
>> it may worth to add a kind of "in-progress" flag to catch erroneous
>> interrupts.
>>
> TX interrupt needs special handling if this change is done. Hence I think it should be
> taken up after sufficient testing in a separate patch.

This one is indeed a bit more trickier. Probably another alternative could be to keep GIC
interrupt disabled while no transfer is performed, then you'll have to request interrupt
in a disabled state using IRQ_NOAUTOEN flag.

And yes, that all should be a separate changes if you're going to implement them.

Re: [PATCH V5 6/7] i2c: tegra: fix PIO rx/tx residual transfer check

[Bitan Biswas]

On 6/14/19 6:02 AM, Dmitry Osipenko wrote:
> 14.06.2019 12:50, Bitan Biswas пишет:
>>
>>
>> On 6/13/19 5:28 AM, Dmitry Osipenko wrote:
>>> 13.06.2019 14:30, Bitan Biswas пишет:
>>>>
>>>>
>>>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>>>>> 11.06.2019 13:51, Bitan Biswas пишет:
>>>>>> Fix expression for residual bytes(less than word) transfer
>>>>>> in I2C PIO mode RX/TX.
>>>>>>
>>>>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>>>>> ---
>>>>>
>>>>> [snip]
>>>>>
>>>>>>             /*
>>>>>> -         * Update state before writing to FIFO.  If this casues us
>>>>>> +         * Update state before writing to FIFO.  If this causes us
>>>>>>              * to finish writing all bytes (AKA buf_remaining goes to
>>>>>> 0) we
>>>>>>              * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>>>>> -         * not maskable).  We need to make sure that the isr sees
>>>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>>>>> +         * not maskable).
>>>>>>              */
>>>>>>             buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>>>>
>>>>> Looks like the comment could be removed altogether because it doesn't
>>>>> make sense since interrupt handler is under xfer_lock which is kept
>>>>> locked during of tegra_i2c_xfer_msg().
>>>> I would push a separate patch to remove this comment because of
>>>> xfer_lock in ISR now.
>>>>
>>>>>
>>>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>>>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>>>>
>>>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
>>>> newer than Tegra30 allows one to not see interrupt after Packet transfer
>>>> complete. With the xfer_lock in ISR the scenario discussed in comment
>>>> can be ignored.
>>>
>>> Also note that xfer_lock could be removed and replaced with a just
>>> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
>>> about IRQ not firing during of the preparation process.
>> This should need sufficient testing hence let us do it in a different series.
> 
> I don't think that there is much to test here since obviously it should work.
> 
I shall push a patch for this as basic i2c read write test passed.

>>>
>>> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
>>> IRQ's could be simply unmasked during the driver's probe, in that case
>>> it may worth to add a kind of "in-progress" flag to catch erroneous
>>> interrupts.
>>>
>> TX interrupt needs special handling if this change is done. Hence I think it should be
>> taken up after sufficient testing in a separate patch.
> 
> This one is indeed a bit more trickier. Probably another alternative could be to keep GIC
> interrupt disabled while no transfer is performed, then you'll have to request interrupt
> in a disabled state using IRQ_NOAUTOEN flag.
> 
> And yes, that all should be a separate changes if you're going to implement them.
> 
OK

-Thanks,
  Bitan