[PATCH 1/4] clk: rockchip: add rk3288 isp_in clock ids

[PATCH 1/4] clk: rockchip: add rk3288 isp_in clock ids

[Jacob Chen]

Add clock-ids for the isp block of the rk3288.


Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
 include/dt-bindings/clock/rk3288-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index 9a586e2..08de7de 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -168,6 +168,7 @@
 #define PCLK_WDT		368
 #define PCLK_EFUSE256		369
 #define PCLK_EFUSE1024		370
+#define PCLK_ISP_IN		371
 
 /* hclk gates */
 #define HCLK_GPS		448
-- 
2.7.4

[PATCH 2/4] clk: rockchip: use rk3288 isp_in clock ids

[Jacob Chen]

Reference the newly added isp clock-ids in the clock-tree.


Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 39af05a..8047cea 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -801,7 +801,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 
 	GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
 	INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
-	GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
+	GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
 	INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
 };
 
-- 
2.7.4

[PATCH 3/4] clk: rockchip: add rk3288 cif_out clock ids

[Jacob Chen]

Add clock-ids for the cif block of the rk3288


Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
 include/dt-bindings/clock/rk3288-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index 08de7de..128b191 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -88,6 +88,7 @@
 #define SCLK_PVTM_GPU		124
 #define SCLK_CRYPTO		125
 #define SCLK_MIPIDSI_24M	126
+#define SCLK_CIF_OUT		127
 
 #define SCLK_MAC		151
 #define SCLK_MACREF_OUT		152
-- 
2.7.4

[PATCH 4/4] clk: rockchip: add rk3288 cif_out clock

[Jacob Chen]

Add the clocks for the cif block of the rk3288

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
 drivers/clk/rockchip/clk-rk3288.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 8047cea..f071c24 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -192,6 +192,7 @@ PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac", "xin24m" };
 PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
 PNAME(mux_uart3_p)	= { "uart3_src", "uart3_frac", "xin24m" };
 PNAME(mux_uart4_p)	= { "uart4_src", "uart4_frac", "xin24m" };
+PNAME(mux_cif_out_p)	= { "cif_src", "xin24m" };
 PNAME(mux_vip_out_p)	= { "vip_src", "xin24m" };
 PNAME(mux_mac_p)	= { "mac_pll_src", "ext_gmac" };
 PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };
@@ -448,6 +449,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 			RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
 			RK3288_CLKGATE_CON(3), 15, GFLAGS),
 
+	COMPOSITE_NOGATE(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
+			RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, 9, 5, DFLAGS),
+	COMPOSITE_NODIV(SCLK_CIF_OUT, "sclk_cif_out", mux_cif_out_p, 0,
+			RK3288_CLKSEL_CON(26), 15, 1, MFLAGS,
+			RK3288_CLKGATE_CON(3), 7, GFLAGS),
+
 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 			RK3288_CLKGATE_CON(5), 12, GFLAGS),
 	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
-- 
2.7.4

Re: [PATCH 4/4] clk: rockchip: add rk3288 cif_out clock

[Heiko Stuebner]

Hi Jacob,

Am Dienstag, 10. Januar 2017, 19:59:20 CET schrieb Jacob Chen:
> Add the clocks for the cif block of the rk3288
> 
> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
> ---
>  drivers/clk/rockchip/clk-rk3288.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c index 8047cea..f071c24 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -192,6 +192,7 @@ PNAME(mux_uart1_p)	= { "uart1_src", "uart1_frac",
> "xin24m" }; PNAME(mux_uart2_p)	= { "uart2_src", "uart2_frac", "xin24m" };
>  PNAME(mux_uart3_p)	= { "uart3_src", "uart3_frac", "xin24m" };
>  PNAME(mux_uart4_p)	= { "uart4_src", "uart4_frac", "xin24m" };
> +PNAME(mux_cif_out_p)	= { "cif_src", "xin24m" };
>  PNAME(mux_vip_out_p)	= { "vip_src", "xin24m" };
>  PNAME(mux_mac_p)	= { "mac_pll_src", "ext_gmac" };
>  PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };
> @@ -448,6 +449,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = { RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
>  			RK3288_CLKGATE_CON(3), 15, GFLAGS),
> 
> +	COMPOSITE_NOGATE(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
> +			RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, 9, 5, DFLAGS),
> +	COMPOSITE_NODIV(SCLK_CIF_OUT, "sclk_cif_out", mux_cif_out_p, 0,
> +			RK3288_CLKSEL_CON(26), 15, 1, MFLAGS,
> +			RK3288_CLKGATE_CON(3), 7, GFLAGS),
> +

we already have vip_src and sclk_vip_out defined, which I guess are the clocks 
you are adding here and according to the TRM I have the names are also correct 
(clock diagram 2).

But the clkid is not set yet, so I'd suggest adding SCLK_VIP_OUT and assigning 
to the existing clocks.

Also, according to the clock diagram, the gate needs to be (and already is) 
part of the vip_src clock and not the sclk_vip_out.


Heiko

Re: [PATCH 1/4] clk: rockchip: add rk3288 isp_in clock ids

[Heiko Stuebner]

Am Dienstag, 10. Januar 2017, 19:59:17 CET schrieb Jacob Chen:
> Add clock-ids for the isp block of the rk3288.
> 
> 
> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>

applied for 4.11

Thanks
Heiko

Re: [PATCH 2/4] clk: rockchip: use rk3288 isp_in clock ids

[Heiko Stuebner]

Am Dienstag, 10. Januar 2017, 19:59:18 CET schrieb Jacob Chen:
> Reference the newly added isp clock-ids in the clock-tree.
> 
> 
> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>

applied for 4.11

Thanks
Heiko

Re: [PATCH 4/4] clk: rockchip: add rk3288 cif_out clock

[Jacob Chen]

2017-01-13 21:53 GMT+08:00 Heiko Stuebner <heiko@sntech.de>:
> Hi Jacob,
>
> Am Dienstag, 10. Januar 2017, 19:59:20 CET schrieb Jacob Chen:
>> Add the clocks for the cif block of the rk3288
>>
>> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
>> ---
>>  drivers/clk/rockchip/clk-rk3288.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3288.c
>> b/drivers/clk/rockchip/clk-rk3288.c index 8047cea..f071c24 100644
>> --- a/drivers/clk/rockchip/clk-rk3288.c
>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>> @@ -192,6 +192,7 @@ PNAME(mux_uart1_p)        = { "uart1_src", "uart1_frac",
>> "xin24m" }; PNAME(mux_uart2_p)        = { "uart2_src", "uart2_frac", "xin24m" };
>>  PNAME(mux_uart3_p)   = { "uart3_src", "uart3_frac", "xin24m" };
>>  PNAME(mux_uart4_p)   = { "uart4_src", "uart4_frac", "xin24m" };
>> +PNAME(mux_cif_out_p) = { "cif_src", "xin24m" };
>>  PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
>>  PNAME(mux_mac_p)     = { "mac_pll_src", "ext_gmac" };
>>  PNAME(mux_hsadcout_p)        = { "hsadc_src", "ext_hsadc" };
>> @@ -448,6 +449,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
>> __initdata = { RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
>>                       RK3288_CLKGATE_CON(3), 15, GFLAGS),
>>
>> +     COMPOSITE_NOGATE(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
>> +                     RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, 9, 5, DFLAGS),
>> +     COMPOSITE_NODIV(SCLK_CIF_OUT, "sclk_cif_out", mux_cif_out_p, 0,
>> +                     RK3288_CLKSEL_CON(26), 15, 1, MFLAGS,
>> +                     RK3288_CLKGATE_CON(3), 7, GFLAGS),
>> +
>
> we already have vip_src and sclk_vip_out defined, which I guess are the clocks
> you are adding here and according to the TRM I have the names are also correct
> (clock diagram 2).
>
> But the clkid is not set yet, so I'd suggest adding SCLK_VIP_OUT and assigning
> to the existing clocks.
>
> Also, according to the clock diagram, the gate needs to be (and already is)
> part of the vip_src clock and not the sclk_vip_out.
>
>
> Heiko

Right, I didn't find that it have already been defined..