From: Sandipan Das <sandipan.das@amd.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: peterz@infradead.org, bp@alien8.de, dave.hansen@linux.intel.com,
acme@kernel.org, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, namhyung@kernel.org,
jolsa@kernel.org, tglx@linutronix.de, mingo@redhat.com,
pbonzini@redhat.com, jmattson@google.com, eranian@google.com,
ananth.narayan@amd.com, ravi.bangoria@amd.com,
santosh.shukla@amd.com,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-perf-users@vger.kernel.org, x86@kernel.org
Subject: Re: [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling
Date: Tue, 22 Mar 2022 14:07:58 +0530 [thread overview]
Message-ID: <7de451b4-32ff-c8b5-7c69-6440f73b59ae@amd.com> (raw)
In-Reply-To: <4bc9b537-f0de-5b75-5418-61c1d6dca849@gmail.com>
On 3/22/2022 12:36 PM, Like Xu wrote:
> On 17/3/2022 2:28 pm, Sandipan Das wrote:
>> + val = x86_perf_event_update(event);
>
> The variable 'val' set but not used.
>
>> + mask = BIT_ULL(idx);
>> +
>> + if (!(status & mask))
>
> Needed here ?
>
If you are referring to this previous usage of 'val' within
x86_pmu_handle_irq():
if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
then, no. Instead of looking at bit 47 of the raw counter value,
one can look at the overflow bits of the global status register
to determine if a counter overflow has occurred.
Will remove 'val' as you suggested since it is no longer needed
for any decision making.
next prev parent reply other threads:[~2022-03-22 8:38 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-17 6:28 [PATCH 0/7] perf/x86/amd/core: Add AMD PerfMonV2 support Sandipan Das
2022-03-17 6:28 ` [PATCH 1/7] x86/cpufeatures: Add PerfMonV2 feature bit Sandipan Das
2022-03-17 6:28 ` [PATCH 2/7] x86/msr: Add PerfCntrGlobal* registers Sandipan Das
2022-03-17 11:25 ` Peter Zijlstra
2022-03-17 6:28 ` [PATCH 3/7] perf/x86/amd/core: Detect PerfMonV2 support Sandipan Das
2022-03-17 11:27 ` Peter Zijlstra
2022-03-17 6:28 ` [PATCH 4/7] perf/x86/amd/core: Detect available counters Sandipan Das
2022-03-17 11:32 ` Peter Zijlstra
2022-03-17 6:28 ` [PATCH 5/7] perf/x86/amd/core: Add PerfMonV2 counter control Sandipan Das
2022-03-17 11:46 ` Peter Zijlstra
2022-03-18 8:02 ` Sandipan Das
2022-03-18 10:52 ` Peter Zijlstra
2022-03-17 6:28 ` [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling Sandipan Das
2022-03-17 12:01 ` Peter Zijlstra
2022-03-17 17:45 ` Stephane Eranian
2022-03-18 8:18 ` Sandipan Das
2022-03-22 7:06 ` Like Xu
2022-03-22 8:37 ` Sandipan Das [this message]
2022-03-17 6:28 ` [PATCH 7/7] kvm: x86/cpuid: Fix Architectural Performance Monitoring support Sandipan Das
2022-03-17 12:07 ` Peter Zijlstra
2022-03-18 7:59 ` Sandipan Das
2022-03-22 7:31 ` Like Xu
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