[PATCH 00/18] drm/sun4i: Allwinner MIPI-DSI support

[PATCH 00/18] drm/sun4i: Allwinner MIPI-DSI support

[Maxime Ripard]

Hi,

Here is an preliminary version of the MIPI-DSI support for the Allwinner
SoCs.

This controller can be found on a number of recent SoCs, such as the
A31, A33 or the A64.

Given the sparse documentation, there's a number of obscure areas, but
the current implementation has been tested with a 4-lanes DSI panel on
an A33.

In order to support properly the DSI controller, we also had to rework a
bit the TCON code to ease the encoders support. The support is a bit rough
around the edges at the time, and some artifacts are still shown on the
screen for some reasons. Wider testing with different display will
hopefully nail those down.

It depends for the moment on the clock protection serie sent by Jerome
Brunet:
http://lists.infradead.org/pipermail/linux-amlogic/2017-June/004059.html

Let me know what you think,
Maxime

Maxime Ripard (18):
  regmap: mmio: Add function to attach a clock
  drm/sun4i: Add if statement instead of depends on
  drm/sun4i: Realign Makefile padding and reorder it
  drm/sun4i: Remove useless atomic_check
  drm/sun4i: tcon: remove unused function
  drm/sun4i: tcon: Don't rely on encoders to enable the TCON
  drm/sun4i: tcon: Don't rely on encoders to set the TCON mode
  drm/sun4i: tcon: Add TRI finish interrupt for vblank
  drm/sun4i: tcon: Adjust dotclock dividers range
  drm/sun4i: tcon: Move out the tcon0 common setup
  dt-bindings: display: Add Allwinner MIPI-DSI bindings
  drm/sun4i: Add Allwinner A31 MIPI-DSI controller support
  dt-bindings: vendor: Add Huarui Lighting
  dt-bindings: panel: Add Huarui LHR050H41 panel documentation
  drm/panel: Add Huarui LHR050H41 panel driver
  arm: dts: sun8i: a33: Add the DSI-related nodes
  arm: dts: sun8i: Add BananaPI M2-Magic DTS
  [DO NOT MERGE] arm: dts: sun8i: bpi-m2m: Add DSI display

 Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt |   19 +-
 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt        |   85 ++++++-
 Documentation/devicetree/bindings/vendor-prefixes.txt                |    1 +-
 arch/arm/boot/dts/Makefile                                           |    1 +-
 arch/arm/boot/dts/sun8i-a33.dtsi                                     |   50 ++-
 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts                         |  360 ++++++++++++++++++++++++-
 drivers/base/regmap/regmap-mmio.c                                    |   24 ++-
 drivers/gpu/drm/panel/Kconfig                                        |    9 +-
 drivers/gpu/drm/panel/Makefile                                       |    1 +-
 drivers/gpu/drm/panel/panel-huarui-lhr050h41.c                       |  444 +++++++++++++++++++++++++++++-
 drivers/gpu/drm/sun4i/Kconfig                                        |   17 +-
 drivers/gpu/drm/sun4i/Makefile                                       |   31 +-
 drivers/gpu/drm/sun4i/sun4i_crtc.c                                   |   33 +-
 drivers/gpu/drm/sun4i/sun4i_dotclock.c                               |   20 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c                           |    1 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c                               |   15 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c                          |    1 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c                                  |    7 +-
 drivers/gpu/drm/sun4i/sun4i_rgb.c                                    |   37 +--
 drivers/gpu/drm/sun4i/sun4i_tcon.c                                   |  275 ++++++++++++------
 drivers/gpu/drm/sun4i/sun4i_tcon.h                                   |   68 ++--
 drivers/gpu/drm/sun4i/sun4i_tv.c                                     |   20 +-
 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c                              |  297 +++++++++++++++++++-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c                               | 1098 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h                               |   67 ++++-
 include/linux/regmap.h                                               |    4 +-
 26 files changed, 2783 insertions(+), 202 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
 create mode 100644 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
 create mode 100644 drivers/gpu/drm/panel/panel-huarui-lhr050h41.c
 create mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
 create mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h

base-commit: d3d855e7c4ffaaa6c2cb221849da65e979d8aa80
-- 
git-series 0.9.1

[PATCH 01/18] regmap: mmio: Add function to attach a clock

[Maxime Ripard]

regmap_init_mmio_clk allows to specify a clock that needs to be enabled
while accessing the registers.

However, that clock is retrieved through its clock ID, which means it will
lookup that clock based on the current device that registers the regmap,
and, in the DT case, will only look in that device OF node.

This might be problematic if the clock to enable is stored in another node.
Let's add a function that allows to attach a clock that has already been
retrieved to a regmap in order to fix this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/base/regmap/regmap-mmio.c | 24 ++++++++++++++++++++++++
 include/linux/regmap.h            |  4 ++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c
index 5189fd6182f6..5cadfd3394d8 100644
--- a/drivers/base/regmap/regmap-mmio.c
+++ b/drivers/base/regmap/regmap-mmio.c
@@ -28,6 +28,8 @@
 struct regmap_mmio_context {
 	void __iomem *regs;
 	unsigned val_bytes;
+
+	bool attached_clk;
 	struct clk *clk;
 
 	void (*reg_write)(struct regmap_mmio_context *ctx,
@@ -363,4 +365,26 @@ struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
 }
 EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
 
+int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
+{
+	struct regmap_mmio_context *ctx = map->bus_context;
+
+	ctx->clk = clk;
+	ctx->attached_clk = true;
+
+	return clk_prepare(ctx->clk);
+}
+EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
+
+void regmap_mmio_detach_clk(struct regmap *map)
+{
+	struct regmap_mmio_context *ctx = map->bus_context;
+
+	clk_unprepare(ctx->clk);
+
+	ctx->attached_clk = false;
+	ctx->clk = NULL;
+}
+EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
+
 MODULE_LICENSE("GPL v2");
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 978abfbac617..11a292a76586 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -21,6 +21,7 @@
 #include <linux/lockdep.h>
 
 struct module;
+struct clk;
 struct device;
 struct i2c_client;
 struct irq_domain;
@@ -789,6 +790,9 @@ bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg);
 	__regmap_lockdep_wrapper(__devm_regmap_init_ac97, #config,	\
 				ac97, config)
 
+int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk);
+void regmap_mmio_detach_clk(struct regmap *map);
+
 void regmap_exit(struct regmap *map);
 int regmap_reinit_cache(struct regmap *map,
 			const struct regmap_config *config);
-- 
git-series 0.9.1

[PATCH 02/18] drm/sun4i: Add if statement instead of depends on

[Maxime Ripard]

The depends on relationship is obvious, and using an if statement will
propagate it to every option without the need for each and every one of
them to define it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/Kconfig | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5bcad8f5fb4f..5cc116692913 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -13,9 +13,10 @@ config DRM_SUN4I
 	  Display Engine. If M is selected the module will be called
 	  sun4i-drm.
 
+if DRM_SUN4I
+
 config DRM_SUN4I_HDMI
        tristate "Allwinner A10 HDMI Controller Support"
-       depends on DRM_SUN4I
        default DRM_SUN4I
        help
 	  Choose this option if you have an Allwinner SoC with an HDMI
@@ -23,7 +24,6 @@ config DRM_SUN4I_HDMI
 
 config DRM_SUN4I_BACKEND
 	tristate "Support for Allwinner A10 Display Engine Backend"
-	depends on DRM_SUN4I
 	default DRM_SUN4I
 	help
 	  Choose this option if you have an Allwinner SoC with the
@@ -33,10 +33,11 @@ config DRM_SUN4I_BACKEND
 
 config DRM_SUN8I_MIXER
 	tristate "Support for Allwinner Display Engine 2.0 Mixer"
-	depends on DRM_SUN4I
 	default MACH_SUN8I
 	help
 	  Choose this option if you have an Allwinner SoC with the
 	  Allwinner Display Engine 2.0, which has a mixer to do some
 	  graphics mixture and feed graphics to TCON, If M is
 	  selected the module will be called sun8i-mixer.
+
+endif
-- 
git-series 0.9.1

[PATCH 03/18] drm/sun4i: Realign Makefile padding and reorder it

[Maxime Ripard]

Some options were not padded as they should, and the order in the Makefile
was chaotic. Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/Makefile | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index e29fd3a2ba9c..42871ee7acf6 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -1,23 +1,23 @@
-sun4i-drm-y += sun4i_drv.o
-sun4i-drm-y += sun4i_framebuffer.o
+sun4i-backend-y			+= sun4i_backend.o sun4i_layer.o
 
-sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
-sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
-sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
+sun4i-drm-y			+= sun4i_drv.o
+sun4i-drm-y			+= sun4i_framebuffer.o
 
-sun4i-tcon-y += sun4i_tcon.o
-sun4i-tcon-y += sun4i_rgb.o
-sun4i-tcon-y += sun4i_dotclock.o
-sun4i-tcon-y += sun4i_crtc.o
+sun4i-drm-hdmi-y		+= sun4i_hdmi_enc.o
+sun4i-drm-hdmi-y		+= sun4i_hdmi_ddc_clk.o
+sun4i-drm-hdmi-y		+= sun4i_hdmi_tmds_clk.o
 
-sun4i-backend-y += sun4i_backend.o sun4i_layer.o
+sun4i-tcon-y			+= sun4i_tcon.o
+sun4i-tcon-y			+= sun4i_rgb.o
+sun4i-tcon-y			+= sun4i_dotclock.o
+sun4i-tcon-y			+= sun4i_crtc.o
 
-sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
+sun8i-mixer-y			+= sun8i_mixer.o sun8i_layer.o
 
 obj-$(CONFIG_DRM_SUN4I)		+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)		+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)		+= sun4i_tv.o
 
-obj-$(CONFIG_DRM_SUN4I_BACKEND)		+= sun4i-backend.o
+obj-$(CONFIG_DRM_SUN4I_BACKEND)	+= sun4i-backend.o
 obj-$(CONFIG_DRM_SUN4I_HDMI)	+= sun4i-drm-hdmi.o
-obj-$(CONFIG_DRM_SUN8I_MIXER)		+= sun8i-mixer.o
+obj-$(CONFIG_DRM_SUN8I_MIXER)	+= sun8i-mixer.o
-- 
git-series 0.9.1

[PATCH 04/18] drm/sun4i: Remove useless atomic_check

[Maxime Ripard]

The atomic_check callback is optional, and we don't implement anything in
some parts of our drivers. Let's remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_layer.c | 7 -------
 drivers/gpu/drm/sun4i/sun4i_rgb.c   | 8 --------
 drivers/gpu/drm/sun4i/sun4i_tv.c    | 8 --------
 3 files changed, 23 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c
index ead4f9d4c1ee..62b08cb47ccd 100644
--- a/drivers/gpu/drm/sun4i/sun4i_layer.c
+++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
@@ -25,12 +25,6 @@ struct sun4i_plane_desc {
 	       uint32_t                nformats;
 };
 
-static int sun4i_backend_layer_atomic_check(struct drm_plane *plane,
-					    struct drm_plane_state *state)
-{
-	return 0;
-}
-
 static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane,
 					       struct drm_plane_state *old_state)
 {
@@ -53,7 +47,6 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane,
 }
 
 static struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = {
-	.atomic_check	= sun4i_backend_layer_atomic_check,
 	.atomic_disable	= sun4i_backend_layer_atomic_disable,
 	.atomic_update	= sun4i_backend_layer_atomic_update,
 };
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 422b191faa77..76362c09c608 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -128,13 +128,6 @@ static struct drm_connector_funcs sun4i_rgb_con_funcs = {
 	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
 };
 
-static int sun4i_rgb_atomic_check(struct drm_encoder *encoder,
-				  struct drm_crtc_state *crtc_state,
-				  struct drm_connector_state *conn_state)
-{
-	return 0;
-}
-
 static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
 {
 	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
@@ -182,7 +175,6 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
 }
 
 static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
-	.atomic_check	= sun4i_rgb_atomic_check,
 	.mode_set	= sun4i_rgb_encoder_mode_set,
 	.disable	= sun4i_rgb_encoder_disable,
 	.enable		= sun4i_rgb_encoder_enable,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 338b9e5bb2a3..73bfe7b1cd78 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -341,13 +341,6 @@ static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
 	mode->vtotal = mode->vsync_end  + tv_mode->vback_porch;
 }
 
-static int sun4i_tv_atomic_check(struct drm_encoder *encoder,
-				 struct drm_crtc_state *crtc_state,
-				 struct drm_connector_state *conn_state)
-{
-	return 0;
-}
-
 static void sun4i_tv_disable(struct drm_encoder *encoder)
 {
 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
@@ -489,7 +482,6 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
 }
 
 static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
-	.atomic_check	= sun4i_tv_atomic_check,
 	.disable	= sun4i_tv_disable,
 	.enable		= sun4i_tv_enable,
 	.mode_set	= sun4i_tv_mode_set,
-- 
git-series 0.9.1

[PATCH 05/18] drm/sun4i: tcon: remove unused function

[Maxime Ripard]

Even though that function is defined in the TCON header, it's not defined
nor used anywhere. Remove the prototype.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index e3c50ecdcd04..552c88ec16be 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -194,8 +194,6 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel);
 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
 
 /* Mode Related Controls */
-void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon,
-				 bool enable);
 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
 			struct drm_encoder *encoder);
 void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
-- 
git-series 0.9.1

[PATCH 06/18] drm/sun4i: tcon: Don't rely on encoders to enable the TCON

[Maxime Ripard]

So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.

This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.

We also needed to know which channel the encoder is connected to, which is
encoder-specific.

The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_crtc.c     | 22 ++++++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c |  8 +--
 drivers/gpu/drm/sun4i/sun4i_rgb.c      | 14 +---
 drivers/gpu/drm/sun4i/sun4i_tcon.c     | 91 +++++++++++++--------------
 drivers/gpu/drm/sun4i/sun4i_tcon.h     | 10 +---
 drivers/gpu/drm/sun4i/sun4i_tv.c       |  6 +--
 6 files changed, 70 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
index f8c70439d1e2..30c7568dde5c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
@@ -30,6 +30,22 @@
 #include "sunxi_engine.h"
 #include "sun4i_tcon.h"
 
+/*
+ * While this isn't really working in the DRM theory, in practice we
+ * can only ever have one encoder per TCON since we have a mux in our
+ * TCON.
+ */
+static struct drm_encoder *sun4i_crtc_get_encoder(struct drm_crtc *crtc)
+{
+	struct drm_encoder *encoder;
+
+	drm_for_each_encoder(encoder, crtc->dev)
+		if (encoder->crtc == crtc)
+			return encoder;
+
+	return NULL;
+}
+
 static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
 				    struct drm_crtc_state *old_state)
 {
@@ -71,11 +87,12 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
 
 static void sun4i_crtc_disable(struct drm_crtc *crtc)
 {
+	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
 
 	DRM_DEBUG_DRIVER("Disabling the CRTC\n");
 
-	sun4i_tcon_disable(scrtc->tcon);
+	sun4i_tcon_set_status(scrtc->tcon, encoder, false);
 
 	if (crtc->state->event && !crtc->state->active) {
 		spin_lock_irq(&crtc->dev->event_lock);
@@ -88,11 +105,12 @@ static void sun4i_crtc_disable(struct drm_crtc *crtc)
 
 static void sun4i_crtc_enable(struct drm_crtc *crtc)
 {
+	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
 
 	DRM_DEBUG_DRIVER("Enabling the CRTC\n");
 
-	sun4i_tcon_enable(scrtc->tcon);
+	sun4i_tcon_set_status(scrtc->tcon, encoder, true);
 }
 
 static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index d3398f6250ef..06af2f6d0b31 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -85,8 +85,6 @@ static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
 {
 	struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
-	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
-	struct sun4i_tcon *tcon = crtc->tcon;
 	u32 val;
 
 	DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
@@ -94,22 +92,16 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder)
 	val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
 	val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
-
-	sun4i_tcon_channel_disable(tcon, 1);
 }
 
 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
 {
 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 	struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
-	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
-	struct sun4i_tcon *tcon = crtc->tcon;
 	u32 val = 0;
 
 	DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
 
-	sun4i_tcon_channel_enable(tcon, 1);
-
 	sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
 	val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
 	val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 76362c09c608..ecce1f5b50ab 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -135,13 +135,10 @@ static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
 
 	DRM_DEBUG_DRIVER("Enabling RGB output\n");
 
-	if (!IS_ERR(tcon->panel))
+	if (!IS_ERR(tcon->panel)) {
 		drm_panel_prepare(tcon->panel);
-
-	sun4i_tcon_channel_enable(tcon, 0);
-
-	if (!IS_ERR(tcon->panel))
 		drm_panel_enable(tcon->panel);
+	}
 }
 
 static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
@@ -151,13 +148,10 @@ static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
 
 	DRM_DEBUG_DRIVER("Disabling RGB output\n");
 
-	if (!IS_ERR(tcon->panel))
+	if (!IS_ERR(tcon->panel)) {
 		drm_panel_disable(tcon->panel);
-
-	sun4i_tcon_channel_disable(tcon, 0);
-
-	if (!IS_ERR(tcon->panel))
 		drm_panel_unprepare(tcon->panel);
+	}
 }
 
 static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..dc70bc2a42a5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -14,6 +14,7 @@
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
+#include <drm/drm_encoder.h>
 #include <drm/drm_modes.h>
 #include <drm/drm_of.h>
 
@@ -32,66 +33,62 @@
 #include "sun4i_tcon.h"
 #include "sunxi_engine.h"
 
-void sun4i_tcon_disable(struct sun4i_tcon *tcon)
+static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
+					  bool enabled)
 {
-	DRM_DEBUG_DRIVER("Disabling TCON\n");
+	struct clk *clk;
 
-	/* Disable the TCON */
-	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
-			   SUN4I_TCON_GCTL_TCON_ENABLE, 0);
-}
-EXPORT_SYMBOL(sun4i_tcon_disable);
-
-void sun4i_tcon_enable(struct sun4i_tcon *tcon)
-{
-	DRM_DEBUG_DRIVER("Enabling TCON\n");
-
-	/* Enable the TCON */
-	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
-			   SUN4I_TCON_GCTL_TCON_ENABLE,
-			   SUN4I_TCON_GCTL_TCON_ENABLE);
-}
-EXPORT_SYMBOL(sun4i_tcon_enable);
-
-void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
-{
-	DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
-
-	/* Disable the TCON's channel */
-	if (channel == 0) {
+	switch (channel) {
+	case 0:
 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
-				   SUN4I_TCON0_CTL_TCON_ENABLE, 0);
-		clk_disable_unprepare(tcon->dclk);
+				   SUN4I_TCON0_CTL_TCON_ENABLE,
+				   enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
+		clk = tcon->dclk;
+		break;
+	case 1:
+		WARN_ON(!tcon->quirks->has_channel_1);
+		regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
+				   SUN4I_TCON1_CTL_TCON_ENABLE,
+				   enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
+		clk = tcon->sclk1;
+		break;
+	default:
+		DRM_DEBUG_DRIVER("Unknown channel... doing nothing\n");
 		return;
 	}
 
-	WARN_ON(!tcon->quirks->has_channel_1);
-	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
-			   SUN4I_TCON1_CTL_TCON_ENABLE, 0);
-	clk_disable_unprepare(tcon->sclk1);
+	if (enabled)
+		clk_prepare_enable(clk);
+	else
+		clk_disable_unprepare(clk);
 }
-EXPORT_SYMBOL(sun4i_tcon_channel_disable);
 
-void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
+void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
+			   struct drm_encoder *encoder,
+			   bool enabled)
 {
-	DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
-
-	/* Enable the TCON's channel */
-	if (channel == 0) {
-		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
-				   SUN4I_TCON0_CTL_TCON_ENABLE,
-				   SUN4I_TCON0_CTL_TCON_ENABLE);
-		clk_prepare_enable(tcon->dclk);
+	int channel;
+
+	switch (encoder->encoder_type) {
+	case DRM_MODE_ENCODER_NONE:
+		channel = 0;
+		break;
+	case DRM_MODE_ENCODER_TMDS:
+	case DRM_MODE_ENCODER_TVDAC:
+		channel = 1;
+		break;
+	default:
+		DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
 		return;
 	}
 
-	WARN_ON(!tcon->quirks->has_channel_1);
-	regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
-			   SUN4I_TCON1_CTL_TCON_ENABLE,
-			   SUN4I_TCON1_CTL_TCON_ENABLE);
-	clk_prepare_enable(tcon->sclk1);
+	sun4i_tcon_channel_set_status(tcon, channel, enabled);
+
+	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
+			   SUN4I_TCON_GCTL_TCON_ENABLE,
+			   enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
 }
-EXPORT_SYMBOL(sun4i_tcon_channel_enable);
+EXPORT_SYMBOL(sun4i_tcon_set_status);
 
 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 {
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 552c88ec16be..824732c90a2a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -183,15 +183,9 @@ struct sun4i_tcon {
 struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
 struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
 
-/* Global Control */
-void sun4i_tcon_disable(struct sun4i_tcon *tcon);
-void sun4i_tcon_enable(struct sun4i_tcon *tcon);
-
-/* Channel Control */
-void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel);
-void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel);
-
 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
+void sun4i_tcon_set_status(struct sun4i_tcon *crtc, struct drm_encoder *encoder,
+			   bool enable);
 
 /* Mode Related Controls */
 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 73bfe7b1cd78..78d6cf77fdd3 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -345,12 +345,9 @@ static void sun4i_tv_disable(struct drm_encoder *encoder)
 {
 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
 	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
-	struct sun4i_tcon *tcon = crtc->tcon;
 
 	DRM_DEBUG_DRIVER("Disabling the TV Output\n");
 
-	sun4i_tcon_channel_disable(tcon, 1);
-
 	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
 			   SUN4I_TVE_EN_ENABLE,
 			   0);
@@ -362,7 +359,6 @@ static void sun4i_tv_enable(struct drm_encoder *encoder)
 {
 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
 	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
-	struct sun4i_tcon *tcon = crtc->tcon;
 
 	DRM_DEBUG_DRIVER("Enabling the TV Output\n");
 
@@ -371,8 +367,6 @@ static void sun4i_tv_enable(struct drm_encoder *encoder)
 	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
 			   SUN4I_TVE_EN_ENABLE,
 			   SUN4I_TVE_EN_ENABLE);
-
-	sun4i_tcon_channel_enable(tcon, 1);
 }
 
 static void sun4i_tv_mode_set(struct drm_encoder *encoder,
-- 
git-series 0.9.1

[PATCH 07/18] drm/sun4i: tcon: Don't rely on encoders to set the TCON mode

[Maxime Ripard]

Just like we did for the TCON enable and disable, for historical reasons we
used to rely on the encoders calling the TCON mode_set function, while the
CRTC has a callback for that.

Let's implement it in order to reduce the boilerplate code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_crtc.c          | 11 ++++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c  |  1 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c      |  7 +---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c |  1 +-
 drivers/gpu/drm/sun4i/sun4i_rgb.c           | 15 +------
 drivers/gpu/drm/sun4i/sun4i_tcon.c          | 56 ++++++++++------------
 drivers/gpu/drm/sun4i/sun4i_tcon.h          | 10 +----
 drivers/gpu/drm/sun4i/sun4i_tv.c            |  6 +--
 8 files changed, 40 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
index 30c7568dde5c..886595f579ab 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
@@ -113,11 +113,22 @@ static void sun4i_crtc_enable(struct drm_crtc *crtc)
 	sun4i_tcon_set_status(scrtc->tcon, encoder, true);
 }
 
+static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
+	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
+
+	sun4i_tcon_mode_set(scrtc->tcon, encoder, mode);
+}
+
+
 static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = {
 	.atomic_begin	= sun4i_crtc_atomic_begin,
 	.atomic_flush	= sun4i_crtc_atomic_flush,
 	.disable	= sun4i_crtc_disable,
 	.enable		= sun4i_crtc_enable,
+	.mode_set_nofb	= sun4i_crtc_mode_set_nofb,
 };
 
 static int sun4i_crtc_enable_vblank(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index 4692e8c345ed..7348bdbaa803 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -12,7 +12,6 @@
 
 #include <linux/clk-provider.h>
 
-#include "sun4i_tcon.h"
 #include "sun4i_hdmi.h"
 
 struct sun4i_ddc {
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 06af2f6d0b31..67ef8acdb439 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -27,7 +27,6 @@
 #include "sun4i_crtc.h"
 #include "sun4i_drv.h"
 #include "sun4i_hdmi.h"
-#include "sun4i_tcon.h"
 
 #define DDC_SEGMENT_ADDR	0x30
 
@@ -119,15 +118,9 @@ static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
 				struct drm_display_mode *adjusted_mode)
 {
 	struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
-	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
-	struct sun4i_tcon *tcon = crtc->tcon;
 	unsigned int x, y;
 	u32 val;
 
-	sun4i_tcon1_mode_set(tcon, mode);
-	sun4i_tcon_set_mux(tcon, 1, encoder);
-
-	clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 	clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
 	clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5cf2527bffc8..5b6727623037 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -12,7 +12,6 @@
 
 #include <linux/clk-provider.h>
 
-#include "sun4i_tcon.h"
 #include "sun4i_hdmi.h"
 
 struct sun4i_tmds {
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index ecce1f5b50ab..9061e16e3088 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -154,22 +154,7 @@ static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
 	}
 }
 
-static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
-				       struct drm_display_mode *mode,
-				       struct drm_display_mode *adjusted_mode)
-{
-	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
-	struct sun4i_tcon *tcon = rgb->tcon;
-
-	sun4i_tcon0_mode_set(tcon, mode);
-	sun4i_tcon_set_mux(tcon, 0, encoder);
-
-	/* FIXME: This seems to be board specific */
-	clk_set_phase(tcon->dclk, 120);
-}
-
 static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
-	.mode_set	= sun4i_rgb_encoder_mode_set,
 	.disable	= sun4i_rgb_encoder_disable,
 	.enable		= sun4i_rgb_encoder_enable,
 };
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index dc70bc2a42a5..c4407910dfaf 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -106,29 +106,6 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 }
 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 
-void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
-			struct drm_encoder *encoder)
-{
-	u32 val;
-
-	if (!tcon->quirks->has_unknown_mux)
-		return;
-
-	if (channel != 1)
-		return;
-
-	if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
-		val = 1;
-	else
-		val = 0;
-
-	/*
-	 * FIXME: Undocumented bits
-	 */
-	regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
-}
-EXPORT_SYMBOL(sun4i_tcon_set_mux);
-
 static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
 				    int channel)
 {
@@ -147,8 +124,8 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
 	return delay;
 }
 
-void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
-			  struct drm_display_mode *mode)
+static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
+				 struct drm_display_mode *mode)
 {
 	unsigned int bp, hsync, vsync;
 	u8 clk_delay;
@@ -221,10 +198,9 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
 	/* Enable the output on the pins */
 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
 }
-EXPORT_SYMBOL(sun4i_tcon0_mode_set);
 
-void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
-			  struct drm_display_mode *mode)
+static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
+				 struct drm_display_mode *mode)
 {
 	unsigned int bp, hsync, vsync, vtotal;
 	u8 clk_delay;
@@ -312,7 +288,29 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
 			   SUN4I_TCON_GCTL_IOMAP_MASK,
 			   SUN4I_TCON_GCTL_IOMAP_TCON1);
 }
-EXPORT_SYMBOL(sun4i_tcon1_mode_set);
+
+void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
+			 struct drm_display_mode *mode)
+{
+	switch (encoder->encoder_type) {
+	case DRM_MODE_ENCODER_NONE:
+		sun4i_tcon0_mode_set(tcon, mode);
+		break;
+	case DRM_MODE_ENCODER_TVDAC:
+		/*
+		 * FIXME: Undocumented bits
+		 */
+		if (tcon->quirks->has_unknown_mux)
+			regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
+		/* Fallthrough */
+	case DRM_MODE_ENCODER_TMDS:
+		sun4i_tcon1_mode_set(tcon, mode);
+		break;
+	default:
+		DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
+	}
+}
+EXPORT_SYMBOL(sun4i_tcon_mode_set);
 
 static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
 					struct sun4i_crtc *scrtc)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 824732c90a2a..a318e5ccb612 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -184,15 +184,9 @@ struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
 struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
 
 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
+void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
+			 struct drm_display_mode *mode);
 void sun4i_tcon_set_status(struct sun4i_tcon *crtc, struct drm_encoder *encoder,
 			   bool enable);
 
-/* Mode Related Controls */
-void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
-			struct drm_encoder *encoder);
-void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
-			  struct drm_display_mode *mode);
-void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
-			  struct drm_display_mode *mode);
-
 #endif /* __SUN4I_TCON_H__ */
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 78d6cf77fdd3..69b9f8d98a13 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -24,7 +24,6 @@
 
 #include "sun4i_crtc.h"
 #include "sun4i_drv.h"
-#include "sun4i_tcon.h"
 #include "sunxi_engine.h"
 
 #define SUN4I_TVE_EN_REG		0x000
@@ -374,13 +373,8 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
 			      struct drm_display_mode *adjusted_mode)
 {
 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
-	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
-	struct sun4i_tcon *tcon = crtc->tcon;
 	const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
 
-	sun4i_tcon1_mode_set(tcon, mode);
-	sun4i_tcon_set_mux(tcon, 1, encoder);
-
 	/* Enable and map the DAC to the output */
 	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
 			   SUN4I_TVE_EN_DAC_MAP_MASK,
-- 
git-series 0.9.1

[PATCH 08/18] drm/sun4i: tcon: Add TRI finish interrupt for vblank

[Maxime Ripard]

The "CPU" (or Intel 8080) interface uses a different interrupt called
TRI_FINISH (most likely TRI being for trigger) to notify the end of frames,
and hence the VBLANK period.

And that interrupt to the possible VBLANK interrupts source.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  9 ++++++---
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  4 ++++
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c4407910dfaf..a3bbf9994cfa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -97,7 +97,8 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
 	DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
 
 	mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
-	       SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
+		SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
+		SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
 
 	if (enable)
 		val = mask;
@@ -336,7 +337,8 @@ static irqreturn_t sun4i_tcon_handler(int irq, void *private)
 	regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
 
 	if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
-			SUN4I_TCON_GINT0_VBLANK_INT(1))))
+			SUN4I_TCON_GINT0_VBLANK_INT(1) |
+			SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
 		return IRQ_NONE;
 
 	drm_crtc_handle_vblank(&scrtc->crtc);
@@ -345,7 +347,8 @@ static irqreturn_t sun4i_tcon_handler(int irq, void *private)
 	/* Acknowledge the interrupt */
 	regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
 			   SUN4I_TCON_GINT0_VBLANK_INT(0) |
-			   SUN4I_TCON_GINT0_VBLANK_INT(1),
+			   SUN4I_TCON_GINT0_VBLANK_INT(1) |
+			   SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
 			   0);
 
 	return IRQ_HANDLED;
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index a318e5ccb612..b3582ee82855 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -28,7 +28,11 @@
 
 #define SUN4I_TCON_GINT0_REG			0x4
 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)		BIT(31 - (pipe))
+#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE	BIT(27)
+#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE	BIT(26)
 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe)		BIT(15 - (pipe))
+#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT		BIT(11)
+#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT		BIT(10)
 
 #define SUN4I_TCON_GINT1_REG			0x8
 #define SUN4I_TCON_FRM_CTL_REG			0x10
-- 
git-series 0.9.1

[PATCH 09/18] drm/sun4i: tcon: Adjust dotclock dividers range

[Maxime Ripard]

It seems like the dotclock dividers are a bit less strict range, and can
operate even with a smaller than 6 divider. Loose the boundaries a bit.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index d401156490f3..0b844c0dd102 100644
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -77,7 +77,25 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
 	u8 best_div = 1;
 	int i;
 
-	for (i = 6; i <= 127; i++) {
+	/*
+	 * There's something odd here.
+	 *
+	 * In the A13 user manual, this is stated to be >= 6 when
+	 * dclk1 and dclk2 are used (without any hint on how to use
+	 * them), and >= 4 when only dclk is used.
+	 *
+	 * In the A33 user manual, when only dclk is used, it is set
+	 * to be >= 6 in the former case, and >= 1 in the
+	 * latter. There's also some (obscure) explanations about the
+	 * dclk1 and dclk2 vs dclk that seems to be in the upper 4
+	 * bits. What those clocks are and what bit does what is not
+	 * really clear.
+	 *
+	 * On the A33 however, while something lower than 4 works, it
+	 * does have a few artifacts. Let's not use those values, and
+	 * see how it goes.
+	 */
+	for (i = 4; i <= 127; i++) {
 		unsigned long ideal = rate * i;
 		unsigned long rounded;
 
-- 
git-series 0.9.1

[PATCH 10/18] drm/sun4i: tcon: Move out the tcon0 common setup

[Maxime Ripard]

Some channel0 setup has to be done, no matter what the output interface is
(RGB, CPU, LVDS). Move that code into a common function in order to avoid
duplication.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index a3bbf9994cfa..f051862d635e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -125,15 +125,26 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
 	return delay;
 }
 
-static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
-				 struct drm_display_mode *mode)
+static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
+					struct drm_display_mode *mode)
+{
+	/* Configure the dot clock */
+	clk_set_rate_protect(tcon->dclk, mode->crtc_clock * 1000);
+
+	/* Set the resolution */
+	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
+		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
+}
+
+static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
+				     struct drm_display_mode *mode)
 {
 	unsigned int bp, hsync, vsync;
 	u8 clk_delay;
 	u32 val = 0;
 
-	/* Configure the dot clock */
-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+	sun4i_tcon0_mode_set_common(tcon, mode);
 
 	/* Adjust clock delay */
 	clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
@@ -141,11 +152,6 @@ static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
 			   SUN4I_TCON0_CTL_CLK_DELAY_MASK,
 			   SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
 
-	/* Set the resolution */
-	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-		     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
-
 	/*
 	 * This is called a backporch in the register documentation,
 	 * but it really is the back porch + hsync
@@ -295,7 +301,7 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
 {
 	switch (encoder->encoder_type) {
 	case DRM_MODE_ENCODER_NONE:
-		sun4i_tcon0_mode_set(tcon, mode);
+		sun4i_tcon0_mode_set_rgb(tcon, mode);
 		break;
 	case DRM_MODE_ENCODER_TVDAC:
 		/*
-- 
git-series 0.9.1

[PATCH 11/18] dt-bindings: display: Add Allwinner MIPI-DSI bindings

[Maxime Ripard]

The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85 +++++++-
 1 file changed, 85 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
new file mode 100644
index 000000000000..2e7c5aa7020f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
@@ -0,0 +1,85 @@
+Allwinner A31 DSI Encoder
+=========================
+
+The DSI pipeline consists of two separate blocks: the DSI controller
+itself, and its associated D-PHY.
+
+DSI Encoder
+-----------
+
+The DSI Encoder generates the DSI signal from the TCON's.
+
+Required properties:
+  - compatible: value must be one of:
+    * allwinner,sun6i-a31-mipi-dsi
+  - reg: base address and size of memory-mapped region
+  - interrupts: interrupt associated to this IP
+  - clocks: phandles to the clocks feeding the DSI encoder
+    * bus: the DSI interface clock
+    * mod: the DSI module clock
+  - clock-names: the clock names mentioned above
+  - phys: phandle to the D-PHY
+  - phy-names: must be "dphy"
+  - resets: phandle to the reset controller driving the encoder
+
+  - ports: A ports node with endpoint definitions as defined in
+    Documentation/devicetree/bindings/media/video-interfaces.txt. The
+    port should be the input endpoint, usually coming from the
+    associated TCON.
+
+D-PHY
+-----
+
+Required properties:
+  - compatible: value must be one of:
+    * allwinner,sun6i-a31-mipi-dphy
+  - reg: base address and size of memory-mapped region
+  - clocks: phandles to the clocks feeding the DSI encoder
+    * bus: the DSI interface clock
+    * mod: the DSI module clock
+  - clock-names: the clock names mentioned above
+  - resets: phandle to the reset controller driving the encoder
+
+Example:
+
+dsi0: dsi@01ca0000 {
+	compatible = "allwinner,sun6i-a31-mipi-dsi";
+	reg = <0x01ca0000 0x1000>;
+	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&ccu CLK_BUS_MIPI_DSI>,
+		 <&ccu CLK_DSI_SCLK>;
+	clock-names = "bus", "mod";
+	resets = <&ccu RST_BUS_MIPI_DSI>;
+	phys = <&dphy0>;
+	phy-names = "dphy";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dsi0_in: port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			dsi0_in_tcon0: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&tcon0_out_dsi0>;
+			};
+		};
+	};
+};
+
+dphy0: d-phy@01ca1000 {
+	compatible = "allwinner,sun6i-a31-mipi-dphy";
+	reg = <0x01ca1000 0x1000>;
+	clocks = <&ccu CLK_BUS_MIPI_DSI>,
+		 <&ccu CLK_DSI_DPHY>;
+	clock-names = "bus", "mod";
+	resets = <&ccu RST_BUS_MIPI_DSI>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	#phy-cells = <0>;
+};
-- 
git-series 0.9.1

[PATCH 12/18] drm/sun4i: Add Allwinner A31 MIPI-DSI controller support

[Maxime Ripard]

Most of the Allwinner SoCs since the A31 share the same MIPI-DSI
controller.

While that controller is mostly undocumented, the code is out there and has
been cleaned up in order to be integrated into DRM. However, there's still
some dark areas that are a bit unclear about how the block exactly
operates.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/sun4i/Kconfig           |   10 +-
 drivers/gpu/drm/sun4i/Makefile          |    5 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c      |   99 ++-
 drivers/gpu/drm/sun4i/sun4i_tcon.h      |   42 +-
 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c |  297 ++++++-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c  | 1098 ++++++++++++++++++++++++-
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h  |   67 +-
 7 files changed, 1617 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
 create mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
 create mode 100644 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h

diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 5cc116692913..76a157168003 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -31,6 +31,16 @@ config DRM_SUN4I_BACKEND
 	  do some alpha blending and feed graphics to TCON. If M is
 	  selected the module will be called sun4i-backend.
 
+config DRM_SUN6I_DSI
+	tristate "Allwinner A31 MIPI-DSI Controller Support"
+	default MACH_SUN8I
+	select CRC_CCITT
+	select DRM_MIPI_DSI
+	help
+	  Choose this option if you want have an Allwinner SoC with
+	  MIPI-DSI support. If M is selected the module will be called
+	  sun6i-dsi
+
 config DRM_SUN8I_MIXER
 	tristate "Support for Allwinner Display Engine 2.0 Mixer"
 	default MACH_SUN8I
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 42871ee7acf6..b93536ef701a 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -12,12 +12,15 @@ sun4i-tcon-y			+= sun4i_rgb.o
 sun4i-tcon-y			+= sun4i_dotclock.o
 sun4i-tcon-y			+= sun4i_crtc.o
 
+sun6i-dsi-y			+= sun6i_mipi_dphy.o
+sun6i-dsi-y			+= sun6i_mipi_dsi.o
+
 sun8i-mixer-y			+= sun8i_mixer.o sun8i_layer.o
 
 obj-$(CONFIG_DRM_SUN4I)		+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)		+= sun6i_drc.o
 obj-$(CONFIG_DRM_SUN4I)		+= sun4i_tv.o
-
 obj-$(CONFIG_DRM_SUN4I_BACKEND)	+= sun4i-backend.o
 obj-$(CONFIG_DRM_SUN4I_HDMI)	+= sun4i-drm-hdmi.o
+obj-$(CONFIG_DRM_SUN6I_DSI)	+= sun6i-dsi.o
 obj-$(CONFIG_DRM_SUN8I_MIXER)	+= sun8i-mixer.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index f051862d635e..d11bc9e0d39d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -31,6 +31,7 @@
 #include "sun4i_drv.h"
 #include "sun4i_rgb.h"
 #include "sun4i_tcon.h"
+#include "sun6i_mipi_dsi.h"
 #include "sunxi_engine.h"
 
 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
@@ -70,6 +71,7 @@ void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
 	int channel;
 
 	switch (encoder->encoder_type) {
+	case DRM_MODE_ENCODER_DSI:
 	case DRM_MODE_ENCODER_NONE:
 		channel = 0;
 		break;
@@ -125,6 +127,29 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
 	return delay;
 }
 
+static void sun4i_tcon0_frame_control_enable(struct sun4i_tcon *tcon)
+{
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_SEED_PR_REG, 1);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_SEED_PG_REG, 3);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_SEED_PB_REG, 5);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_SEED_LR_REG, 7);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_SEED_LG_REG, 11);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_SEED_LB_REG, 13);
+
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_TBL0_REG, 0x01010000);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_TBL1_REG, 0x15151111);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_TBL2_REG, 0x57575555);
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_TBL3_REG, 0x7f7f7777);
+
+	/*
+	 * FIXME: This seems to only be the case for RGB666, but it's
+	 * not clear when the TCON should be setup to something
+	 * different
+	 */
+	regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG,
+		     SUN4I_TCON_FRM_CTL_EN);
+}
+
 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
 					struct drm_display_mode *mode)
 {
@@ -137,6 +162,70 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
 		     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
 }
 
+static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+				     struct mipi_dsi_device *device,
+				     struct drm_display_mode *mode)
+{
+	u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
+	u8 lanes = device->lanes;
+	u32 block_space, start_delay;
+	u32 tcon_div;
+
+	sun4i_tcon0_mode_set_common(tcon, mode);
+
+	regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
+			   SUN4I_TCON0_CTL_IF_MASK,
+			   SUN4I_TCON0_CTL_IF_8080);
+
+	regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
+		     SUN4I_TCON_ECC_FIFO_EN);
+
+	regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
+		     SUN4I_TCON0_CPU_IF_MODE_DSI |
+		     SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH |
+		     SUN4I_TCON0_CPU_IF_TRI_FIFO_EN |
+		     SUN4I_TCON0_CPU_IF_TRI_EN);
+
+	/*
+	 * This looks suspicious, but it works...
+	 *
+	 * The datasheet says that this should be set higher than 20 *
+	 * pixel cycle, but it's not clear what a pixel cycle is.
+	 */
+	regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
+	tcon_div &= GENMASK(6, 0);
+	block_space = mode->htotal * bpp / (tcon_div * lanes);
+	block_space -= mode->hdisplay + 40;
+
+	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
+		     SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) |
+		     SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay));
+
+	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
+		     SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay));
+
+	start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1);
+	start_delay = start_delay * mode->crtc_htotal * 149;
+	start_delay = start_delay / (mode->crtc_clock / 1000) / 8;
+	regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
+		     SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
+		     SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay));
+
+	sun4i_tcon0_frame_control_enable(tcon);
+
+	/*
+	 * The Allwinner BSP has a comment that the period should be
+	 * the display clock * 15, but uses an hardcoded 3000...
+	 */
+	regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
+		     SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
+		     SUN4I_TCON_SAFE_PERIOD_MODE(3));
+
+	/* Enable the output on the pins */
+	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
+		     0xe0000000);
+}
+
 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
 				     struct drm_display_mode *mode)
 {
@@ -299,7 +388,17 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
 			 struct drm_display_mode *mode)
 {
+	struct sun6i_dsi *dsi;
+
 	switch (encoder->encoder_type) {
+	case DRM_MODE_ENCODER_DSI:
+		/*
+		 * This is not really elegant, but it's the "cleaner"
+		 * way I could think of...
+		 */
+		dsi = encoder_to_sun6i_dsi(encoder);
+		sun4i_tcon0_mode_set_cpu(tcon, dsi->device, mode);
+		break;
 	case DRM_MODE_ENCODER_NONE:
 		sun4i_tcon0_mode_set_rgb(tcon, mode);
 		break;
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index b3582ee82855..8f79de891c71 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -35,10 +35,25 @@
 #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT		BIT(10)
 
 #define SUN4I_TCON_GINT1_REG			0x8
+
 #define SUN4I_TCON_FRM_CTL_REG			0x10
+#define SUN4I_TCON_FRM_CTL_EN				BIT(31)
+
+#define SUN4I_TCON_FRM_SEED_PR_REG		0x14
+#define SUN4I_TCON_FRM_SEED_PG_REG		0x18
+#define SUN4I_TCON_FRM_SEED_PB_REG		0x1c
+#define SUN4I_TCON_FRM_SEED_LR_REG		0x20
+#define SUN4I_TCON_FRM_SEED_LG_REG		0x24
+#define SUN4I_TCON_FRM_SEED_LB_REG		0x28
+#define SUN4I_TCON_FRM_TBL0_REG			0x2c
+#define SUN4I_TCON_FRM_TBL1_REG			0x30
+#define SUN4I_TCON_FRM_TBL2_REG			0x34
+#define SUN4I_TCON_FRM_TBL3_REG			0x38
 
 #define SUN4I_TCON0_CTL_REG			0x40
 #define SUN4I_TCON0_CTL_TCON_ENABLE			BIT(31)
+#define SUN4I_TCON0_CTL_IF_MASK				GENMASK(25, 24)
+#define SUN4I_TCON0_CTL_IF_8080				(1 << 24)
 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
 #define SUN4I_TCON0_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
 
@@ -64,7 +79,14 @@
 #define SUN4I_TCON0_BASIC3_V_SYNC(height)		(((height) - 1) & 0x7ff)
 
 #define SUN4I_TCON0_HV_IF_REG			0x58
+
 #define SUN4I_TCON0_CPU_IF_REG			0x60
+#define SUN4I_TCON0_CPU_IF_MODE_MASK			GENMASK(31, 28)
+#define SUN4I_TCON0_CPU_IF_MODE_DSI			(1 << 28)
+#define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH		BIT(16)
+#define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN			BIT(2)
+#define SUN4I_TCON0_CPU_IF_TRI_EN			BIT(0)
+
 #define SUN4I_TCON0_CPU_WR_REG			0x64
 #define SUN4I_TCON0_CPU_RD0_REG			0x68
 #define SUN4I_TCON0_CPU_RDA_REG			0x6c
@@ -116,6 +138,10 @@
 
 #define SUN4I_TCON1_IO_POL_REG			0xf0
 #define SUN4I_TCON1_IO_TRI_REG			0xf4
+
+#define SUN4I_TCON_ECC_FIFO_REG			0xf8
+#define SUN4I_TCON_ECC_FIFO_EN				BIT(3)
+
 #define SUN4I_TCON_CEU_CTL_REG			0x100
 #define SUN4I_TCON_CEU_MUL_RR_REG		0x110
 #define SUN4I_TCON_CEU_MUL_RG_REG		0x114
@@ -132,6 +158,22 @@
 #define SUN4I_TCON_CEU_RANGE_R_REG		0x140
 #define SUN4I_TCON_CEU_RANGE_G_REG		0x144
 #define SUN4I_TCON_CEU_RANGE_B_REG		0x148
+
+#define SUN4I_TCON0_CPU_TRI0_REG		0x160
+#define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space)		((((space) - 1) & 0xfff) << 16)
+#define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size)		(((size) - 1) & 0xfff)
+
+#define SUN4I_TCON0_CPU_TRI1_REG		0x164
+#define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num)		(((num) - 1) & 0xffff)
+
+#define SUN4I_TCON0_CPU_TRI2_REG		0x168
+#define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay)		(((delay) & 0xffff) << 16)
+#define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set)	((set) & 0xfff)
+
+#define SUN4I_TCON_SAFE_PERIOD_REG		0x1f0
+#define SUN4I_TCON_SAFE_PERIOD_NUM(num)			(((num) & 0xfff) << 16)
+#define SUN4I_TCON_SAFE_PERIOD_MODE(mode)		((mode) & 0x3)
+
 #define SUN4I_TCON_MUX_CTRL_REG			0x200
 #define SUN4I_TCON1_FILL_CTL_REG		0x300
 #define SUN4I_TCON1_FILL_BEG0_REG		0x304
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
new file mode 100644
index 000000000000..a7a73084c745
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+ * Copyright (C) 2017 Free Electrons
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include "sun6i_mipi_dsi.h"
+
+#define SUN6I_DPHY_GCTL_REG		0x00
+#define SUN6I_DPHY_GCTL_LANE_NUM(n)		((((n) - 1) & 3) << 4)
+#define SUN6I_DPHY_GCTL_EN			BIT(0)
+
+#define SUN6I_DPHY_TX_CTL_REG		0x04
+#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT	BIT(28)
+
+#define SUN6I_DPHY_TX_TIME0_REG		0x10
+#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)		(((n) & 0xff) << 24)
+#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n)	(((n) & 0xff) << 16)
+#define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n)	((n) & 0xff)
+
+#define SUN6I_DPHY_TX_TIME1_REG		0x14
+#define SUN6I_DPHY_TX_TIME1_CLK_POST(n)		(((n) & 0xff) << 24)
+#define SUN6I_DPHY_TX_TIME1_CLK_PRE(n)		(((n) & 0xff) << 16)
+#define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n)		(((n) & 0xff) << 8)
+#define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n)	((n) & 0xff)
+
+#define SUN6I_DPHY_TX_TIME2_REG		0x18
+#define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n)	((n) & 0xff)
+
+#define SUN6I_DPHY_TX_TIME3_REG		0x1c
+
+#define SUN6I_DPHY_TX_TIME4_REG		0x20
+#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n)	(((n) & 0xff) << 8)
+#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n)	((n) & 0xff)
+
+#define SUN6I_DPHY_ANA0_REG		0x4c
+#define SUN6I_DPHY_ANA0_REG_PWS			BIT(31)
+#define SUN6I_DPHY_ANA0_REG_DMPC		BIT(28)
+#define SUN6I_DPHY_ANA0_REG_DMPD(n)		(((n) & 0xf) << 24)
+#define SUN6I_DPHY_ANA0_REG_SLV(n)		(((n) & 7) << 12)
+#define SUN6I_DPHY_ANA0_REG_DEN(n)		(((n) & 0xf) << 8)
+
+#define SUN6I_DPHY_ANA1_REG		0x50
+#define SUN6I_DPHY_ANA1_REG_VTTMODE		BIT(31)
+#define SUN6I_DPHY_ANA1_REG_CSMPS(n)		(((n) & 3) << 28)
+#define SUN6I_DPHY_ANA1_REG_SVTT(n)		(((n) & 0xf) << 24)
+
+#define SUN6I_DPHY_ANA2_REG		0x54
+#define SUN6I_DPHY_ANA2_EN_P2S_CPU(n)		(((n) & 0xf) << 24)
+#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK		GENMASK(27, 24)
+#define SUN6I_DPHY_ANA2_EN_CK_CPU		BIT(4)
+#define SUN6I_DPHY_ANA2_REG_ENIB		BIT(1)
+
+#define SUN6I_DPHY_ANA3_REG		0x58
+#define SUN6I_DPHY_ANA3_EN_VTTD(n)		(((n) & 0xf) << 28)
+#define SUN6I_DPHY_ANA3_EN_VTTD_MASK		GENMASK(31, 28)
+#define SUN6I_DPHY_ANA3_EN_VTTC			BIT(27)
+#define SUN6I_DPHY_ANA3_EN_DIV			BIT(26)
+#define SUN6I_DPHY_ANA3_EN_LDOC			BIT(25)
+#define SUN6I_DPHY_ANA3_EN_LDOD			BIT(24)
+#define SUN6I_DPHY_ANA3_EN_LDOR			BIT(18)
+
+#define SUN6I_DPHY_ANA4_REG		0x5c
+#define SUN6I_DPHY_ANA4_REG_DMPLVC		BIT(24)
+#define SUN6I_DPHY_ANA4_REG_DMPLVD(n)		(((n) & 0xf) << 20)
+#define SUN6I_DPHY_ANA4_REG_CKDV(n)		(((n) & 0x1f) << 12)
+#define SUN6I_DPHY_ANA4_REG_TMSC(n)		(((n) & 3) << 10)
+#define SUN6I_DPHY_ANA4_REG_TMSD(n)		(((n) & 3) << 8)
+#define SUN6I_DPHY_ANA4_REG_TXDNSC(n)		(((n) & 3) << 6)
+#define SUN6I_DPHY_ANA4_REG_TXDNSD(n)		(((n) & 3) << 4)
+#define SUN6I_DPHY_ANA4_REG_TXPUSC(n)		(((n) & 3) << 2)
+#define SUN6I_DPHY_ANA4_REG_TXPUSD(n)		((n) & 3)
+
+#define SUN6I_DPHY_DBG5_REG		0xf4
+
+int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes)
+{
+	reset_control_deassert(dphy->reset);
+	clk_prepare_enable(dphy->mod_clk);
+	clk_set_rate_protect(dphy->mod_clk, 150000000);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
+		     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
+		     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
+		     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
+		     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
+		     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
+		     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
+		     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
+		     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
+		     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
+		     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
+
+	/* FIXME: Number of lanes? */
+	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
+		     SUN6I_DPHY_GCTL_LANE_NUM(lanes) |
+		     SUN6I_DPHY_GCTL_EN);
+
+	return 0;
+}
+
+int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes)
+{
+	u8 lanes_mask = GENMASK(lanes - 1, 0);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+		     SUN6I_DPHY_ANA0_REG_PWS |
+		     SUN6I_DPHY_ANA0_REG_DMPC |
+		     SUN6I_DPHY_ANA0_REG_SLV(7) |
+		     SUN6I_DPHY_ANA0_REG_DMPD(lanes_mask) |
+		     SUN6I_DPHY_ANA0_REG_DEN(lanes_mask));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
+		     SUN6I_DPHY_ANA1_REG_CSMPS(1) |
+		     SUN6I_DPHY_ANA1_REG_SVTT(7));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
+		     SUN6I_DPHY_ANA4_REG_CKDV(1) |
+		     SUN6I_DPHY_ANA4_REG_TMSC(1) |
+		     SUN6I_DPHY_ANA4_REG_TMSD(1) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSC(1) |
+		     SUN6I_DPHY_ANA4_REG_TXDNSD(1) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSC(1) |
+		     SUN6I_DPHY_ANA4_REG_TXPUSD(1) |
+		     SUN6I_DPHY_ANA4_REG_DMPLVC |
+		     SUN6I_DPHY_ANA4_REG_DMPLVD(lanes_mask));
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
+		     SUN6I_DPHY_ANA2_REG_ENIB);
+	udelay(5);
+
+	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
+		     SUN6I_DPHY_ANA3_EN_LDOR |
+		     SUN6I_DPHY_ANA3_EN_LDOC |
+		     SUN6I_DPHY_ANA3_EN_LDOD);
+	udelay(1);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
+			   SUN6I_DPHY_ANA3_EN_VTTC |
+			   SUN6I_DPHY_ANA3_EN_VTTD_MASK,
+			   SUN6I_DPHY_ANA3_EN_VTTC |
+			   SUN6I_DPHY_ANA3_EN_VTTD(lanes_mask));
+	udelay(1);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
+			   SUN6I_DPHY_ANA3_EN_DIV,
+			   SUN6I_DPHY_ANA3_EN_DIV);
+	udelay(1);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU,
+			   SUN6I_DPHY_ANA2_EN_CK_CPU);
+	udelay(1);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
+			   SUN6I_DPHY_ANA1_REG_VTTMODE,
+			   SUN6I_DPHY_ANA1_REG_VTTMODE);
+
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
+			   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
+			   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
+
+	return 0;
+}
+
+int sun6i_dphy_power_off(struct sun6i_dphy *dphy)
+{
+	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
+			   SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
+
+	return 0;
+}
+
+int sun6i_dphy_exit(struct sun6i_dphy *dphy)
+{
+	clk_rate_unprotect(dphy->mod_clk);
+	clk_disable_unprepare(dphy->mod_clk);
+	reset_control_assert(dphy->reset);
+
+	return 0;
+}
+
+static struct regmap_config sun6i_dphy_regmap_config = {
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= SUN6I_DPHY_DBG5_REG,
+	.name		= "mipi-dphy",
+};
+
+static const struct of_device_id sun6i_dphy_of_table[] = {
+	{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
+	{ }
+};
+
+int sun6i_dphy_probe(struct sun6i_dsi *dsi, struct device_node *node)
+{
+	struct sun6i_dphy *dphy;
+	struct resource res;
+	void __iomem *regs;
+	int ret;
+
+	if (!of_match_node(sun6i_dphy_of_table, node)) {
+		dev_err(dsi->dev, "Incompatible D-PHY\n");
+		return -EINVAL;
+	}
+
+	dphy = devm_kzalloc(dsi->dev, sizeof(*dphy), GFP_KERNEL);
+	if (!dphy)
+		return -ENOMEM;
+
+	ret = of_address_to_resource(node, 0, &res);
+	if (ret) {
+		dev_err(dsi->dev, "phy: Couldn't get our resources\n");
+		return ret;
+	}
+
+	regs = devm_ioremap_resource(dsi->dev, &res);
+	if (IS_ERR(regs)) {
+		dev_err(dsi->dev, "Couldn't map the DPHY encoder registers\n");
+		return PTR_ERR(regs);
+	}
+
+	dphy->regs = devm_regmap_init_mmio(dsi->dev, regs,
+					   &sun6i_dphy_regmap_config);
+	if (IS_ERR(dphy->regs)) {
+		dev_err(dsi->dev, "Couldn't create the DPHY encoder regmap\n");
+		return PTR_ERR(dphy->regs);
+	}
+
+	dphy->reset = of_reset_control_get_shared(node, NULL);
+	if (IS_ERR(dphy->reset)) {
+		dev_err(dsi->dev, "Couldn't get our reset line\n");
+		return PTR_ERR(dphy->reset);
+	}
+
+	dphy->bus_clk = of_clk_get_by_name(node, "bus");
+	if (IS_ERR(dphy->bus_clk)) {
+		dev_err(dsi->dev, "Couldn't get the DPHY bus clock\n");
+		ret = PTR_ERR(dphy->bus_clk);
+		goto err_free_reset;
+	}
+	regmap_mmio_attach_clk(dphy->regs, dphy->bus_clk);
+
+	dphy->mod_clk = of_clk_get_by_name(node, "mod");
+	if (IS_ERR(dphy->mod_clk)) {
+		dev_err(dsi->dev, "Couldn't get the DPHY mod clock\n");
+		ret = PTR_ERR(dphy->mod_clk);
+		goto err_free_bus;
+	}
+
+	dsi->dphy = dphy;
+
+	return 0;
+
+err_free_bus:
+	regmap_mmio_detach_clk(dphy->regs);
+	clk_put(dphy->bus_clk);
+err_free_reset:
+	reset_control_put(dphy->reset);
+	return ret;
+}
+
+int sun6i_dphy_remove(struct sun6i_dsi *dsi)
+{
+	struct sun6i_dphy *dphy = dsi->dphy;
+
+	regmap_mmio_detach_clk(dphy->regs);
+	clk_put(dphy->mod_clk);
+	clk_put(dphy->bus_clk);
+	reset_control_put(dphy->reset);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
new file mode 100644
index 000000000000..3da3f7c060e5
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -0,0 +1,1098 @@
+/*
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+ * Copyright (C) 2017 Free Electrons
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/crc-ccitt.h>
+#include <linux/of_address.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <linux/phy/phy.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include "sun4i_drv.h"
+#include "sun6i_mipi_dsi.h"
+
+#include <video/mipi_display.h>
+
+#define SUN6I_DSI_CTL_REG		0x000
+#define SUN6I_DSI_CTL_EN			BIT(0)
+
+#define SUN6I_DSI_BASIC_CTL_REG		0x00c
+#define SUN6I_DSI_BASIC_CTL_HBP_DIS		BIT(2)
+#define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS		BIT(1)
+#define SUN6I_DSI_BASIC_CTL_VIDEO_BURST		BIT(0)
+
+#define SUN6I_DSI_BASIC_CTL0_REG	0x010
+#define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN		BIT(18)
+#define SUN6I_DSI_BASIC_CTL0_CRC_EN		BIT(17)
+#define SUN6I_DSI_BASIC_CTL0_ECC_EN		BIT(16)
+#define SUN6I_DSI_BASIC_CTL0_INST_ST		BIT(0)
+
+#define SUN6I_DSI_BASIC_CTL1_REG	0x014
+#define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n)	(((n) & 0x1fff) << 4)
+#define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL		BIT(2)
+#define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION	BIT(1)
+#define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE		BIT(0)
+
+#define SUN6I_DSI_BASIC_SIZE0_REG	0x018
+#define SUN6I_DSI_BASIC_SIZE0_VBP(n)		(((n) & 0xfff) << 16)
+#define SUN6I_DSI_BASIC_SIZE0_VSA(n)		((n) & 0xfff)
+
+#define SUN6I_DSI_BASIC_SIZE1_REG	0x01c
+#define SUN6I_DSI_BASIC_SIZE1_VT(n)		(((n) & 0xfff) << 16)
+#define SUN6I_DSI_BASIC_SIZE1_VACT(n)		((n) & 0xfff)
+
+#define SUN6I_DSI_INST_FUNC_REG(n)	(0x020 + (n) * 0x04)
+#define SUN6I_DSI_INST_FUNC_INST_MODE(n)	(((n) & 0xf) << 28)
+#define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n)	(((n) & 0xf) << 24)
+#define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n)	(((n) & 0xf) << 20)
+#define SUN6I_DSI_INST_FUNC_LANE_CEN		BIT(4)
+#define SUN6I_DSI_INST_FUNC_LANE_DEN(n)		((n) & 0xf)
+
+#define SUN6I_DSI_INST_LOOP_SEL_REG	0x040
+
+#define SUN6I_DSI_INST_LOOP_NUM_REG(n)	(0x044 + (n) * 0x10)
+#define SUN6I_DSI_INST_LOOP_NUM_N1(n)		(((n) & 0xfff) << 16)
+#define SUN6I_DSI_INST_LOOP_NUM_N0(n)		((n) & 0xfff)
+
+#define SUN6I_DSI_INST_JUMP_SEL_REG	0x048
+
+#define SUN6I_DSI_INST_JUMP_CFG_REG(n)	(0x04c + (n) * 0x04)
+#define SUN6I_DSI_INST_JUMP_CFG_TO(n)		(((n) & 0xf) << 20)
+#define SUN6I_DSI_INST_JUMP_CFG_POINT(n)	(((n) & 0xf) << 16)
+#define SUN6I_DSI_INST_JUMP_CFG_NUM(n)		((n) & 0xffff)
+
+#define SUN6I_DSI_TRANS_START_REG	0x060
+
+#define SUN6I_DSI_TRANS_ZERO_REG	0x078
+
+#define SUN6I_DSI_TCON_DRQ_REG		0x07c
+#define SUN6I_DSI_TCON_DRQ_ENABLE_MODE		BIT(28)
+#define SUN6I_DSI_TCON_DRQ_SET(n)		((n) & 0x3ff)
+
+#define SUN6I_DSI_PIXEL_CTL0_REG	0x080
+#define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE	BIT(16)
+#define SUN6I_DSI_PIXEL_CTL0_FORMAT(n)		((n) & 0xf)
+
+#define SUN6I_DSI_PIXEL_CTL1_REG	0x084
+
+#define SUN6I_DSI_PIXEL_PH_REG		0x090
+#define SUN6I_DSI_PIXEL_PH_ECC(n)		(((n) & 0xff) << 24)
+#define SUN6I_DSI_PIXEL_PH_WC(n)		(((n) & 0xffff) << 8)
+#define SUN6I_DSI_PIXEL_PH_VC(n)		(((n) & 3) << 6)
+#define SUN6I_DSI_PIXEL_PH_DT(n)		((n) & 0x3f)
+
+#define SUN6I_DSI_PIXEL_PF0_REG		0x098
+#define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n)	((n) & 0xffff)
+
+#define SUN6I_DSI_PIXEL_PF1_REG		0x09c
+#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n)	(((n) & 0xffff) << 16)
+#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n)	((n) & 0xffff)
+
+#define SUN6I_DSI_SYNC_HSS_REG		0x0b0
+
+#define SUN6I_DSI_SYNC_HSE_REG		0x0b4
+
+#define SUN6I_DSI_SYNC_VSS_REG		0x0b8
+
+#define SUN6I_DSI_SYNC_VSE_REG		0x0bc
+
+#define SUN6I_DSI_BLK_HSA0_REG		0x0c0
+
+#define SUN6I_DSI_BLK_HSA1_REG		0x0c4
+#define SUN6I_DSI_BLK_PF(n)			(((n) & 0xffff) << 16)
+#define SUN6I_DSI_BLK_PD(n)			((n) & 0xff)
+
+#define SUN6I_DSI_BLK_HBP0_REG		0x0c8
+
+#define SUN6I_DSI_BLK_HBP1_REG		0x0cc
+
+#define SUN6I_DSI_BLK_HFP0_REG		0x0d0
+
+#define SUN6I_DSI_BLK_HFP1_REG		0x0d4
+
+#define SUN6I_DSI_BLK_HBLK0_REG		0x0e0
+
+#define SUN6I_DSI_BLK_HBLK1_REG		0x0e4
+
+#define SUN6I_DSI_BLK_VBLK0_REG		0x0e8
+
+#define SUN6I_DSI_BLK_VBLK1_REG		0x0ec
+
+#define SUN6I_DSI_BURST_LINE_REG	0x0f0
+#define SUN6I_DSI_BURST_LINE_SYNC_POINT(n)	(((n) & 0xffff) << 16)
+#define SUN6I_DSI_BURST_LINE_NUM(n)		((n) & 0xffff)
+
+#define SUN6I_DSI_BURST_DRQ_REG		0x0f4
+#define SUN6I_DSI_BURST_DRQ_EDGE1(n)		(((n) & 0xffff) << 16)
+#define SUN6I_DSI_BURST_DRQ_EDGE0(n)		((n) & 0xffff)
+
+#define SUN6I_DSI_CMD_CTL_REG		0x200
+#define SUN6I_DSI_CMD_CTL_RX_OVERFLOW		BIT(26)
+#define SUN6I_DSI_CMD_CTL_RX_FLAG		BIT(25)
+#define SUN6I_DSI_CMD_CTL_TX_FLAG		BIT(9)
+
+#define SUN6I_DSI_CMD_RX_REG(n)		(0x240 + (n) * 0x04)
+
+#define SUN6I_DSI_DEBUG_DATA_REG	0x2f8
+
+#define SUN6I_DSI_CMD_TX_REG(n)		(0x300 + (n) * 0x04)
+
+enum sun6i_dsi_start_inst {
+	DSI_START_LPRX,
+	DSI_START_LPTX,
+	DSI_START_HSC,
+	DSI_START_HSD,
+};
+
+enum sun6i_dsi_inst_id {
+	DSI_INST_ID_LP11	= 0,
+	DSI_INST_ID_TBA,
+	DSI_INST_ID_HSC,
+	DSI_INST_ID_HSD,
+	DSI_INST_ID_LPDT,
+	DSI_INST_ID_HSCEXIT,
+	DSI_INST_ID_NOP,
+	DSI_INST_ID_DLY,
+	DSI_INST_ID_END		= 15,
+};
+
+enum sun6i_dsi_inst_mode {
+	DSI_INST_MODE_STOP	= 0,
+	DSI_INST_MODE_TBA,
+	DSI_INST_MODE_HS,
+	DSI_INST_MODE_ESCAPE,
+	DSI_INST_MODE_HSCEXIT,
+	DSI_INST_MODE_NOP,
+};
+
+enum sun6i_dsi_inst_escape {
+	DSI_INST_ESCA_LPDT	= 0,
+	DSI_INST_ESCA_ULPS,
+	DSI_INST_ESCA_UN1,
+	DSI_INST_ESCA_UN2,
+	DSI_INST_ESCA_RESET,
+	DSI_INST_ESCA_UN3,
+	DSI_INST_ESCA_UN4,
+	DSI_INST_ESCA_UN5,
+};
+
+enum sun6i_dsi_inst_packet {
+	DSI_INST_PACK_PIXEL	= 0,
+	DSI_INST_PACK_COMMAND,
+};
+
+static u32 sun6i_dsi_ecc_array[] = {
+	[0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
+	       BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
+	       BIT(23)),
+	[1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
+	       BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
+	       BIT(23)),
+	[2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
+	       BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
+	[3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
+	       BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
+	[4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
+	       BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
+	[5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
+	       BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
+	       BIT(23)),
+};
+
+static u32 sun6i_dsi_ecc_compute(unsigned int data)
+{
+	int i;
+	u8 ecc = 0;
+
+	for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
+		u32 field = sun6i_dsi_ecc_array[i];
+		bool init = false;
+		u8 val = 0;
+		int j;
+
+		for (j = 0; j < 24; j++) {
+			if (!(BIT(j) & field))
+				continue;
+
+			if (!init) {
+				val = (BIT(j) & data) ? 1 : 0;
+				init = true;
+			} else {
+				val ^= (BIT(j) & data) ? 1 : 0;
+			}
+		}
+
+		ecc |= val << i;
+	}
+
+	return ecc;
+}
+
+static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
+{
+	return crc_ccitt(0xffff, buffer, len);
+}
+
+static u16 sun6i_dsi_crc_repeat_compute(u8 pd, size_t len)
+{
+	u8 buffer[len];
+
+	memset(buffer, pd, len);
+
+	return sun6i_dsi_crc_compute(buffer, len);
+}
+
+static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
+{
+	u32 val = dt & 0x3f;
+
+	val |= (vc & 3) << 6;
+	val |= (d0 & 0xff) << 8;
+	val |= (d1 & 0xff) << 16;
+	val |= sun6i_dsi_ecc_compute(val) << 24;
+
+	return val;
+}
+
+static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
+{
+	return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
+					wc & 0xff, wc >> 8);
+}
+
+static u32 sun6i_dsi_build_blk1_pkt(u16 pd, size_t len)
+{
+	u32 val = SUN6I_DSI_BLK_PD(pd);
+
+	return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat_compute(pd, len));
+}
+
+static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
+{
+	regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
+			   SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
+}
+
+static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
+{
+	regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
+			   SUN6I_DSI_BASIC_CTL0_INST_ST,
+			   SUN6I_DSI_BASIC_CTL0_INST_ST);
+}
+
+static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
+{
+	u32 val;
+
+	return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
+					val,
+					!(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
+					100, 5000);
+}
+
+static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
+				 enum sun6i_dsi_inst_id id,
+				 enum sun6i_dsi_inst_mode mode,
+				 bool clock, u8 data,
+				 enum sun6i_dsi_inst_packet packet,
+				 enum sun6i_dsi_inst_escape escape)
+{
+	regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
+		     SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
+		     SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
+		     SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
+		     (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
+		     SUN6I_DSI_INST_FUNC_LANE_DEN(data));
+}
+
+static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
+				struct mipi_dsi_device *device)
+{
+	u8 lanes_mask = GENMASK(device->lanes - 1, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
+			     true, lanes_mask, 0, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
+			     false, 1, 0, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
+			     true, 0, DSI_INST_PACK_PIXEL, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
+			     false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
+			     false, 1, DSI_INST_PACK_COMMAND,
+			     DSI_INST_ESCA_LPDT);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
+			     true, 0, 0, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
+			     false, lanes_mask, 0, 0);
+
+	sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
+			     true, lanes_mask, 0, 0);
+
+	regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
+		     SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
+		     SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
+		     SUN6I_DSI_INST_JUMP_CFG_NUM(1));
+};
+
+static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
+					   struct drm_display_mode *mode)
+{
+	return mode->vtotal - (mode->vsync_end - mode->vdisplay) + 1;
+}
+
+static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
+				  struct drm_display_mode *mode)
+{
+	struct mipi_dsi_device *device = dsi->device;
+	u32 val = 0;
+
+	if ((mode->hsync_end - mode->hdisplay) > 20) {
+		/* Maaaaaagic */
+		u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
+
+		drq *= mipi_dsi_pixel_format_to_bpp(device->format);
+		drq /= 32;
+
+		val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
+		       SUN6I_DSI_TCON_DRQ_SET(drq));
+	}
+
+	regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
+}
+
+static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
+				      struct drm_display_mode *mode)
+{
+	u16 delay = 50 - 1;
+
+	regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
+		     SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
+		     SUN6I_DSI_INST_LOOP_NUM_N1(delay));
+	regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
+		     SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
+		     SUN6I_DSI_INST_LOOP_NUM_N1(delay));
+}
+
+static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
+				   struct drm_display_mode *mode)
+{
+	struct mipi_dsi_device *device = dsi->device;
+	u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
+	u8 dt, fmt;
+	u16 wc;
+
+	/*
+	 * TODO: The format defines are only valid in video mode and
+	 * change in command mode.
+	 */
+	switch (device->format) {
+	case MIPI_DSI_FMT_RGB888:
+		dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
+		fmt = 8;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
+		fmt = 9;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
+		fmt = 10;
+		break;
+	case MIPI_DSI_FMT_RGB565:
+		dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
+		fmt = 11;
+		break;
+	default:
+		return;
+	}
+	val |= SUN6I_DSI_PIXEL_PH_DT(dt);
+
+	wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
+	val |= SUN6I_DSI_PIXEL_PH_WC(wc);
+	val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
+
+	regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
+
+	regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
+		     SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
+
+	regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
+		     SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
+		     SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
+
+	regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
+		     SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
+		     SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
+}
+
+static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
+				    struct drm_display_mode *mode)
+{
+	struct mipi_dsi_device *device = dsi->device;
+	unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
+	u16 hbp, hfp, hsa, hblk, vblk;
+
+	regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, 0);
+
+	regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
+		     sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
+					      device->channel,
+					      0, 0));
+
+	regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
+		     sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
+					      device->channel,
+					      0, 0));
+
+	regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
+		     sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
+					      device->channel,
+					      0, 0));
+
+	regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
+		     sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
+					      device->channel,
+					      0, 0));
+
+	regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
+		     SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
+					       mode->vsync_start) |
+		     SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start -
+					       mode->vdisplay));
+
+	regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
+		     SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
+		     SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
+
+	/*
+	 * A sync period is composed of a blanking packet (4 bytes +
+	 * payload + 2 bytes) and a sync event packet (4 bytes). Its
+	 * minimal size is therefore 10 bytes
+	 */
+#define HSA_PACKET_OVERHEAD	10
+	hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
+		  (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
+		     sun6i_dsi_build_blk0_pkt(device->channel, hsa));
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
+		     sun6i_dsi_build_blk1_pkt(0, hsa));
+
+	/*
+	 * The backporch is set using a blanking packet (4 bytes +
+	 * payload + 2 bytes). Its minimal size is therefore 6 bytes
+	 */
+#define HBP_PACKET_OVERHEAD	6
+	hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
+		  (mode->hsync_start - mode->hdisplay) * Bpp - HBP_PACKET_OVERHEAD);
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
+		     sun6i_dsi_build_blk0_pkt(device->channel, hbp));
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
+		     sun6i_dsi_build_blk1_pkt(0, hbp));
+
+	/*
+	 * The frontporch is set using a blanking packet (4 bytes +
+	 * payload + 2 bytes). Its minimal size is therefore 6 bytes
+	 */
+#define HFP_PACKET_OVERHEAD	6
+	hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
+		  (mode->htotal - mode->hsync_end) * Bpp - HFP_PACKET_OVERHEAD);
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
+		     sun6i_dsi_build_blk0_pkt(device->channel, hfp));
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
+		     sun6i_dsi_build_blk1_pkt(0, hfp));
+
+	/*
+	 * hblk seems to be the line + porches length.
+	 */
+	hblk = mode->htotal * Bpp - hsa;
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
+		     sun6i_dsi_build_blk0_pkt(device->channel, hblk));
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
+		     sun6i_dsi_build_blk1_pkt(0, hblk));
+
+	/*
+	 * And I'm not entirely sure what vblk is about. The driver in
+	 * Allwinner BSP is using a rather convoluted calculation
+	 * there only for 4 lanes. However, using 0 (the !4 lanes
+	 * case) even with a 4 lanes screen seems to work...
+	 */
+	vblk = 0;
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
+		     sun6i_dsi_build_blk0_pkt(device->channel, vblk));
+	regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
+		     sun6i_dsi_build_blk1_pkt(0, vblk));
+}
+
+static int sun6i_dsi_start(struct sun6i_dsi *dsi,
+			   enum sun6i_dsi_start_inst func)
+{
+	switch (func) {
+	case DSI_START_LPTX:
+		regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
+			     DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
+			     DSI_INST_ID_END  << (4 * DSI_INST_ID_LPDT));
+		break;
+	case DSI_START_LPRX:
+		regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
+			     DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
+			     DSI_INST_ID_DLY  << (4 * DSI_INST_ID_LPDT) |
+			     DSI_INST_ID_TBA  << (4 * DSI_INST_ID_DLY) |
+			     DSI_INST_ID_END  << (4 * DSI_INST_ID_TBA));
+		break;
+	case DSI_START_HSC:
+		regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
+			     DSI_INST_ID_HSC  << (4 * DSI_INST_ID_LP11) |
+			     DSI_INST_ID_END  << (4 * DSI_INST_ID_HSC));
+		break;
+	case DSI_START_HSD:
+		regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
+			     DSI_INST_ID_NOP  << (4 * DSI_INST_ID_LP11) |
+			     DSI_INST_ID_HSD  << (4 * DSI_INST_ID_NOP) |
+			     DSI_INST_ID_DLY  << (4 * DSI_INST_ID_HSD) |
+			     DSI_INST_ID_NOP  << (4 * DSI_INST_ID_DLY) |
+			     DSI_INST_ID_END  << (4 * DSI_INST_ID_HSCEXIT));
+		break;
+	default:
+		regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
+			     DSI_INST_ID_END  << (4 * DSI_INST_ID_LP11));
+		break;
+	}
+
+	sun6i_dsi_inst_abort(dsi);
+	sun6i_dsi_inst_commit(dsi);
+
+	if (func == DSI_START_HSC)
+		regmap_write_bits(dsi->regs,
+				  SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
+				  SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
+
+	return 0;
+}
+
+static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+{
+	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+	struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
+	struct mipi_dsi_device *device = dsi->device;
+	u16 delay;
+
+	DRM_DEBUG_DRIVER("Enabling DSI output\n");
+
+	pm_runtime_get_sync(dsi->dev);
+
+	delay = sun6i_dsi_get_video_start_delay(dsi, mode);
+	regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
+		     SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
+		     SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
+		     SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
+		     SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
+
+	sun6i_dsi_setup_burst(dsi, mode);
+	sun6i_dsi_setup_inst_loop(dsi, mode);
+	sun6i_dsi_setup_format(dsi, mode);
+	sun6i_dsi_setup_timings(dsi, mode);
+
+	sun6i_dphy_init(dsi->dphy, device->lanes);
+	sun6i_dphy_power_on(dsi->dphy, device->lanes);
+
+	if (!IS_ERR(dsi->panel))
+		drm_panel_prepare(dsi->panel);
+
+	sun6i_dsi_start(dsi, DSI_START_HSC);
+
+	udelay(1000);
+
+	sun6i_dsi_start(dsi, DSI_START_HSD);
+
+	if (!IS_ERR(dsi->panel))
+		drm_panel_enable(dsi->panel);
+}
+
+static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
+{
+	struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
+
+	DRM_DEBUG_DRIVER("Disabling DSI output\n");
+
+	if (!IS_ERR(dsi->panel)) {
+		drm_panel_disable(dsi->panel);
+		drm_panel_unprepare(dsi->panel);
+	}
+
+	sun6i_dphy_power_off(dsi->dphy);
+	sun6i_dphy_exit(dsi->dphy);
+
+	pm_runtime_put(dsi->dev);
+}
+
+static int sun6i_dsi_get_modes(struct drm_connector *connector)
+{
+	struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
+
+	return drm_panel_get_modes(dsi->panel);
+}
+
+static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
+	.get_modes	= sun6i_dsi_get_modes,
+};
+
+static enum drm_connector_status
+sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
+	.dpms			= drm_atomic_helper_connector_dpms,
+	.detect			= sun6i_dsi_connector_detect,
+	.fill_modes		= drm_helper_probe_single_connector_modes,
+	.destroy		= drm_connector_cleanup,
+	.reset			= drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
+};
+
+static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
+	.disable	= sun6i_dsi_encoder_disable,
+	.enable		= sun6i_dsi_encoder_enable,
+};
+
+static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
+	.destroy	= drm_encoder_cleanup,
+};
+
+static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
+				       const struct mipi_dsi_msg *msg)
+{
+	u32 pkt = msg->type;
+
+	if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
+		pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
+		pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
+	} else {
+		pkt |= (((u8 *)msg->tx_buf)[0] << 8);
+		if (msg->tx_len > 1)
+			pkt |= (((u8 *)msg->tx_buf)[1] << 16);
+	}
+
+	pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
+
+	return pkt;
+}
+
+static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
+				     const struct mipi_dsi_msg *msg)
+{
+	regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
+		     sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
+	regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
+			  0xff, (4 - 1));
+
+	sun6i_dsi_start(dsi, DSI_START_LPTX);
+
+	return msg->tx_len;
+}
+
+static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
+				    const struct mipi_dsi_msg *msg)
+{
+	int ret, len = 0;
+	u8 *bounce;
+	u16 crc;
+	u32 val;
+
+	regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
+		     sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
+
+	bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
+	if (!bounce)
+		return -ENOMEM;
+
+	memcpy(bounce, msg->tx_buf, msg->tx_len);
+	len += msg->tx_len;
+
+	crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
+	memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
+	len += sizeof(crc);
+
+	regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
+	regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
+	kfree(bounce);
+
+	sun6i_dsi_start(dsi, DSI_START_LPTX);
+
+	ret = sun6i_dsi_inst_wait_for_completion(dsi);
+	if (ret < 0) {
+		sun6i_dsi_inst_abort(dsi);
+		return ret;
+	}
+
+	regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
+	if (!(val & SUN6I_DSI_CMD_CTL_TX_FLAG))
+		return -EAGAIN;
+
+	return msg->tx_len;
+}
+
+static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
+			      const struct mipi_dsi_msg *msg)
+{
+	u32 val;
+	int ret;
+	u8 byte0;
+
+	regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
+		     sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
+	regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
+		     (4 - 1));
+
+	sun6i_dsi_start(dsi, DSI_START_LPRX);
+
+	ret = sun6i_dsi_inst_wait_for_completion(dsi);
+	if (ret < 0) {
+		sun6i_dsi_inst_abort(dsi);
+		return ret;
+	}
+
+	regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
+	if (!(val & SUN6I_DSI_CMD_CTL_RX_FLAG))
+		return -EAGAIN;
+
+	if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
+		return -EIO;
+
+	regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
+	byte0 = val & 0xff;
+	if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
+		return -EIO;
+
+	((u8 *)msg->rx_buf)[0] = (val >> 8);
+
+	return 1;
+}
+
+static int sun6i_dsi_attach(struct mipi_dsi_host *host,
+			    struct mipi_dsi_device *device)
+{
+	struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
+
+	dsi->device = device;
+	dsi->panel = of_drm_find_panel(device->dev.of_node);
+	if (!dsi->panel)
+		return -EINVAL;
+
+	dev_info(host->dev, "Attached device %s\n", device->name);
+
+	return 0;
+}
+
+static int sun6i_dsi_detach(struct mipi_dsi_host *host,
+			    struct mipi_dsi_device *device)
+{
+	struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
+
+	dsi->panel = NULL;
+	dsi->device = NULL;
+
+	return 0;
+}
+
+static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
+				  const struct mipi_dsi_msg *msg)
+{
+	struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
+	int ret;
+
+	ret = sun6i_dsi_inst_wait_for_completion(dsi);
+	if (ret < 0)
+		sun6i_dsi_inst_abort(dsi);
+
+	regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
+		     SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
+		     SUN6I_DSI_CMD_CTL_RX_FLAG |
+		     SUN6I_DSI_CMD_CTL_TX_FLAG);
+
+	switch (msg->type) {
+	case MIPI_DSI_DCS_SHORT_WRITE:
+	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+		ret = sun6i_dsi_dcs_write_short(dsi, msg);
+		break;
+
+	case MIPI_DSI_DCS_LONG_WRITE:
+		ret = sun6i_dsi_dcs_write_long(dsi, msg);
+		break;
+
+	case MIPI_DSI_DCS_READ:
+		if (msg->rx_len == 1) {
+			ret = sun6i_dsi_dcs_read(dsi, msg);
+			break;
+		}
+
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
+	.attach		= sun6i_dsi_attach,
+	.detach		= sun6i_dsi_detach,
+	.transfer	= sun6i_dsi_transfer,
+};
+
+static const struct regmap_config sun6i_dsi_regmap_config = {
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= SUN6I_DSI_CMD_TX_REG(255),
+	.name		= "mipi-dsi",
+};
+
+static int sun6i_dsi_bind(struct device *dev, struct device *master,
+			 void *data)
+{
+	struct drm_device *drm = data;
+	struct sun4i_drv *drv = drm->dev_private;
+	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
+	int ret;
+
+	if (!dsi->panel)
+		return -EPROBE_DEFER;
+
+	dsi->drv = drv;
+
+	drm_encoder_helper_add(&dsi->encoder,
+			       &sun6i_dsi_enc_helper_funcs);
+	ret = drm_encoder_init(drm,
+			       &dsi->encoder,
+			       &sun6i_dsi_enc_funcs,
+			       DRM_MODE_ENCODER_DSI,
+			       NULL);
+	if (ret) {
+		dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
+		return ret;
+	}
+	dsi->encoder.possible_crtcs = BIT(0);
+
+	drm_connector_helper_add(&dsi->connector,
+				 &sun6i_dsi_connector_helper_funcs);
+	ret = drm_connector_init(drm, &dsi->connector,
+				 &sun6i_dsi_connector_funcs,
+				 DRM_MODE_CONNECTOR_DSI);
+	if (ret) {
+		dev_err(dsi->dev,
+			"Couldn't initialise the DSI connector\n");
+		goto err_cleanup_connector;
+	}
+
+	drm_mode_connector_attach_encoder(&dsi->connector, &dsi->encoder);
+	drm_panel_attach(dsi->panel, &dsi->connector);
+
+	return 0;
+
+err_cleanup_connector:
+	drm_encoder_cleanup(&dsi->encoder);
+	return ret;
+}
+
+static void sun6i_dsi_unbind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
+
+	drm_panel_detach(dsi->panel);
+}
+
+static const struct component_ops sun6i_dsi_ops = {
+	.bind	= sun6i_dsi_bind,
+	.unbind	= sun6i_dsi_unbind,
+};
+
+static int sun6i_dsi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *dphy_node;
+	struct sun6i_dsi *dsi;
+	struct resource *res;
+	void __iomem *base;
+	int ret;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return -ENOMEM;
+	dev_set_drvdata(dev, dsi);
+	dsi->dev = dev;
+	dsi->host.ops = &sun6i_dsi_host_ops;
+	dsi->host.dev = dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base)) {
+		dev_err(dev, "Couldn't map the DSI encoder registers\n");
+		return PTR_ERR(base);
+	}
+
+	dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
+					      &sun6i_dsi_regmap_config);
+	if (IS_ERR(dsi->regs)) {
+		dev_err(dev, "Couldn't create the DSI encoder regmap\n");
+		return PTR_ERR(dsi->regs);
+	}
+
+	dsi->reset = devm_reset_control_get_shared(dev, NULL);
+	if (IS_ERR(dsi->reset)) {
+		dev_err(dev, "Couldn't get our reset line\n");
+		return PTR_ERR(dsi->reset);
+	}
+
+	dsi->mod_clk = devm_clk_get(dev, "mod");
+	if (IS_ERR(dsi->mod_clk)) {
+		dev_err(dev, "Couldn't get the DSI mod clock\n");
+		return PTR_ERR(dsi->mod_clk);
+	}
+
+	/*
+	 * In order to operate properly, that clock seems to be always
+	 * set to 297MHz.
+	 */
+	clk_set_rate_protect(dsi->mod_clk, 297000000);
+
+	dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
+	ret = sun6i_dphy_probe(dsi, dphy_node);
+	of_node_put(dphy_node);
+	if (ret) {
+		dev_err(dev, "Couldn't get the MIPI D-PHY\n");
+		goto err_unprotect_clk;
+	}
+
+	pm_runtime_enable(dev);
+
+	ret = mipi_dsi_host_register(&dsi->host);
+	if (ret) {
+		dev_err(dev, "Couldn't register MIPI-DSI host\n");
+		goto err_remove_phy;
+	}
+
+	ret = component_add(&pdev->dev, &sun6i_dsi_ops);
+	if (ret) {
+		dev_err(dev, "Couldn't register our component\n");
+		goto err_remove_dsi_host;
+	}
+
+	return 0;
+
+err_remove_dsi_host:
+	mipi_dsi_host_unregister(&dsi->host);
+err_remove_phy:
+	pm_runtime_disable(dev);
+	sun6i_dphy_remove(dsi);
+err_unprotect_clk:
+	clk_rate_unprotect(dsi->mod_clk);
+	return ret;
+}
+
+static int sun6i_dsi_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
+
+	component_del(&pdev->dev, &sun6i_dsi_ops);
+	mipi_dsi_host_unregister(&dsi->host);
+	pm_runtime_disable(dev);
+	sun6i_dphy_remove(dsi);
+	clk_rate_unprotect(dsi->mod_clk);
+
+	return 0;
+}
+
+static int sun6i_dsi_runtime_resume(struct device *dev)
+{
+	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
+
+	reset_control_deassert(dsi->reset);
+	clk_prepare_enable(dsi->mod_clk);
+
+	/*
+	 * Enable the DSI block.
+	 *
+	 * Some part of it can only be done once we get a number of
+	 * lanes, see sun6i_dsi_inst_init
+	 */
+	regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
+
+	regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
+		     SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
+
+	regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
+	regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
+
+	if (dsi->device)
+		sun6i_dsi_inst_init(dsi, dsi->device);
+
+	regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
+
+	return 0;
+}
+
+static int sun6i_dsi_runtime_suspend(struct device *dev)
+{
+	struct sun6i_dsi *dsi = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(dsi->mod_clk);
+	reset_control_assert(dsi->reset);
+
+	return 0;
+}
+
+static const struct dev_pm_ops sun6i_dsi_pm_ops = {
+	SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
+			   sun6i_dsi_runtime_resume,
+			   NULL)
+};
+
+static const struct of_device_id sun6i_dsi_of_table[] = {
+	{ .compatible = "allwinner,sun6i-a31-mipi-dsi" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
+
+static struct platform_driver sun6i_dsi_platform_driver = {
+	.probe		= sun6i_dsi_probe,
+	.remove		= sun6i_dsi_remove,
+	.driver		= {
+		.name		= "sun6i-mipi-dsi",
+		.of_match_table	= sun6i_dsi_of_table,
+		.pm		= &sun6i_dsi_pm_ops,
+	},
+};
+module_platform_driver(sun6i_dsi_platform_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
new file mode 100644
index 000000000000..363748808637
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+ * Copyright (C) 2017 Free Electrons
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _SUN6I_MIPI_DSI_H_
+#define _SUN6I_MIPI_DSI_H_
+
+#include <drm/drm_connector.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_mipi_dsi.h>
+
+struct sun6i_dphy {
+	struct clk		*bus_clk;
+	struct clk		*mod_clk;
+	struct regmap		*regs;
+	struct reset_control	*reset;
+};
+
+struct sun6i_dsi {
+	struct drm_connector	connector;
+	struct drm_encoder	encoder;
+	struct mipi_dsi_host	host;
+
+	struct clk		*bus_clk;
+	struct clk		*mod_clk;
+	struct regmap		*regs;
+	struct reset_control	*reset;
+	struct sun6i_dphy	*dphy;
+
+	struct device		*dev;
+	struct sun4i_drv	*drv;
+	struct mipi_dsi_device	*device;
+	struct drm_panel	*panel;
+};
+
+static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
+{
+	return container_of(host, struct sun6i_dsi, host);
+};
+
+static inline struct sun6i_dsi *connector_to_sun6i_dsi(struct drm_connector *connector)
+{
+	return container_of(connector, struct sun6i_dsi, connector);
+};
+
+static inline struct sun6i_dsi *encoder_to_sun6i_dsi(struct drm_encoder *encoder)
+{
+	return container_of(encoder, struct sun6i_dsi, encoder);
+};
+
+int sun6i_dphy_probe(struct sun6i_dsi *dsi, struct device_node *node);
+int sun6i_dphy_remove(struct sun6i_dsi *dsi);
+
+int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes);
+int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes);
+int sun6i_dphy_power_off(struct sun6i_dphy *dphy);
+int sun6i_dphy_exit(struct sun6i_dphy *dphy);
+
+#endif /* _SUN6I_MIPI_DSI_H_ */
-- 
git-series 0.9.1

[PATCH 13/18] dt-bindings: vendor: Add Huarui Lighting

[Maxime Ripard]

Huarui Lighting makes display panel, add it to the list of panels.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index afbb47ce50dd..cc5850a325f8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -142,6 +142,7 @@ holt	Holt Integrated Circuits, Inc.
 honeywell	Honeywell
 hp	Hewlett Packard
 holtek	Holtek Semiconductor, Inc.
+huarui	Huarui Lighting Co. Ltd
 hwacom	HwaCom Systems Inc.
 i2se	I2SE GmbH
 ibm	International Business Machines (IBM)
-- 
git-series 0.9.1

[PATCH 14/18] dt-bindings: panel: Add Huarui LHR050H41 panel documentation

[Maxime Ripard]

The LHR050H41 is a 1280x700 4-lanes DSI panel.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt

diff --git a/Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt b/Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt
new file mode 100644
index 000000000000..b254db4d29c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt
@@ -0,0 +1,19 @@
+Huarui LHR050H41 MIPI-DSI panel
+
+Required properties:
+  - compatible: "huarui,lhr050h41"
+  - reg: DSI virtual channel used by that screen
+  - power-gpios: a GPIO phandle for the power pin
+  - reset-gpios: a GPIO phandle for the reset pin
+
+Optional properties:
+  - backlight: phandle to the backlight used
+
+Example:
+panel@0 {
+	compatible = "huarui,lhr050h41";
+	reg = <0>;
+	power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
+	reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
+	backlight = <&pwm_bl>;
+};
-- 
git-series 0.9.1

[PATCH 15/18] drm/panel: Add Huarui LHR050H41 panel driver

[Maxime Ripard]

The LHR050H41 panel is the panel shipped with the BananaPi M2-Magic. Add a
driver for it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/gpu/drm/panel/Kconfig                  |   9 +-
 drivers/gpu/drm/panel/Makefile                 |   1 +-
 drivers/gpu/drm/panel/panel-huarui-lhr050h41.c | 444 ++++++++++++++++++-
 3 files changed, 454 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-huarui-lhr050h41.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d84a031fae24..eaa6e102775a 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -28,6 +28,15 @@ config DRM_PANEL_SIMPLE
 	  that it can be automatically turned off when the panel goes into a
 	  low power state.
 
+config DRM_PANEL_HUARUI_LHR050H41
+	tristate "Huarui LHR050H41 panel"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y if you want to enable support for the Huarui Lighting
+	  LHR05041 DSI panel. The panel has a 1280x720 resolution.
+
 config DRM_PANEL_INNOLUX_P079ZCA
 	tristate "Innolux P079ZCA panel"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 9f6610d08b00..58de7a853898 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
+obj-$(CONFIG_DRM_PANEL_HUARUI_LHR050H41) += panel-huarui-lhr050h41.o
 obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
 obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
 obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
diff --git a/drivers/gpu/drm/panel/panel-huarui-lhr050h41.c b/drivers/gpu/drm/panel/panel-huarui-lhr050h41.c
new file mode 100644
index 000000000000..eb675eb9ee7d
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-huarui-lhr050h41.c
@@ -0,0 +1,444 @@
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/gpio/consumer.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+#include <video/mipi_display.h>
+
+struct lhr050h41 {
+	struct drm_panel	panel;
+	struct mipi_dsi_device	*dsi;
+
+	struct backlight_device *backlight;
+	struct gpio_desc	*power;
+	struct gpio_desc	*reset;
+};
+
+static inline struct lhr050h41 *panel_to_lhr050h41(struct drm_panel *panel)
+{
+	return container_of(panel, struct lhr050h41, panel);
+}
+
+static int lhr050h41_switch_page(struct lhr050h41 *ctx, u8 page)
+{
+	u8 buf[4] = { 0xff, 0x98, 0x81, page };
+
+	return mipi_dsi_dcs_write_buffer(ctx->dsi, buf, sizeof(buf));
+}
+
+static int lhr050h41_send_cmd_data(struct lhr050h41 *ctx, u8 cmd, u8 data)
+{
+	u8 buf[2] = { cmd, data };
+
+	return mipi_dsi_dcs_write_buffer(ctx->dsi, buf, sizeof(buf));
+}
+
+static int lhr050h41_send_init_sequence(struct lhr050h41 *ctx)
+{
+	lhr050h41_switch_page(ctx, 3);
+
+	lhr050h41_send_cmd_data(ctx, 0x01, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x02, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x03, 0x73);
+	lhr050h41_send_cmd_data(ctx, 0x04, 0x03);
+	lhr050h41_send_cmd_data(ctx, 0x05, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x06, 0x06);
+	lhr050h41_send_cmd_data(ctx, 0x07, 0x06);
+	lhr050h41_send_cmd_data(ctx, 0x08, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x09, 0x18);
+	lhr050h41_send_cmd_data(ctx, 0x0a, 0x04);
+	lhr050h41_send_cmd_data(ctx, 0x0b, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x0c, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x0d, 0x03);
+	lhr050h41_send_cmd_data(ctx, 0x0e, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x0f, 0x25);
+	lhr050h41_send_cmd_data(ctx, 0x10, 0x25);
+	lhr050h41_send_cmd_data(ctx, 0x11, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x12, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x13, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x14, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x15, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x16, 0x0C);
+	lhr050h41_send_cmd_data(ctx, 0x17, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x18, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x19, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x1a, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x1b, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x1c, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x1d, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x1e, 0xC0);
+	lhr050h41_send_cmd_data(ctx, 0x1f, 0x80);
+	lhr050h41_send_cmd_data(ctx, 0x20, 0x04);
+	lhr050h41_send_cmd_data(ctx, 0x21, 0x01);
+	lhr050h41_send_cmd_data(ctx, 0x22, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x23, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x24, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x25, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x26, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x27, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x28, 0x33);
+	lhr050h41_send_cmd_data(ctx, 0x29, 0x03);
+	lhr050h41_send_cmd_data(ctx, 0x2a, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x2b, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x2c, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x2d, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x2e, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x2f, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x30, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x31, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x32, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x33, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x34, 0x04);
+	lhr050h41_send_cmd_data(ctx, 0x35, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x36, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x37, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x38, 0x3C);
+	lhr050h41_send_cmd_data(ctx, 0x39, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x3a, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x3b, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x3c, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x3d, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x3e, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x3f, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x40, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x41, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x42, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x43, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x44, 0x00);
+
+	lhr050h41_send_cmd_data(ctx, 0x50, 0x01);
+	lhr050h41_send_cmd_data(ctx, 0x51, 0x23);
+	lhr050h41_send_cmd_data(ctx, 0x52, 0x45);
+	lhr050h41_send_cmd_data(ctx, 0x53, 0x67);
+	lhr050h41_send_cmd_data(ctx, 0x54, 0x89);
+	lhr050h41_send_cmd_data(ctx, 0x55, 0xab);
+	lhr050h41_send_cmd_data(ctx, 0x56, 0x01);
+	lhr050h41_send_cmd_data(ctx, 0x57, 0x23);
+	lhr050h41_send_cmd_data(ctx, 0x58, 0x45);
+	lhr050h41_send_cmd_data(ctx, 0x59, 0x67);
+	lhr050h41_send_cmd_data(ctx, 0x5a, 0x89);
+	lhr050h41_send_cmd_data(ctx, 0x5b, 0xab);
+	lhr050h41_send_cmd_data(ctx, 0x5c, 0xcd);
+	lhr050h41_send_cmd_data(ctx, 0x5d, 0xef);
+
+	lhr050h41_send_cmd_data(ctx, 0x5e, 0x11);
+	lhr050h41_send_cmd_data(ctx, 0x5f, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x60, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x61, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x62, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x63, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x64, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x65, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x66, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x67, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x68, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x69, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x6a, 0x0C);
+	lhr050h41_send_cmd_data(ctx, 0x6b, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x6c, 0x0F);
+	lhr050h41_send_cmd_data(ctx, 0x6d, 0x0E);
+	lhr050h41_send_cmd_data(ctx, 0x6e, 0x0D);
+	lhr050h41_send_cmd_data(ctx, 0x6f, 0x06);
+	lhr050h41_send_cmd_data(ctx, 0x70, 0x07);
+	lhr050h41_send_cmd_data(ctx, 0x71, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x72, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x73, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x74, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x75, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x76, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x77, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x78, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x79, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x7a, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x7b, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x7c, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x7d, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x7e, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x7f, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x80, 0x0C);
+	lhr050h41_send_cmd_data(ctx, 0x81, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x82, 0x0F);
+	lhr050h41_send_cmd_data(ctx, 0x83, 0x0E);
+	lhr050h41_send_cmd_data(ctx, 0x84, 0x0D);
+	lhr050h41_send_cmd_data(ctx, 0x85, 0x06);
+	lhr050h41_send_cmd_data(ctx, 0x86, 0x07);
+	lhr050h41_send_cmd_data(ctx, 0x87, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x88, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x89, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x8A, 0x02);
+
+	lhr050h41_switch_page(ctx, 4);
+	lhr050h41_send_cmd_data(ctx, 0x6C, 0x15);
+	lhr050h41_send_cmd_data(ctx, 0x6E, 0x22);
+	lhr050h41_send_cmd_data(ctx, 0x6F, 0x33);
+	lhr050h41_send_cmd_data(ctx, 0x3A, 0xA4);
+	lhr050h41_send_cmd_data(ctx, 0x8D, 0x0D);
+	lhr050h41_send_cmd_data(ctx, 0x87, 0xBA);
+	lhr050h41_send_cmd_data(ctx, 0x26, 0x76);
+	lhr050h41_send_cmd_data(ctx, 0xB2, 0xD1);
+
+	lhr050h41_switch_page(ctx, 1);
+	lhr050h41_send_cmd_data(ctx, 0x22, 0x0A);
+	lhr050h41_send_cmd_data(ctx, 0x53, 0xDC);
+	lhr050h41_send_cmd_data(ctx, 0x55, 0xA7);
+	lhr050h41_send_cmd_data(ctx, 0x50, 0x78);
+	lhr050h41_send_cmd_data(ctx, 0x51, 0x78);
+	lhr050h41_send_cmd_data(ctx, 0x31, 0x02);
+	lhr050h41_send_cmd_data(ctx, 0x60, 0x14);
+	lhr050h41_send_cmd_data(ctx, 0xA0, 0x2A);
+	lhr050h41_send_cmd_data(ctx, 0xA1, 0x39);
+	lhr050h41_send_cmd_data(ctx, 0xA2, 0x46);
+	lhr050h41_send_cmd_data(ctx, 0xA3, 0x0e);
+	lhr050h41_send_cmd_data(ctx, 0xA4, 0x12);
+	lhr050h41_send_cmd_data(ctx, 0xA5, 0x25);
+	lhr050h41_send_cmd_data(ctx, 0xA6, 0x19);
+	lhr050h41_send_cmd_data(ctx, 0xA7, 0x1d);
+	lhr050h41_send_cmd_data(ctx, 0xA8, 0xa6);
+	lhr050h41_send_cmd_data(ctx, 0xA9, 0x1C);
+	lhr050h41_send_cmd_data(ctx, 0xAA, 0x29);
+	lhr050h41_send_cmd_data(ctx, 0xAB, 0x85);
+	lhr050h41_send_cmd_data(ctx, 0xAC, 0x1C);
+	lhr050h41_send_cmd_data(ctx, 0xAD, 0x1B);
+	lhr050h41_send_cmd_data(ctx, 0xAE, 0x51);
+	lhr050h41_send_cmd_data(ctx, 0xAF, 0x22);
+	lhr050h41_send_cmd_data(ctx, 0xB0, 0x2d);
+	lhr050h41_send_cmd_data(ctx, 0xB1, 0x4f);
+	lhr050h41_send_cmd_data(ctx, 0xB2, 0x59);
+	lhr050h41_send_cmd_data(ctx, 0xB3, 0x3F);
+	lhr050h41_send_cmd_data(ctx, 0xC0, 0x2A);
+	lhr050h41_send_cmd_data(ctx, 0xC1, 0x3a);
+	lhr050h41_send_cmd_data(ctx, 0xC2, 0x45);
+	lhr050h41_send_cmd_data(ctx, 0xC3, 0x0e);
+	lhr050h41_send_cmd_data(ctx, 0xC4, 0x11);
+	lhr050h41_send_cmd_data(ctx, 0xC5, 0x24);
+	lhr050h41_send_cmd_data(ctx, 0xC6, 0x1a);
+	lhr050h41_send_cmd_data(ctx, 0xC7, 0x1c);
+	lhr050h41_send_cmd_data(ctx, 0xC8, 0xaa);
+	lhr050h41_send_cmd_data(ctx, 0xC9, 0x1C);
+	lhr050h41_send_cmd_data(ctx, 0xCA, 0x29);
+	lhr050h41_send_cmd_data(ctx, 0xCB, 0x96);
+	lhr050h41_send_cmd_data(ctx, 0xCC, 0x1C);
+	lhr050h41_send_cmd_data(ctx, 0xCD, 0x1B);
+	lhr050h41_send_cmd_data(ctx, 0xCE, 0x51);
+	lhr050h41_send_cmd_data(ctx, 0xCF, 0x22);
+	lhr050h41_send_cmd_data(ctx, 0xD0, 0x2b);
+	lhr050h41_send_cmd_data(ctx, 0xD1, 0x4b);
+	lhr050h41_send_cmd_data(ctx, 0xD2, 0x59);
+	lhr050h41_send_cmd_data(ctx, 0xD3, 0x3F);
+
+	lhr050h41_switch_page(ctx, 0);
+	lhr050h41_send_cmd_data(ctx, 0x35, 0x00);
+	lhr050h41_send_cmd_data(ctx, 0x11, 0x00);
+
+	mdelay(120);
+
+	lhr050h41_send_cmd_data(ctx, 0x29, 0x00);
+
+	mdelay(20);
+
+	return 0;
+}
+
+static int lhr050h41_prepare(struct drm_panel *panel)
+{
+	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
+
+	/* Power the panel */
+	gpiod_set_value(ctx->power, 1);
+	mdelay(5);
+
+	/* And reset it */
+	gpiod_set_value(ctx->reset, 1);
+	mdelay(20);
+
+	gpiod_set_value(ctx->reset, 0);
+	mdelay(20);
+
+	lhr050h41_send_init_sequence(ctx);
+
+	return 0;
+}
+
+static void lhr050h41_enable_bl(struct lhr050h41 *ctx, bool enable)
+{
+	if (!ctx->backlight)
+		return;
+
+	if (enable) {
+		ctx->backlight->props.state &= ~BL_CORE_FBBLANK;
+		ctx->backlight->props.power = FB_BLANK_UNBLANK;
+	} else {
+		ctx->backlight->props.power = FB_BLANK_POWERDOWN;
+		ctx->backlight->props.state |= BL_CORE_FBBLANK;
+	}
+
+	backlight_update_status(ctx->backlight);
+}
+
+static int lhr050h41_enable(struct drm_panel *panel)
+{
+	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
+
+	lhr050h41_enable_bl(ctx, true);
+
+	return 0;
+}
+
+static int lhr050h41_disable(struct drm_panel *panel)
+{
+	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
+
+	lhr050h41_enable_bl(ctx, false);
+
+	return mipi_dsi_dcs_set_display_off(ctx->dsi);
+}
+
+static int lhr050h41_unprepare(struct drm_panel *panel)
+{
+	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
+
+	mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
+	gpiod_set_value(ctx->power, 0);
+	gpiod_set_value(ctx->reset, 1);
+
+	return 0;
+}
+
+static const struct drm_display_mode default_mode = {
+	.clock		= 62000,
+	.vrefresh	= 60,
+
+	.hdisplay	= 720,
+	.hsync_start	= 720 + 10,
+	.hsync_end	= 720 + 10 + 20,
+	.htotal		= 720 + 10 + 20 + 30,
+
+	.vdisplay	= 1280,
+	.vsync_start	= 1280 + 10,
+	.vsync_end	= 1280 + 10 + 10,
+	.vtotal		= 1280 + 10 + 10 + 20,
+};
+
+static int lhr050h41_get_modes(struct drm_panel *panel)
+{
+	struct drm_connector *connector = panel->connector;
+	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(panel->drm, &default_mode);
+	if (!mode) {
+		dev_err(&ctx->dsi->dev, "failed to add mode %ux%ux@%u\n",
+			default_mode.hdisplay, default_mode.vdisplay,
+			default_mode.vrefresh);
+		return -ENOMEM;
+	}
+
+	drm_mode_set_name(mode);
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_probed_add(connector, mode);
+
+	panel->connector->display_info.width_mm = 62;
+	panel->connector->display_info.height_mm = 110;
+
+	return 1;
+}
+
+static const struct drm_panel_funcs lhr050h41_funcs = {
+	.prepare	= lhr050h41_prepare,
+	.unprepare	= lhr050h41_unprepare,
+	.enable		= lhr050h41_enable,
+	.disable	= lhr050h41_disable,
+	.get_modes	= lhr050h41_get_modes,
+};
+
+static int lhr050h41_dsi_probe(struct mipi_dsi_device *dsi)
+{
+	struct device_node *np;
+	struct lhr050h41 *ctx;
+	int ret;
+
+	ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dsi = dsi;
+
+	drm_panel_init(&ctx->panel);
+	ctx->panel.dev = &dsi->dev;
+	ctx->panel.funcs = &lhr050h41_funcs;
+
+	ctx->power = devm_gpiod_get(&dsi->dev, "power", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->power)) {
+		dev_err(&dsi->dev, "Couldn't get our power GPIO\n");
+		return PTR_ERR(ctx->power);
+	}
+
+	ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
+	if (IS_ERR(ctx->reset)) {
+		dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
+		return PTR_ERR(ctx->reset);
+	}
+
+	np = of_parse_phandle(dsi->dev.of_node, "backlight", 0);
+	if (np) {
+		ctx->backlight = of_find_backlight_by_node(np);
+		of_node_put(np);
+
+		if (!ctx->backlight)
+			return -EPROBE_DEFER;
+	}
+
+	ret = drm_panel_add(&ctx->panel);
+	if (ret < 0)
+		return ret;
+
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->lanes = 4;
+
+	return mipi_dsi_attach(dsi);
+}
+
+static int lhr050h41_dsi_remove(struct mipi_dsi_device *dsi)
+{
+	struct lhr050h41 *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+
+	if (ctx->backlight)
+		put_device(&ctx->backlight->dev);
+
+	return 0;
+}
+
+static const struct of_device_id lhr050h41_of_match[] = {
+	{ .compatible = "huarui,lhr050h41" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, lhr050h41_of_match);
+
+static struct mipi_dsi_driver lhr050h41_dsi_driver = {
+	.probe		= lhr050h41_dsi_probe,
+	.remove		= lhr050h41_dsi_remove,
+	.driver = {
+		.name		= "lhr050h41-dsi",
+		.of_match_table	= lhr050h41_of_match,
+	},
+};
+module_mipi_dsi_driver(lhr050h41_dsi_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_DESCRIPTION("Huarui LHR050H41 LCD Driver");
+MODULE_LICENSE("GPL v2");
-- 
git-series 0.9.1

[PATCH 16/18] arm: dts: sun8i: a33: Add the DSI-related nodes

[Maxime Ripard]

The A33 has a MIPI-DSI block, along with its D-PHY. Let's add it in order
to use it in the relevant boards.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun8i-a33.dtsi | 50 ++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 22660919bd08..18d1bf9f8e84 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -236,10 +236,14 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <1>;
+
+					tcon0_out_dsi0: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&dsi0_in_tcon0>;
+					};
 				};
 			};
 		};
-
 		crypto: crypto-engine@01c15000 {
 			compatible = "allwinner,sun4i-a10-crypto";
 			reg = <0x01c15000 0x1000>;
@@ -280,6 +284,50 @@
 			#io-channel-cells = <0>;
 		};
 
+		dsi0: dsi@01ca0000 {
+			compatible = "allwinner,sun6i-a31-mipi-dsi";
+			reg = <0x01ca0000 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+				 <&ccu CLK_DSI_SCLK>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_MIPI_DSI>;
+			phys = <&dphy0>;
+			phy-names = "dphy";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dsi0_in: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					dsi0_in_tcon0: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&tcon0_out_dsi0>;
+					};
+				};
+			};
+		};
+
+		dphy0: d-phy@01ca1000 {
+			compatible = "allwinner,sun6i-a31-mipi-dphy";
+			reg = <0x01ca1000 0x1000>;
+			clocks = <&ccu CLK_BUS_MIPI_DSI>,
+				 <&ccu CLK_DSI_DPHY>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_MIPI_DSI>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#phy-cells = <0>;
+		};
+
 		fe0: display-frontend@01e00000 {
 			compatible = "allwinner,sun8i-a33-display-frontend";
 			reg = <0x01e00000 0x20000>;
-- 
git-series 0.9.1

[PATCH 17/18] arm: dts: sun8i: Add BananaPI M2-Magic DTS

[Maxime Ripard]

The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
DSI, CSI and GPIOs.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/Makefile                   |   1 +-
 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 321 ++++++++++++++++++++-
 2 files changed, 322 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4b17f35dc9a7..e0d77ab79f5f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -918,6 +918,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
+	sun8i-r16-bananapi-m2m.dtb \
 	sun8i-r16-parrot.dtb \
 	sun8i-v3s-licheepi-zero.dtb \
 	sun8i-v3s-licheepi-zero-dock.dtb
diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
new file mode 100644
index 000000000000..eaf09666720d
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) 2017 Free Electrons <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BananaPi M2 Magic";
+	compatible = "sinovoip,bananapi-m2m", "allwinner,sun8i-a33";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue {
+			label = "bpi-m2m:blue:usr";
+			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
+		};
+
+		green {
+			label = "bpi-m2m:green:usr";
+			gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
+		};
+
+		red {
+			label = "bpi-m2m:red:power";
+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	reg_vcc5v0: vcc5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	wifi_pwrseq: wifi_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+	};
+};
+
+&codec {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc3>;
+};
+
+&cpu0_opp_table {
+	opp@1104000000 {
+		opp-hz = /bits/ 64 <1104000000>;
+		opp-microvolt = <1320000>;
+		clock-latency-ns = <244144>; /* 8 32k periods */
+	};
+
+	opp@1200000000 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <1320000>;
+		clock-latency-ns = <244144>; /* 8 32k periods */
+	};
+};
+
+&dai {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+/* This is the i2c bus exposed on the DSI connector for the touch panel */
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "disabled";
+};
+
+/* This is the i2c bus exposed on the GPIO header */
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "disabled";
+};
+
+/* This is the i2c bus exposed on the CSI connector to control the sensor */
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins_a>;
+	status = "disabled";
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <4>;
+	cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+	cd-inverted;
+	status = "okay";
+};
+
+&mmc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins_a>;
+	vmmc-supply = <&reg_aldo1>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_8bit_pins>;
+	vmmc-supply = <&reg_dcdc1>;
+	bus-width = <8>;
+	non-removable;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp22x: pmic@3a3 {
+		compatible = "x-powers,axp223";
+		reg = <0x3a3>;
+		interrupt-parent = <&nmi_intc>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		eldoin-supply = <&reg_dcdc1>;
+		x-powers,drive-vbus-en;
+	};
+};
+
+#include "axp223.dtsi"
+
+&ac_power_supply {
+	status = "okay";
+};
+
+&reg_aldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <2500000>;
+	regulator-max-microvolt = <2500000>;
+	regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_dc1sw {
+	regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <900000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+	regulator-always-on;
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+	regulator-name = "vcc-dram";
+};
+
+/*
+ * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same
+ * time, with the two being in sync. Since this is not really
+ * supported right now, just use the two as always on, and we will fix
+ * it later.
+ */
+&reg_dldo1 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi1";
+};
+
+&reg_drivevbus {
+	regulator-name = "usb0-vbus";
+	status = "okay";
+};
+
+&reg_rtc_ldo {
+	regulator-name = "vcc-rtc";
+};
+
+&sound {
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus_power-supply = <&usb_power_supply>;
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb1_vbus-supply = <&reg_vcc5v0>;
+	status = "okay";
+};
-- 
git-series 0.9.1

[PATCH 18/18] [DO NOT MERGE] arm: dts: sun8i: bpi-m2m: Add DSI display

[Maxime Ripard]

The BananaPi M2M has an optional 1280x720 DSI panel. Since that panel is
optional, we can only show a DT patch that would show how to enable it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 39 +++++++++++++++++++++-
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index eaf09666720d..11a4dfde2679 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -44,6 +44,7 @@
 #include "sun8i-a33.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
 
 / {
 	model = "BananaPi M2 Magic";
@@ -81,6 +82,14 @@
 		};
 	};
 
+	pwm_bl: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <1 2 4 8 16 32 64 128 255>;
+		default-brightness-level = <8>;
+		enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PG10 */
+	};
+
 	reg_vcc5v0: vcc5v0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0";
@@ -120,6 +129,26 @@
 	status = "okay";
 };
 
+&de {
+	status = "okay";
+};
+
+&dphy0 {
+	status = "okay";
+};
+
+&dsi0 {
+	status = "okay";
+
+	panel@0 {
+		compatible = "huarui,lhr050h41";
+		reg = <0>;
+		power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
+		reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
+		backlight = <&pwm_bl>;
+	};
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -179,6 +208,12 @@
 	status = "okay";
 };
 
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins>;
+	status = "okay";
+};
+
 &r_rsb {
 	status = "okay";
 
@@ -291,6 +326,10 @@
 	status = "okay";
 };
 
+&tcon0 {
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_b>;
-- 
git-series 0.9.1

Re: [PATCH 01/18] regmap: mmio: Add function to attach a clock

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 295 bytes --]

On Thu, Jul 13, 2017 at 04:12:56PM +0200, Maxime Ripard wrote:

> This might be problematic if the clock to enable is stored in another node.
> Let's add a function that allows to attach a clock that has already been
> retrieved to a regmap in order to fix this.

What is the use case for this?

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 02/18] drm/sun4i: Add if statement instead of depends on

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The depends on relationship is obvious, and using an if statement will
> propagate it to every option without the need for each and every one of
> them to define it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH 03/18] drm/sun4i: Realign Makefile padding and reorder it

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some options were not padded as they should, and the order in the Makefile
> was chaotic. Fix that.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/gpu/drm/sun4i/Makefile | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
> index e29fd3a2ba9c..42871ee7acf6 100644
> --- a/drivers/gpu/drm/sun4i/Makefile
> +++ b/drivers/gpu/drm/sun4i/Makefile
> @@ -1,23 +1,23 @@
> -sun4i-drm-y += sun4i_drv.o
> -sun4i-drm-y += sun4i_framebuffer.o
> +sun4i-backend-y                        += sun4i_backend.o sun4i_layer.o
>
> -sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
> -sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
> -sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
> +sun4i-drm-y                    += sun4i_drv.o
> +sun4i-drm-y                    += sun4i_framebuffer.o

I don't think this applies on top of Jonathan's HDMI I2C patch
you already have queued up.

Also you might want to leave a comment describe what the
ordering should be. Otherwise it will still be messed up
down the road.

ChenYu

>
> -sun4i-tcon-y += sun4i_tcon.o
> -sun4i-tcon-y += sun4i_rgb.o
> -sun4i-tcon-y += sun4i_dotclock.o
> -sun4i-tcon-y += sun4i_crtc.o
> +sun4i-drm-hdmi-y               += sun4i_hdmi_enc.o
> +sun4i-drm-hdmi-y               += sun4i_hdmi_ddc_clk.o
> +sun4i-drm-hdmi-y               += sun4i_hdmi_tmds_clk.o
>
> -sun4i-backend-y += sun4i_backend.o sun4i_layer.o
> +sun4i-tcon-y                   += sun4i_tcon.o
> +sun4i-tcon-y                   += sun4i_rgb.o
> +sun4i-tcon-y                   += sun4i_dotclock.o
> +sun4i-tcon-y                   += sun4i_crtc.o
>
> -sun8i-mixer-y += sun8i_mixer.o sun8i_layer.o
> +sun8i-mixer-y                  += sun8i_mixer.o sun8i_layer.o
>
>  obj-$(CONFIG_DRM_SUN4I)                += sun4i-drm.o sun4i-tcon.o
>  obj-$(CONFIG_DRM_SUN4I)                += sun6i_drc.o
>  obj-$(CONFIG_DRM_SUN4I)                += sun4i_tv.o
>
> -obj-$(CONFIG_DRM_SUN4I_BACKEND)                += sun4i-backend.o
> +obj-$(CONFIG_DRM_SUN4I_BACKEND)        += sun4i-backend.o
>  obj-$(CONFIG_DRM_SUN4I_HDMI)   += sun4i-drm-hdmi.o
> -obj-$(CONFIG_DRM_SUN8I_MIXER)          += sun8i-mixer.o
> +obj-$(CONFIG_DRM_SUN8I_MIXER)  += sun8i-mixer.o
> --
> git-series 0.9.1

Re: [PATCH 04/18] drm/sun4i: Remove useless atomic_check

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The atomic_check callback is optional, and we don't implement anything in
> some parts of our drivers. Let's remove it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH 05/18] drm/sun4i: tcon: remove unused function

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Even though that function is defined in the TCON header, it's not defined
> nor used anywhere. Remove the prototype.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH 06/18] drm/sun4i: tcon: Don't rely on encoders to enable the TCON

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> So far, we've required all the TCON-connected encoders to call the TCON
> enable and disable functions.
>
> This was made this way because in the RGB/LVDS case, the TCON is the CRTC
> and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
> have another encoder down the road that needs to be programmed.
>
> We also needed to know which channel the encoder is connected to, which is
> encoder-specific.
>
> The CRTC's enable and disable callbacks can work just fine for our use
> case, and we can get the channel to use just by looking at the type of
> encoder, since that is fixed. Implement those callbacks, which will
> remove some of the encoder boilerplate.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Overall this looks good. A few minor comments below.

> ---
>  drivers/gpu/drm/sun4i/sun4i_crtc.c     | 22 ++++++-
>  drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c |  8 +--
>  drivers/gpu/drm/sun4i/sun4i_rgb.c      | 14 +---
>  drivers/gpu/drm/sun4i/sun4i_tcon.c     | 91 +++++++++++++--------------
>  drivers/gpu/drm/sun4i/sun4i_tcon.h     | 10 +---
>  drivers/gpu/drm/sun4i/sun4i_tv.c       |  6 +--
>  6 files changed, 70 insertions(+), 81 deletions(-)
>

[...]

>  static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index d9791292553e..dc70bc2a42a5 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -14,6 +14,7 @@
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_crtc.h>
>  #include <drm/drm_crtc_helper.h>
> +#include <drm/drm_encoder.h>
>  #include <drm/drm_modes.h>
>  #include <drm/drm_of.h>
>
> @@ -32,66 +33,62 @@
>  #include "sun4i_tcon.h"
>  #include "sunxi_engine.h"
>
> -void sun4i_tcon_disable(struct sun4i_tcon *tcon)
> +static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
> +                                         bool enabled)
>  {
> -       DRM_DEBUG_DRIVER("Disabling TCON\n");
> +       struct clk *clk;
>
> -       /* Disable the TCON */
> -       regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
> -                          SUN4I_TCON_GCTL_TCON_ENABLE, 0);
> -}
> -EXPORT_SYMBOL(sun4i_tcon_disable);
> -
> -void sun4i_tcon_enable(struct sun4i_tcon *tcon)
> -{
> -       DRM_DEBUG_DRIVER("Enabling TCON\n");
> -
> -       /* Enable the TCON */
> -       regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
> -                          SUN4I_TCON_GCTL_TCON_ENABLE,
> -                          SUN4I_TCON_GCTL_TCON_ENABLE);
> -}
> -EXPORT_SYMBOL(sun4i_tcon_enable);
> -
> -void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
> -{
> -       DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
> -
> -       /* Disable the TCON's channel */
> -       if (channel == 0) {
> +       switch (channel) {
> +       case 0:
>                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
> -                                  SUN4I_TCON0_CTL_TCON_ENABLE, 0);
> -               clk_disable_unprepare(tcon->dclk);
> +                                  SUN4I_TCON0_CTL_TCON_ENABLE,
> +                                  enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
> +               clk = tcon->dclk;
> +               break;
> +       case 1:
> +               WARN_ON(!tcon->quirks->has_channel_1);
> +               regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
> +                                  SUN4I_TCON1_CTL_TCON_ENABLE,
> +                                  enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
> +               clk = tcon->sclk1;
> +               break;
> +       default:
> +               DRM_DEBUG_DRIVER("Unknown channel... doing nothing\n");
>                 return;
>         }
>
> -       WARN_ON(!tcon->quirks->has_channel_1);
> -       regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
> -                          SUN4I_TCON1_CTL_TCON_ENABLE, 0);
> -       clk_disable_unprepare(tcon->sclk1);
> +       if (enabled)
> +               clk_prepare_enable(clk);

I wonder if it's better to enable the clk before the TCON?

> +       else
> +               clk_disable_unprepare(clk);
>  }
> -EXPORT_SYMBOL(sun4i_tcon_channel_disable);
>
> -void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
> +void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
> +                          struct drm_encoder *encoder,
> +                          bool enabled)
>  {
> -       DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
> -
> -       /* Enable the TCON's channel */
> -       if (channel == 0) {
> -               regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
> -                                  SUN4I_TCON0_CTL_TCON_ENABLE,
> -                                  SUN4I_TCON0_CTL_TCON_ENABLE);
> -               clk_prepare_enable(tcon->dclk);
> +       int channel;
> +
> +       switch (encoder->encoder_type) {
> +       case DRM_MODE_ENCODER_NONE:
> +               channel = 0;
> +               break;
> +       case DRM_MODE_ENCODER_TMDS:
> +       case DRM_MODE_ENCODER_TVDAC:
> +               channel = 1;
> +               break;
> +       default:
> +               DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");

We could simply add all the possible types, and print a big warning
if someone does something unexpected. IMHO this is better than having
the user enable some hidden debug flag to figure why the display isn't
working properly.

>                 return;
>         }
>
> -       WARN_ON(!tcon->quirks->has_channel_1);
> -       regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
> -                          SUN4I_TCON1_CTL_TCON_ENABLE,
> -                          SUN4I_TCON1_CTL_TCON_ENABLE);
> -       clk_prepare_enable(tcon->sclk1);
> +       sun4i_tcon_channel_set_status(tcon, channel, enabled);
> +
> +       regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
> +                          SUN4I_TCON_GCTL_TCON_ENABLE,
> +                          enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);

The global enable bit should be set first.

Also the manual says "When it’s disabled, the module will be reset to
idle state."
so you might get away with just disabling the global enable bit and returning
directly after disabling the clock?

>  }
> -EXPORT_SYMBOL(sun4i_tcon_channel_enable);
> +EXPORT_SYMBOL(sun4i_tcon_set_status);

The TCON and CRTC code are part of the same module.
There is no need to export this function.

ChenYu

>
>  void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
>  {
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
> index 552c88ec16be..824732c90a2a 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
> @@ -183,15 +183,9 @@ struct sun4i_tcon {
>  struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
>  struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
>
> -/* Global Control */
> -void sun4i_tcon_disable(struct sun4i_tcon *tcon);
> -void sun4i_tcon_enable(struct sun4i_tcon *tcon);
> -
> -/* Channel Control */
> -void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel);
> -void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel);
> -
>  void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
> +void sun4i_tcon_set_status(struct sun4i_tcon *crtc, struct drm_encoder *encoder,
> +                          bool enable);
>
>  /* Mode Related Controls */
>  void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
> index 73bfe7b1cd78..78d6cf77fdd3 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tv.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
> @@ -345,12 +345,9 @@ static void sun4i_tv_disable(struct drm_encoder *encoder)
>  {
>         struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
>         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
> -       struct sun4i_tcon *tcon = crtc->tcon;
>
>         DRM_DEBUG_DRIVER("Disabling the TV Output\n");
>
> -       sun4i_tcon_channel_disable(tcon, 1);
> -
>         regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
>                            SUN4I_TVE_EN_ENABLE,
>                            0);
> @@ -362,7 +359,6 @@ static void sun4i_tv_enable(struct drm_encoder *encoder)
>  {
>         struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
>         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
> -       struct sun4i_tcon *tcon = crtc->tcon;
>
>         DRM_DEBUG_DRIVER("Enabling the TV Output\n");
>
> @@ -371,8 +367,6 @@ static void sun4i_tv_enable(struct drm_encoder *encoder)
>         regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
>                            SUN4I_TVE_EN_ENABLE,
>                            SUN4I_TVE_EN_ENABLE);
> -
> -       sun4i_tcon_channel_enable(tcon, 1);
>  }
>
>  static void sun4i_tv_mode_set(struct drm_encoder *encoder,
> --
> git-series 0.9.1

Re: [PATCH 07/18] drm/sun4i: tcon: Don't rely on encoders to set the TCON mode

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Just like we did for the TCON enable and disable, for historical reasons we
> used to rely on the encoders calling the TCON mode_set function, while the
> CRTC has a callback for that.
>
> Let's implement it in order to reduce the boilerplate code.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/gpu/drm/sun4i/sun4i_crtc.c          | 11 ++++-
>  drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c  |  1 +-
>  drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c      |  7 +---
>  drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c |  1 +-
>  drivers/gpu/drm/sun4i/sun4i_rgb.c           | 15 +------
>  drivers/gpu/drm/sun4i/sun4i_tcon.c          | 56 ++++++++++------------
>  drivers/gpu/drm/sun4i/sun4i_tcon.h          | 10 +----
>  drivers/gpu/drm/sun4i/sun4i_tv.c            |  6 +--
>  8 files changed, 40 insertions(+), 67 deletions(-)
>

[...]

> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index dc70bc2a42a5..c4407910dfaf 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -106,29 +106,6 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
>  }
>  EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
>
> -void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
> -                       struct drm_encoder *encoder)
> -{
> -       u32 val;
> -
> -       if (!tcon->quirks->has_unknown_mux)
> -               return;
> -
> -       if (channel != 1)
> -               return;
> -
> -       if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
> -               val = 1;
> -       else
> -               val = 0;
> -
> -       /*
> -        * FIXME: Undocumented bits
> -        */
> -       regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
> -}
> -EXPORT_SYMBOL(sun4i_tcon_set_mux);
> -
>  static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
>                                     int channel)
>  {
> @@ -147,8 +124,8 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
>         return delay;
>  }
>
> -void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> -                         struct drm_display_mode *mode)
> +static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> +                                struct drm_display_mode *mode)

Nit on the side: maybe we could mark mode as constant?
Since the function doesn't change it. Same applies to the
other mode_set functions. But this could be left to another
patch.

>  {
>         unsigned int bp, hsync, vsync;
>         u8 clk_delay;
> @@ -221,10 +198,9 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
>         /* Enable the output on the pins */
>         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
>  }
> -EXPORT_SYMBOL(sun4i_tcon0_mode_set);
>
> -void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
> -                         struct drm_display_mode *mode)
> +static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
> +                                struct drm_display_mode *mode)
>  {
>         unsigned int bp, hsync, vsync, vtotal;
>         u8 clk_delay;
> @@ -312,7 +288,29 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
>                            SUN4I_TCON_GCTL_IOMAP_MASK,
>                            SUN4I_TCON_GCTL_IOMAP_TCON1);
>  }
> -EXPORT_SYMBOL(sun4i_tcon1_mode_set);
> +
> +void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
> +                        struct drm_display_mode *mode)

(also mark encoder as const?)

> +{
> +       switch (encoder->encoder_type) {
> +       case DRM_MODE_ENCODER_NONE:
> +               sun4i_tcon0_mode_set(tcon, mode);
> +               break;
> +       case DRM_MODE_ENCODER_TVDAC:
> +               /*
> +                * FIXME: Undocumented bits
> +                */
> +               if (tcon->quirks->has_unknown_mux)
> +                       regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
> +               /* Fallthrough */
> +       case DRM_MODE_ENCODER_TMDS:
> +               sun4i_tcon1_mode_set(tcon, mode);

IIRC you need to clear the mux bit here. So ...

> +               break;
> +       default:
> +               DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
> +       }

I think keeping the muxing in a separate function would be cleaner.
The above is already slightly messy if you add the bit clearing part.
With all the other muxing possibilities in the other SoC this is
going to get really messy.

> +}
> +EXPORT_SYMBOL(sun4i_tcon_mode_set);
>
>  static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
>                                         struct sun4i_crtc *scrtc)

[...]

Thanks for working on this. Now we've decoupled the TCON/CRTC code
from all the encoders.

Regards
ChenYu

Re: [PATCH 08/18] drm/sun4i: tcon: Add TRI finish interrupt for vblank

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The "CPU" (or Intel 8080) interface uses a different interrupt called
> TRI_FINISH (most likely TRI being for trigger) to notify the end of frames,
> and hence the VBLANK period.
>
> And that interrupt to the possible VBLANK interrupts source.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH 09/18] drm/sun4i: tcon: Adjust dotclock dividers range

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> It seems like the dotclock dividers are a bit less strict range, and can
> operate even with a smaller than 6 divider. Loose the boundaries a bit.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> index d401156490f3..0b844c0dd102 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> @@ -77,7 +77,25 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
>         u8 best_div = 1;
>         int i;
>
> -       for (i = 6; i <= 127; i++) {
> +       /*
> +        * There's something odd here.
> +        *
> +        * In the A13 user manual, this is stated to be >= 6 when
> +        * dclk1 and dclk2 are used (without any hint on how to use
> +        * them), and >= 4 when only dclk is used.

You set it in TCON0_IO_POL_REG, which sets the clock phase delay.
I think we were setting this before, but you removed it as part of
the previous TCON clean up patches?

In the A33, there are even more options, like DCLK / 2 (with 0 or 90
degree phase delay).

> +        *
> +        * In the A33 user manual, when only dclk is used, it is set
> +        * to be >= 6 in the former case, and >= 1 in the
> +        * latter. There's also some (obscure) explanations about the
> +        * dclk1 and dclk2 vs dclk that seems to be in the upper 4
> +        * bits. What those clocks are and what bit does what is not
> +        * really clear.

Looks like mux bits to me. How they differ from TCON0_IO_POL_REG is
beyond me ATM.

ChenYu

> +        *
> +        * On the A33 however, while something lower than 4 works, it
> +        * does have a few artifacts. Let's not use those values, and
> +        * see how it goes.
> +        */
> +       for (i = 4; i <= 127; i++) {
>                 unsigned long ideal = rate * i;
>                 unsigned long rounded;
>
> --
> git-series 0.9.1

Re: [PATCH 17/18] arm: dts: sun8i: Add BananaPI M2-Magic DTS

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
> connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
> DSI, CSI and GPIOs.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Has BPI publicly released the schematics and/or FEX file yet?

Re: [PATCH 13/18] dt-bindings: vendor: Add Huarui Lighting

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Huarui Lighting makes display panel, add it to the list of panels.

I could not find any information on "Huarui Lighting" within the
context of LCD panels. The company I found makes LED lighting
fixtures, floodlights, and high power LED drivers.

This might not be a legitimate branding?

ChenYu

>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index afbb47ce50dd..cc5850a325f8 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -142,6 +142,7 @@ holt        Holt Integrated Circuits, Inc.
>  honeywell      Honeywell
>  hp     Hewlett Packard
>  holtek Holtek Semiconductor, Inc.
> +huarui Huarui Lighting Co. Ltd
>  hwacom HwaCom Systems Inc.
>  i2se   I2SE GmbH
>  ibm    International Business Machines (IBM)
> --
> git-series 0.9.1

Re: [PATCH 15/18] drm/panel: Add Huarui LHR050H41 panel driver

[Andrzej Hajda]

On 13.07.2017 16:13, Maxime Ripard wrote:
> The LHR050H41 panel is the panel shipped with the BananaPi M2-Magic. Add a
> driver for it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/gpu/drm/panel/Kconfig                  |   9 +-
>  drivers/gpu/drm/panel/Makefile                 |   1 +-
>  drivers/gpu/drm/panel/panel-huarui-lhr050h41.c | 444 ++++++++++++++++++-
>  3 files changed, 454 insertions(+)
>  create mode 100644 drivers/gpu/drm/panel/panel-huarui-lhr050h41.c
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index d84a031fae24..eaa6e102775a 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -28,6 +28,15 @@ config DRM_PANEL_SIMPLE
>  	  that it can be automatically turned off when the panel goes into a
>  	  low power state.
>  
> +config DRM_PANEL_HUARUI_LHR050H41
> +	tristate "Huarui LHR050H41 panel"
> +	depends on OF
> +	depends on DRM_MIPI_DSI
> +	depends on BACKLIGHT_CLASS_DEVICE
> +	help
> +	  Say Y if you want to enable support for the Huarui Lighting
> +	  LHR05041 DSI panel. The panel has a 1280x720 resolution.
> +
>  config DRM_PANEL_INNOLUX_P079ZCA
>  	tristate "Innolux P079ZCA panel"
>  	depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index 9f6610d08b00..58de7a853898 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
>  obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
> +obj-$(CONFIG_DRM_PANEL_HUARUI_LHR050H41) += panel-huarui-lhr050h41.o
>  obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
>  obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
>  obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
> diff --git a/drivers/gpu/drm/panel/panel-huarui-lhr050h41.c b/drivers/gpu/drm/panel/panel-huarui-lhr050h41.c
> new file mode 100644
> index 000000000000..eb675eb9ee7d
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-huarui-lhr050h41.c
> @@ -0,0 +1,444 @@

No copyright/license/description at the beginning of the file.


> +#include <linux/backlight.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/fb.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +
> +#include <linux/gpio/consumer.h>

It can be put in alphabetical order.

> +
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_modes.h>
> +#include <drm/drm_panel.h>
> +
> +#include <video/mipi_display.h>
> +
> +struct lhr050h41 {
> +	struct drm_panel	panel;
> +	struct mipi_dsi_device	*dsi;
> +
> +	struct backlight_device *backlight;
> +	struct gpio_desc	*power;
> +	struct gpio_desc	*reset;
> +};
> +
> +static inline struct lhr050h41 *panel_to_lhr050h41(struct drm_panel *panel)
> +{
> +	return container_of(panel, struct lhr050h41, panel);
> +}
> +
> +static int lhr050h41_switch_page(struct lhr050h41 *ctx, u8 page)
> +{
> +	u8 buf[4] = { 0xff, 0x98, 0x81, page };
> +
> +	return mipi_dsi_dcs_write_buffer(ctx->dsi, buf, sizeof(buf));
> +}
> +
> +static int lhr050h41_send_cmd_data(struct lhr050h41 *ctx, u8 cmd, u8 data)
> +{
> +	u8 buf[2] = { cmd, data };
> +
> +	return mipi_dsi_dcs_write_buffer(ctx->dsi, buf, sizeof(buf));
> +}
> +
> +static int lhr050h41_send_init_sequence(struct lhr050h41 *ctx)
> +{
> +	lhr050h41_switch_page(ctx, 3);

No error checking, here and below in most places.

> +
> +	lhr050h41_send_cmd_data(ctx, 0x01, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x02, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x03, 0x73);
> +	lhr050h41_send_cmd_data(ctx, 0x04, 0x03);
> +	lhr050h41_send_cmd_data(ctx, 0x05, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x06, 0x06);
> +	lhr050h41_send_cmd_data(ctx, 0x07, 0x06);
> +	lhr050h41_send_cmd_data(ctx, 0x08, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x09, 0x18);
> +	lhr050h41_send_cmd_data(ctx, 0x0a, 0x04);
> +	lhr050h41_send_cmd_data(ctx, 0x0b, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x0c, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x0d, 0x03);
> +	lhr050h41_send_cmd_data(ctx, 0x0e, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x0f, 0x25);
> +	lhr050h41_send_cmd_data(ctx, 0x10, 0x25);
> +	lhr050h41_send_cmd_data(ctx, 0x11, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x12, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x13, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x14, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x15, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x16, 0x0C);
> +	lhr050h41_send_cmd_data(ctx, 0x17, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x18, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x19, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x1a, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x1b, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x1c, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x1d, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x1e, 0xC0);
> +	lhr050h41_send_cmd_data(ctx, 0x1f, 0x80);
> +	lhr050h41_send_cmd_data(ctx, 0x20, 0x04);
> +	lhr050h41_send_cmd_data(ctx, 0x21, 0x01);
> +	lhr050h41_send_cmd_data(ctx, 0x22, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x23, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x24, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x25, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x26, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x27, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x28, 0x33);
> +	lhr050h41_send_cmd_data(ctx, 0x29, 0x03);
> +	lhr050h41_send_cmd_data(ctx, 0x2a, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x2b, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x2c, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x2d, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x2e, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x2f, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x30, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x31, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x32, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x33, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x34, 0x04);
> +	lhr050h41_send_cmd_data(ctx, 0x35, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x36, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x37, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x38, 0x3C);
> +	lhr050h41_send_cmd_data(ctx, 0x39, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x3a, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x3b, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x3c, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x3d, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x3e, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x3f, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x40, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x41, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x42, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x43, 0x00);
> +	lhr050h41_send_cmd_data(ctx, 0x44, 0x00);
> +
> +	lhr050h41_send_cmd_data(ctx, 0x50, 0x01);
> +	lhr050h41_send_cmd_data(ctx, 0x51, 0x23);
> +	lhr050h41_send_cmd_data(ctx, 0x52, 0x45);
> +	lhr050h41_send_cmd_data(ctx, 0x53, 0x67);
> +	lhr050h41_send_cmd_data(ctx, 0x54, 0x89);
> +	lhr050h41_send_cmd_data(ctx, 0x55, 0xab);
> +	lhr050h41_send_cmd_data(ctx, 0x56, 0x01);
> +	lhr050h41_send_cmd_data(ctx, 0x57, 0x23);
> +	lhr050h41_send_cmd_data(ctx, 0x58, 0x45);
> +	lhr050h41_send_cmd_data(ctx, 0x59, 0x67);
> +	lhr050h41_send_cmd_data(ctx, 0x5a, 0x89);
> +	lhr050h41_send_cmd_data(ctx, 0x5b, 0xab);
> +	lhr050h41_send_cmd_data(ctx, 0x5c, 0xcd);
> +	lhr050h41_send_cmd_data(ctx, 0x5d, 0xef);
> +
> +	lhr050h41_send_cmd_data(ctx, 0x5e, 0x11);
> +	lhr050h41_send_cmd_data(ctx, 0x5f, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x60, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x61, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x62, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x63, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x64, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x65, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x66, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x67, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x68, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x69, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x6a, 0x0C);
> +	lhr050h41_send_cmd_data(ctx, 0x6b, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x6c, 0x0F);
> +	lhr050h41_send_cmd_data(ctx, 0x6d, 0x0E);
> +	lhr050h41_send_cmd_data(ctx, 0x6e, 0x0D);
> +	lhr050h41_send_cmd_data(ctx, 0x6f, 0x06);
> +	lhr050h41_send_cmd_data(ctx, 0x70, 0x07);
> +	lhr050h41_send_cmd_data(ctx, 0x71, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x72, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x73, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x74, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x75, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x76, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x77, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x78, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x79, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x7a, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x7b, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x7c, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x7d, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x7e, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x7f, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x80, 0x0C);
> +	lhr050h41_send_cmd_data(ctx, 0x81, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x82, 0x0F);
> +	lhr050h41_send_cmd_data(ctx, 0x83, 0x0E);
> +	lhr050h41_send_cmd_data(ctx, 0x84, 0x0D);
> +	lhr050h41_send_cmd_data(ctx, 0x85, 0x06);
> +	lhr050h41_send_cmd_data(ctx, 0x86, 0x07);
> +	lhr050h41_send_cmd_data(ctx, 0x87, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x88, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x89, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x8A, 0x02);
> +
> +	lhr050h41_switch_page(ctx, 4);
> +	lhr050h41_send_cmd_data(ctx, 0x6C, 0x15);
> +	lhr050h41_send_cmd_data(ctx, 0x6E, 0x22);
> +	lhr050h41_send_cmd_data(ctx, 0x6F, 0x33);
> +	lhr050h41_send_cmd_data(ctx, 0x3A, 0xA4);
> +	lhr050h41_send_cmd_data(ctx, 0x8D, 0x0D);
> +	lhr050h41_send_cmd_data(ctx, 0x87, 0xBA);
> +	lhr050h41_send_cmd_data(ctx, 0x26, 0x76);
> +	lhr050h41_send_cmd_data(ctx, 0xB2, 0xD1);
> +
> +	lhr050h41_switch_page(ctx, 1);
> +	lhr050h41_send_cmd_data(ctx, 0x22, 0x0A);
> +	lhr050h41_send_cmd_data(ctx, 0x53, 0xDC);
> +	lhr050h41_send_cmd_data(ctx, 0x55, 0xA7);
> +	lhr050h41_send_cmd_data(ctx, 0x50, 0x78);
> +	lhr050h41_send_cmd_data(ctx, 0x51, 0x78);
> +	lhr050h41_send_cmd_data(ctx, 0x31, 0x02);
> +	lhr050h41_send_cmd_data(ctx, 0x60, 0x14);
> +	lhr050h41_send_cmd_data(ctx, 0xA0, 0x2A);
> +	lhr050h41_send_cmd_data(ctx, 0xA1, 0x39);
> +	lhr050h41_send_cmd_data(ctx, 0xA2, 0x46);
> +	lhr050h41_send_cmd_data(ctx, 0xA3, 0x0e);
> +	lhr050h41_send_cmd_data(ctx, 0xA4, 0x12);
> +	lhr050h41_send_cmd_data(ctx, 0xA5, 0x25);
> +	lhr050h41_send_cmd_data(ctx, 0xA6, 0x19);
> +	lhr050h41_send_cmd_data(ctx, 0xA7, 0x1d);
> +	lhr050h41_send_cmd_data(ctx, 0xA8, 0xa6);
> +	lhr050h41_send_cmd_data(ctx, 0xA9, 0x1C);
> +	lhr050h41_send_cmd_data(ctx, 0xAA, 0x29);
> +	lhr050h41_send_cmd_data(ctx, 0xAB, 0x85);
> +	lhr050h41_send_cmd_data(ctx, 0xAC, 0x1C);
> +	lhr050h41_send_cmd_data(ctx, 0xAD, 0x1B);
> +	lhr050h41_send_cmd_data(ctx, 0xAE, 0x51);
> +	lhr050h41_send_cmd_data(ctx, 0xAF, 0x22);
> +	lhr050h41_send_cmd_data(ctx, 0xB0, 0x2d);
> +	lhr050h41_send_cmd_data(ctx, 0xB1, 0x4f);
> +	lhr050h41_send_cmd_data(ctx, 0xB2, 0x59);
> +	lhr050h41_send_cmd_data(ctx, 0xB3, 0x3F);
> +	lhr050h41_send_cmd_data(ctx, 0xC0, 0x2A);
> +	lhr050h41_send_cmd_data(ctx, 0xC1, 0x3a);
> +	lhr050h41_send_cmd_data(ctx, 0xC2, 0x45);
> +	lhr050h41_send_cmd_data(ctx, 0xC3, 0x0e);
> +	lhr050h41_send_cmd_data(ctx, 0xC4, 0x11);
> +	lhr050h41_send_cmd_data(ctx, 0xC5, 0x24);
> +	lhr050h41_send_cmd_data(ctx, 0xC6, 0x1a);
> +	lhr050h41_send_cmd_data(ctx, 0xC7, 0x1c);
> +	lhr050h41_send_cmd_data(ctx, 0xC8, 0xaa);
> +	lhr050h41_send_cmd_data(ctx, 0xC9, 0x1C);
> +	lhr050h41_send_cmd_data(ctx, 0xCA, 0x29);
> +	lhr050h41_send_cmd_data(ctx, 0xCB, 0x96);
> +	lhr050h41_send_cmd_data(ctx, 0xCC, 0x1C);
> +	lhr050h41_send_cmd_data(ctx, 0xCD, 0x1B);
> +	lhr050h41_send_cmd_data(ctx, 0xCE, 0x51);
> +	lhr050h41_send_cmd_data(ctx, 0xCF, 0x22);
> +	lhr050h41_send_cmd_data(ctx, 0xD0, 0x2b);
> +	lhr050h41_send_cmd_data(ctx, 0xD1, 0x4b);
> +	lhr050h41_send_cmd_data(ctx, 0xD2, 0x59);
> +	lhr050h41_send_cmd_data(ctx, 0xD3, 0x3F);

I think you can put all above codes into some array and call it in loop,
with error checking.

> +
> +	lhr050h41_switch_page(ctx, 0);
> +	lhr050h41_send_cmd_data(ctx, 0x35, 0x00);

mipi_dsi_dcs_set_tear_on

> +	lhr050h41_send_cmd_data(ctx, 0x11, 0x00);

mipi_dsi_dcs_exit_sleep_mode

> +
> +	mdelay(120);
I think it should be moved to enable callback, more about it below.
> +
> +	lhr050h41_send_cmd_data(ctx, 0x29, 0x00);

mipi_dsi_dcs_set_display_on

> +
> +	mdelay(20);
> +
> +	return 0;
> +}
> +
> +static int lhr050h41_prepare(struct drm_panel *panel)
> +{
> +	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
> +
> +	/* Power the panel */
> +	gpiod_set_value(ctx->power, 1);
> +	mdelay(5);
> +
> +	/* And reset it */
> +	gpiod_set_value(ctx->reset, 1);
> +	mdelay(20);
> +
> +	gpiod_set_value(ctx->reset, 0);
> +	mdelay(20);
> +
> +	lhr050h41_send_init_sequence(ctx);
> +
> +	return 0;
> +}
> +
> +static void lhr050h41_enable_bl(struct lhr050h41 *ctx, bool enable)
> +{
> +	if (!ctx->backlight)
> +		return;
> +
> +	if (enable) {
> +		ctx->backlight->props.state &= ~BL_CORE_FBBLANK;
> +		ctx->backlight->props.power = FB_BLANK_UNBLANK;
> +	} else {
> +		ctx->backlight->props.power = FB_BLANK_POWERDOWN;
> +		ctx->backlight->props.state |= BL_CORE_FBBLANK;
> +	}
> +
> +	backlight_update_status(ctx->backlight);
> +}
> +
> +static int lhr050h41_enable(struct drm_panel *panel)
> +{
> +	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
> +
> +	lhr050h41_enable_bl(ctx, true);
> +
> +	return 0;
> +}

Usually purpose of mdelay(120) is to wait for finishing initialization
and transmission of first frames to the panel.
So I guess mdelay(120) and mipi_dsi_dcs_set_display_on should be moved
to _enable callback, otherwise you risk having garbage on the screen at
start.

> +
> +static int lhr050h41_disable(struct drm_panel *panel)
> +{
> +	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
> +
> +	lhr050h41_enable_bl(ctx, false);
> +
> +	return mipi_dsi_dcs_set_display_off(ctx->dsi);
> +}
> +
> +static int lhr050h41_unprepare(struct drm_panel *panel)
> +{
> +	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
> +
> +	mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
> +	gpiod_set_value(ctx->power, 0);
> +	gpiod_set_value(ctx->reset, 1);
> +
> +	return 0;
> +}
> +
> +static const struct drm_display_mode default_mode = {
> +	.clock		= 62000,
> +	.vrefresh	= 60,
> +
> +	.hdisplay	= 720,
> +	.hsync_start	= 720 + 10,
> +	.hsync_end	= 720 + 10 + 20,
> +	.htotal		= 720 + 10 + 20 + 30,
> +
> +	.vdisplay	= 1280,
> +	.vsync_start	= 1280 + 10,
> +	.vsync_end	= 1280 + 10 + 10,
> +	.vtotal		= 1280 + 10 + 10 + 20,
> +};
> +
> +static int lhr050h41_get_modes(struct drm_panel *panel)
> +{
> +	struct drm_connector *connector = panel->connector;
> +	struct lhr050h41 *ctx = panel_to_lhr050h41(panel);
> +	struct drm_display_mode *mode;
> +
> +	mode = drm_mode_duplicate(panel->drm, &default_mode);
> +	if (!mode) {
> +		dev_err(&ctx->dsi->dev, "failed to add mode %ux%ux@%u\n",
> +			default_mode.hdisplay, default_mode.vdisplay,
> +			default_mode.vrefresh);
> +		return -ENOMEM;
> +	}
> +
> +	drm_mode_set_name(mode);
> +
> +	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
> +	drm_mode_probed_add(connector, mode);
> +
> +	panel->connector->display_info.width_mm = 62;
> +	panel->connector->display_info.height_mm = 110;
> +
> +	return 1;
> +}
> +
> +static const struct drm_panel_funcs lhr050h41_funcs = {
> +	.prepare	= lhr050h41_prepare,
> +	.unprepare	= lhr050h41_unprepare,
> +	.enable		= lhr050h41_enable,
> +	.disable	= lhr050h41_disable,
> +	.get_modes	= lhr050h41_get_modes,
> +};
> +
> +static int lhr050h41_dsi_probe(struct mipi_dsi_device *dsi)
> +{
> +	struct device_node *np;
> +	struct lhr050h41 *ctx;
> +	int ret;
> +
> +	ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
> +	if (!ctx)
> +		return -ENOMEM;
> +	mipi_dsi_set_drvdata(dsi, ctx);
> +	ctx->dsi = dsi;
> +
> +	drm_panel_init(&ctx->panel);
> +	ctx->panel.dev = &dsi->dev;
> +	ctx->panel.funcs = &lhr050h41_funcs;
> +
> +	ctx->power = devm_gpiod_get(&dsi->dev, "power", GPIOD_OUT_LOW);
> +	if (IS_ERR(ctx->power)) {
> +		dev_err(&dsi->dev, "Couldn't get our power GPIO\n");
> +		return PTR_ERR(ctx->power);
> +	}
> +
> +	ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
> +	if (IS_ERR(ctx->reset)) {
> +		dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
> +		return PTR_ERR(ctx->reset);
> +	}
> +
> +	np = of_parse_phandle(dsi->dev.of_node, "backlight", 0);
> +	if (np) {
> +		ctx->backlight = of_find_backlight_by_node(np);
> +		of_node_put(np);
> +
> +		if (!ctx->backlight)
> +			return -EPROBE_DEFER;
> +	}
> +
> +	ret = drm_panel_add(&ctx->panel);
> +	if (ret < 0)
> +		return ret;
> +
> +	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE;

I guess MIPI_DSI_MODE_VIDEO should be also here.

Regards
Andrzej

> +	dsi->format = MIPI_DSI_FMT_RGB888;
> +	dsi->lanes = 4;
> +
> +	return mipi_dsi_attach(dsi);
> +}
> +
> +static int lhr050h41_dsi_remove(struct mipi_dsi_device *dsi)
> +{
> +	struct lhr050h41 *ctx = mipi_dsi_get_drvdata(dsi);
> +
> +	mipi_dsi_detach(dsi);
> +	drm_panel_remove(&ctx->panel);
> +
> +	if (ctx->backlight)
> +		put_device(&ctx->backlight->dev);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id lhr050h41_of_match[] = {
> +	{ .compatible = "huarui,lhr050h41" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, lhr050h41_of_match);
> +
> +static struct mipi_dsi_driver lhr050h41_dsi_driver = {
> +	.probe		= lhr050h41_dsi_probe,
> +	.remove		= lhr050h41_dsi_remove,
> +	.driver = {
> +		.name		= "lhr050h41-dsi",
> +		.of_match_table	= lhr050h41_of_match,
> +	},
> +};
> +module_mipi_dsi_driver(lhr050h41_dsi_driver);
> +
> +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
> +MODULE_DESCRIPTION("Huarui LHR050H41 LCD Driver");
> +MODULE_LICENSE("GPL v2");

Re: [PATCH 10/18] drm/sun4i: tcon: Move out the tcon0 common setup

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1826 bytes --]

Hi Maxime,

[auto build test ERROR on next-20170710]
[cannot apply to mripard/sunxi/for-next robh/for-next regmap/for-next v4.12 v4.12-rc7 v4.12-rc6 v4.12]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Maxime-Ripard/drm-sun4i-Allwinner-MIPI-DSI-support/20170714-123103
config: arm-sunxi_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/sun4i/sun4i_tcon.c: In function 'sun4i_tcon0_mode_set_common':
>> drivers/gpu/drm/sun4i/sun4i_tcon.c:132:2: error: implicit declaration of function 'clk_set_rate_protect' [-Werror=implicit-function-declaration]
     clk_set_rate_protect(tcon->dclk, mode->crtc_clock * 1000);
     ^~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/clk_set_rate_protect +132 drivers/gpu/drm/sun4i/sun4i_tcon.c

   127	
   128	static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
   129						struct drm_display_mode *mode)
   130	{
   131		/* Configure the dot clock */
 > 132		clk_set_rate_protect(tcon->dclk, mode->crtc_clock * 1000);
   133	
   134		/* Set the resolution */
   135		regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
   136			     SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
   137			     SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
   138	}
   139	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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Re: [PATCH 12/18] drm/sun4i: Add Allwinner A31 MIPI-DSI controller support

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 6384 bytes --]

Hi Maxime,

[auto build test ERROR on next-20170710]
[cannot apply to mripard/sunxi/for-next robh/for-next regmap/for-next v4.12 v4.12-rc7 v4.12-rc6 v4.12]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Maxime-Ripard/drm-sun4i-Allwinner-MIPI-DSI-support/20170714-123103
config: arm-sunxi_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c: In function 'sun6i_dphy_init':
>> drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c:92:2: error: implicit declaration of function 'clk_set_rate_protect' [-Werror=implicit-function-declaration]
     clk_set_rate_protect(dphy->mod_clk, 150000000);
     ^~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c: In function 'sun6i_dphy_exit':
>> drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c:199:2: error: implicit declaration of function 'clk_rate_unprotect' [-Werror=implicit-function-declaration]
     clk_rate_unprotect(dphy->mod_clk);
     ^~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c: In function 'sun6i_dsi_probe':
>> drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c:984:2: error: implicit declaration of function 'clk_set_rate_protect' [-Werror=implicit-function-declaration]
     clk_set_rate_protect(dsi->mod_clk, 297000000);
     ^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c:1016:2: error: implicit declaration of function 'clk_rate_unprotect' [-Werror=implicit-function-declaration]
     clk_rate_unprotect(dsi->mod_clk);
     ^~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/clk_set_rate_protect +92 drivers/gpu/drm/sun4i/sun6i_mipi_dphy.c

    87	
    88	int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes)
    89	{
    90		reset_control_deassert(dphy->reset);
    91		clk_prepare_enable(dphy->mod_clk);
  > 92		clk_set_rate_protect(dphy->mod_clk, 150000000);
    93	
    94		regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
    95			     SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
    96	
    97		regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
    98			     SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
    99			     SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
   100			     SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
   101	
   102		regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
   103			     SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
   104			     SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
   105			     SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
   106			     SUN6I_DPHY_TX_TIME1_CLK_POST(10));
   107	
   108		regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
   109			     SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
   110	
   111		regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
   112	
   113		regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
   114			     SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
   115			     SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
   116	
   117		/* FIXME: Number of lanes? */
   118		regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
   119			     SUN6I_DPHY_GCTL_LANE_NUM(lanes) |
   120			     SUN6I_DPHY_GCTL_EN);
   121	
   122		return 0;
   123	}
   124	
   125	int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes)
   126	{
   127		u8 lanes_mask = GENMASK(lanes - 1, 0);
   128	
   129		regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
   130			     SUN6I_DPHY_ANA0_REG_PWS |
   131			     SUN6I_DPHY_ANA0_REG_DMPC |
   132			     SUN6I_DPHY_ANA0_REG_SLV(7) |
   133			     SUN6I_DPHY_ANA0_REG_DMPD(lanes_mask) |
   134			     SUN6I_DPHY_ANA0_REG_DEN(lanes_mask));
   135	
   136		regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
   137			     SUN6I_DPHY_ANA1_REG_CSMPS(1) |
   138			     SUN6I_DPHY_ANA1_REG_SVTT(7));
   139	
   140		regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
   141			     SUN6I_DPHY_ANA4_REG_CKDV(1) |
   142			     SUN6I_DPHY_ANA4_REG_TMSC(1) |
   143			     SUN6I_DPHY_ANA4_REG_TMSD(1) |
   144			     SUN6I_DPHY_ANA4_REG_TXDNSC(1) |
   145			     SUN6I_DPHY_ANA4_REG_TXDNSD(1) |
   146			     SUN6I_DPHY_ANA4_REG_TXPUSC(1) |
   147			     SUN6I_DPHY_ANA4_REG_TXPUSD(1) |
   148			     SUN6I_DPHY_ANA4_REG_DMPLVC |
   149			     SUN6I_DPHY_ANA4_REG_DMPLVD(lanes_mask));
   150	
   151		regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
   152			     SUN6I_DPHY_ANA2_REG_ENIB);
   153		udelay(5);
   154	
   155		regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
   156			     SUN6I_DPHY_ANA3_EN_LDOR |
   157			     SUN6I_DPHY_ANA3_EN_LDOC |
   158			     SUN6I_DPHY_ANA3_EN_LDOD);
   159		udelay(1);
   160	
   161		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
   162				   SUN6I_DPHY_ANA3_EN_VTTC |
   163				   SUN6I_DPHY_ANA3_EN_VTTD_MASK,
   164				   SUN6I_DPHY_ANA3_EN_VTTC |
   165				   SUN6I_DPHY_ANA3_EN_VTTD(lanes_mask));
   166		udelay(1);
   167	
   168		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
   169				   SUN6I_DPHY_ANA3_EN_DIV,
   170				   SUN6I_DPHY_ANA3_EN_DIV);
   171		udelay(1);
   172	
   173		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
   174				   SUN6I_DPHY_ANA2_EN_CK_CPU,
   175				   SUN6I_DPHY_ANA2_EN_CK_CPU);
   176		udelay(1);
   177	
   178		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
   179				   SUN6I_DPHY_ANA1_REG_VTTMODE,
   180				   SUN6I_DPHY_ANA1_REG_VTTMODE);
   181	
   182		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
   183				   SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
   184				   SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
   185	
   186		return 0;
   187	}
   188	
   189	int sun6i_dphy_power_off(struct sun6i_dphy *dphy)
   190	{
   191		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
   192				   SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
   193	
   194		return 0;
   195	}
   196	
   197	int sun6i_dphy_exit(struct sun6i_dphy *dphy)
   198	{
 > 199		clk_rate_unprotect(dphy->mod_clk);
   200		clk_disable_unprepare(dphy->mod_clk);
   201		reset_control_assert(dphy->reset);
   202	
   203		return 0;
   204	}
   205	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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Re: [PATCH 02/18] drm/sun4i: Add if statement instead of depends on

[Maxime Ripard]

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On Fri, Jul 14, 2017 at 11:09:07AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The depends on relationship is obvious, and using an if statement will
> > propagate it to every option without the need for each and every one of
> > them to define it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 04/18] drm/sun4i: Remove useless atomic_check

[Maxime Ripard]

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On Fri, Jul 14, 2017 at 11:15:18AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The atomic_check callback is optional, and we don't implement anything in
> > some parts of our drivers. Let's remove it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 01/18] regmap: mmio: Add function to attach a clock

[Maxime Ripard]

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Hi Mark,

On Thu, Jul 13, 2017 at 05:01:42PM +0100, Mark Brown wrote:
> On Thu, Jul 13, 2017 at 04:12:56PM +0200, Maxime Ripard wrote:
> 
> > This might be problematic if the clock to enable is stored in another node.
> > Let's add a function that allows to attach a clock that has already been
> > retrieved to a regmap in order to fix this.
> 
> What is the use case for this?

This is useful when the clock you want to be handled by the regmap is
not described in the device node that probed the driver, but one of
its subnode, or an another node entirely.

We're in the latter case, where we have two controllers in the DT, but
are driven by the same driver. We'll create two regmaps, but one will
not have the proper of_node used to retrieve the clock.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 17/18] arm: dts: sun8i: Add BananaPI M2-Magic DTS

[Maxime Ripard]

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On Fri, Jul 14, 2017 at 12:40:19PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
> > connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
> > DSI, CSI and GPIOs.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

> Has BPI publicly released the schematics and/or FEX file yet?

I don't think they did yet.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 11/18] dt-bindings: display: Add Allwinner MIPI-DSI bindings

[Rob Herring]

On Thu, Jul 13, 2017 at 04:13:06PM +0200, Maxime Ripard wrote:
> The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85 +++++++-
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> new file mode 100644
> index 000000000000..2e7c5aa7020f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> @@ -0,0 +1,85 @@
> +Allwinner A31 DSI Encoder
> +=========================
> +
> +The DSI pipeline consists of two separate blocks: the DSI controller
> +itself, and its associated D-PHY.
> +
> +DSI Encoder
> +-----------
> +
> +The DSI Encoder generates the DSI signal from the TCON's.
> +
> +Required properties:
> +  - compatible: value must be one of:
> +    * allwinner,sun6i-a31-mipi-dsi
> +  - reg: base address and size of memory-mapped region
> +  - interrupts: interrupt associated to this IP
> +  - clocks: phandles to the clocks feeding the DSI encoder
> +    * bus: the DSI interface clock
> +    * mod: the DSI module clock
> +  - clock-names: the clock names mentioned above
> +  - phys: phandle to the D-PHY
> +  - phy-names: must be "dphy"
> +  - resets: phandle to the reset controller driving the encoder
> +
> +  - ports: A ports node with endpoint definitions as defined in
> +    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> +    port should be the input endpoint, usually coming from the
> +    associated TCON.

Output port for bridge/panel?

> +
> +D-PHY
> +-----
> +
> +Required properties:
> +  - compatible: value must be one of:
> +    * allwinner,sun6i-a31-mipi-dphy
> +  - reg: base address and size of memory-mapped region
> +  - clocks: phandles to the clocks feeding the DSI encoder
> +    * bus: the DSI interface clock
> +    * mod: the DSI module clock
> +  - clock-names: the clock names mentioned above
> +  - resets: phandle to the reset controller driving the encoder
> +
> +Example:
> +
> +dsi0: dsi@01ca0000 {

Drop the leading 0.

> +	compatible = "allwinner,sun6i-a31-mipi-dsi";
> +	reg = <0x01ca0000 0x1000>;
> +	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> +		 <&ccu CLK_DSI_SCLK>;
> +	clock-names = "bus", "mod";
> +	resets = <&ccu RST_BUS_MIPI_DSI>;
> +	phys = <&dphy0>;
> +	phy-names = "dphy";

> +	#address-cells = <1>;
> +	#size-cells = <0>;

Not needed.

> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		dsi0_in: port@0 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0>;
> +
> +			dsi0_in_tcon0: endpoint@0 {
> +				reg = <0>;

Don't need reg when there's only 1 endpoint.

> +				remote-endpoint = <&tcon0_out_dsi0>;
> +			};
> +		};
> +	};
> +};
> +
> +dphy0: d-phy@01ca1000 {

Drop leading 0.

> +	compatible = "allwinner,sun6i-a31-mipi-dphy";
> +	reg = <0x01ca1000 0x1000>;
> +	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> +		 <&ccu CLK_DSI_DPHY>;
> +	clock-names = "bus", "mod";
> +	resets = <&ccu RST_BUS_MIPI_DSI>;

> +	#address-cells = <1>;
> +	#size-cells = <0>;

For what?

> +	#phy-cells = <0>;
> +};
> -- 
> git-series 0.9.1

Re: [PATCH 14/18] dt-bindings: panel: Add Huarui LHR050H41 panel documentation

[Rob Herring]

On Thu, Jul 13, 2017 at 04:13:09PM +0200, Maxime Ripard wrote:
> The LHR050H41 is a 1280x700 4-lanes DSI panel.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt

Other than the question about the vendor name,

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 10/18] drm/sun4i: tcon: Move out the tcon0 common setup

[Chen-Yu Tsai]

On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some channel0 setup has to be done, no matter what the output interface is
> (RGB, CPU, LVDS). Move that code into a common function in order to avoid
> duplication.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 ++++++++++++++++----------
>  1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index a3bbf9994cfa..f051862d635e 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -125,15 +125,26 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
>         return delay;
>  }
>
> -static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> -                                struct drm_display_mode *mode)
> +static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
> +                                       struct drm_display_mode *mode)
> +{
> +       /* Configure the dot clock */
> +       clk_set_rate_protect(tcon->dclk, mode->crtc_clock * 1000);

I'd prefer not changing APIs in a code move. It also means we could
apply this sooner than later. Otherwise,

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

> +
> +       /* Set the resolution */
> +       regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
> +                    SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
> +                    SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
> +}
> +
> +static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
> +                                    struct drm_display_mode *mode)
>  {
>         unsigned int bp, hsync, vsync;
>         u8 clk_delay;
>         u32 val = 0;
>
> -       /* Configure the dot clock */
> -       clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
> +       sun4i_tcon0_mode_set_common(tcon, mode);
>
>         /* Adjust clock delay */
>         clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
> @@ -141,11 +152,6 @@ static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
>                            SUN4I_TCON0_CTL_CLK_DELAY_MASK,
>                            SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
>
> -       /* Set the resolution */
> -       regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
> -                    SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
> -                    SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
> -
>         /*
>          * This is called a backporch in the register documentation,
>          * but it really is the back porch + hsync
> @@ -295,7 +301,7 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
>  {
>         switch (encoder->encoder_type) {
>         case DRM_MODE_ENCODER_NONE:
> -               sun4i_tcon0_mode_set(tcon, mode);
> +               sun4i_tcon0_mode_set_rgb(tcon, mode);
>                 break;
>         case DRM_MODE_ENCODER_TVDAC:
>                 /*
> --
> git-series 0.9.1

Re: [PATCH 11/18] dt-bindings: display: Add Allwinner MIPI-DSI bindings

[Laurent Pinchart]

On Monday 17 Jul 2017 13:41:49 Rob Herring wrote:
> On Thu, Jul 13, 2017 at 04:13:06PM +0200, Maxime Ripard wrote:
> > The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > 
> >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85
> >  +++++++-
> >  1 file changed, 85 insertions(+)
> >  create mode 100644
> >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt> 
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt new file
> > mode 100644
> > index 000000000000..2e7c5aa7020f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > @@ -0,0 +1,85 @@
> > +Allwinner A31 DSI Encoder
> > +=========================
> > +
> > +The DSI pipeline consists of two separate blocks: the DSI controller
> > +itself, and its associated D-PHY.
> > +
> > +DSI Encoder
> > +-----------
> > +
> > +The DSI Encoder generates the DSI signal from the TCON's.
> > +
> > +Required properties:
> > +  - compatible: value must be one of:
> > +    * allwinner,sun6i-a31-mipi-dsi
> > +  - reg: base address and size of memory-mapped region
> > +  - interrupts: interrupt associated to this IP
> > +  - clocks: phandles to the clocks feeding the DSI encoder
> > +    * bus: the DSI interface clock
> > +    * mod: the DSI module clock
> > +  - clock-names: the clock names mentioned above
> > +  - phys: phandle to the D-PHY
> > +  - phy-names: must be "dphy"
> > +  - resets: phandle to the reset controller driving the encoder
> > +
> > +  - ports: A ports node with endpoint definitions as defined in
> > +    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> > +    port should be the input endpoint, usually coming from the
> > +    associated TCON.
> 
> Output port for bridge/panel?
> 
> > +
> > +D-PHY
> > +-----
> > +
> > +Required properties:
> > +  - compatible: value must be one of:
> > +    * allwinner,sun6i-a31-mipi-dphy
> > +  - reg: base address and size of memory-mapped region
> > +  - clocks: phandles to the clocks feeding the DSI encoder
> > +    * bus: the DSI interface clock
> > +    * mod: the DSI module clock
> > +  - clock-names: the clock names mentioned above
> > +  - resets: phandle to the reset controller driving the encoder
> > +
> > +Example:
> > +
> > +dsi0: dsi@01ca0000 {
> 
> Drop the leading 0.
> 
> > +	compatible = "allwinner,sun6i-a31-mipi-dsi";
> > +	reg = <0x01ca0000 0x1000>;
> > +	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > +	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > +		 <&ccu CLK_DSI_SCLK>;
> > +	clock-names = "bus", "mod";
> > +	resets = <&ccu RST_BUS_MIPI_DSI>;
> > +	phys = <&dphy0>;
> > +	phy-names = "dphy";
> > 
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> 
> Not needed.
> 
> > +
> > +	ports {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		dsi0_in: port@0 {

I don't think the label for the port is needed, you should only reference the 
endpoint.

> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0>;
> > +
> > +			dsi0_in_tcon0: endpoint@0 {
> > +				reg = <0>;
> 
> Don't need reg when there's only 1 endpoint.

And no reg for the port name either when there's a single port. This can all 
be simplified to

dsi0: dsi@1ca0000 {
	compatible = "allwinner,sun6i-a31-mipi-dsi";
	reg = <0x01ca0000 0x1000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>,
		 <&ccu CLK_DSI_SCLK>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_MIPI_DSI>;
	phys = <&dphy0>;
	phy-names = "dphy";

	port {
		dsi0_in_tcon0: endpoint {
			remote-endpoint = <&tcon0_out_dsi0>;
		};
	};
};

> > +				remote-endpoint = <&tcon0_out_dsi0>;
> > +			};
> > +		};
> > +	};
> > +};

[snip]

-- 
Regards,

Laurent Pinchart

Re: [PATCH 01/18] regmap: mmio: Add function to attach a clock

[Mark Brown]

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On Mon, Jul 17, 2017 at 11:01:07AM +0200, Maxime Ripard wrote:
> On Thu, Jul 13, 2017 at 05:01:42PM +0100, Mark Brown wrote:

> > > This might be problematic if the clock to enable is stored in another node.
> > > Let's add a function that allows to attach a clock that has already been
> > > retrieved to a regmap in order to fix this.

> > What is the use case for this?

> This is useful when the clock you want to be handled by the regmap is
> not described in the device node that probed the driver, but one of
> its subnode, or an another node entirely.

> We're in the latter case, where we have two controllers in the DT, but
> are driven by the same driver. We'll create two regmaps, but one will
> not have the proper of_node used to retrieve the clock.

I'm sorry but I'm still not seeing why you're doing this.  Can you be
more concrete please?

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Re: [PATCH 03/18] drm/sun4i: Realign Makefile padding and reorder it

[Maxime Ripard]

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On Fri, Jul 14, 2017 at 11:13:53AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Some options were not padded as they should, and the order in the Makefile
> > was chaotic. Fix that.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/gpu/drm/sun4i/Makefile | 26 +++++++++++++-------------
> >  1 file changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
> > index e29fd3a2ba9c..42871ee7acf6 100644
> > --- a/drivers/gpu/drm/sun4i/Makefile
> > +++ b/drivers/gpu/drm/sun4i/Makefile
> > @@ -1,23 +1,23 @@
> > -sun4i-drm-y += sun4i_drv.o
> > -sun4i-drm-y += sun4i_framebuffer.o
> > +sun4i-backend-y                        += sun4i_backend.o sun4i_layer.o
> >
> > -sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
> > -sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
> > -sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
> > +sun4i-drm-y                    += sun4i_drv.o
> > +sun4i-drm-y                    += sun4i_framebuffer.o
> 
> I don't think this applies on top of Jonathan's HDMI I2C patch
> you already have queued up.
> 
> Also you might want to leave a comment describe what the
> ordering should be. Otherwise it will still be messed up
> down the road.

Good point, I'll do that, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 06/18] drm/sun4i: tcon: Don't rely on encoders to enable the TCON

[Maxime Ripard]

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Hi Chen-Yu,

On Fri, Jul 14, 2017 at 11:40:07AM +0800, Chen-Yu Tsai wrote:
> >  static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder,
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > index d9791292553e..dc70bc2a42a5 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > @@ -14,6 +14,7 @@
> >  #include <drm/drm_atomic_helper.h>
> >  #include <drm/drm_crtc.h>
> >  #include <drm/drm_crtc_helper.h>
> > +#include <drm/drm_encoder.h>
> >  #include <drm/drm_modes.h>
> >  #include <drm/drm_of.h>
> >
> > @@ -32,66 +33,62 @@
> >  #include "sun4i_tcon.h"
> >  #include "sunxi_engine.h"
> >
> > -void sun4i_tcon_disable(struct sun4i_tcon *tcon)
> > +static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
> > +                                         bool enabled)
> >  {
> > -       DRM_DEBUG_DRIVER("Disabling TCON\n");
> > +       struct clk *clk;
> >
> > -       /* Disable the TCON */
> > -       regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
> > -                          SUN4I_TCON_GCTL_TCON_ENABLE, 0);
> > -}
> > -EXPORT_SYMBOL(sun4i_tcon_disable);
> > -
> > -void sun4i_tcon_enable(struct sun4i_tcon *tcon)
> > -{
> > -       DRM_DEBUG_DRIVER("Enabling TCON\n");
> > -
> > -       /* Enable the TCON */
> > -       regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
> > -                          SUN4I_TCON_GCTL_TCON_ENABLE,
> > -                          SUN4I_TCON_GCTL_TCON_ENABLE);
> > -}
> > -EXPORT_SYMBOL(sun4i_tcon_enable);
> > -
> > -void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
> > -{
> > -       DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
> > -
> > -       /* Disable the TCON's channel */
> > -       if (channel == 0) {
> > +       switch (channel) {
> > +       case 0:
> >                 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
> > -                                  SUN4I_TCON0_CTL_TCON_ENABLE, 0);
> > -               clk_disable_unprepare(tcon->dclk);
> > +                                  SUN4I_TCON0_CTL_TCON_ENABLE,
> > +                                  enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
> > +               clk = tcon->dclk;
> > +               break;
> > +       case 1:
> > +               WARN_ON(!tcon->quirks->has_channel_1);
> > +               regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
> > +                                  SUN4I_TCON1_CTL_TCON_ENABLE,
> > +                                  enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
> > +               clk = tcon->sclk1;
> > +               break;
> > +       default:
> > +               DRM_DEBUG_DRIVER("Unknown channel... doing nothing\n");
> >                 return;
> >         }
> >
> > -       WARN_ON(!tcon->quirks->has_channel_1);
> > -       regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
> > -                          SUN4I_TCON1_CTL_TCON_ENABLE, 0);
> > -       clk_disable_unprepare(tcon->sclk1);
> > +       if (enabled)
> > +               clk_prepare_enable(clk);
> 
> I wonder if it's better to enable the clk before the TCON?

I think I kept the current behaviour, which seemed to work fine with
that regard.

> 
> > +       else
> > +               clk_disable_unprepare(clk);
> >  }
> > -EXPORT_SYMBOL(sun4i_tcon_channel_disable);
> >
> > -void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
> > +void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
> > +                          struct drm_encoder *encoder,
> > +                          bool enabled)
> >  {
> > -       DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
> > -
> > -       /* Enable the TCON's channel */
> > -       if (channel == 0) {
> > -               regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
> > -                                  SUN4I_TCON0_CTL_TCON_ENABLE,
> > -                                  SUN4I_TCON0_CTL_TCON_ENABLE);
> > -               clk_prepare_enable(tcon->dclk);
> > +       int channel;
> > +
> > +       switch (encoder->encoder_type) {
> > +       case DRM_MODE_ENCODER_NONE:
> > +               channel = 0;
> > +               break;
> > +       case DRM_MODE_ENCODER_TMDS:
> > +       case DRM_MODE_ENCODER_TVDAC:
> > +               channel = 1;
> > +               break;
> > +       default:
> > +               DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
> 
> We could simply add all the possible types, and print a big warning
> if someone does something unexpected. IMHO this is better than having
> the user enable some hidden debug flag to figure why the display isn't
> working properly.

I'm not sure about all types of encoders, but you're right, it should
be a warning.

> >                 return;
> >         }
> >
> > -       WARN_ON(!tcon->quirks->has_channel_1);
> > -       regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
> > -                          SUN4I_TCON1_CTL_TCON_ENABLE,
> > -                          SUN4I_TCON1_CTL_TCON_ENABLE);
> > -       clk_prepare_enable(tcon->sclk1);
> > +       sun4i_tcon_channel_set_status(tcon, channel, enabled);
> > +
> > +       regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
> > +                          SUN4I_TCON_GCTL_TCON_ENABLE,
> > +                          enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
> 
> The global enable bit should be set first.

ACK


> Also the manual says "When it’s disabled, the module will be reset to
> idle state."
> so you might get away with just disabling the global enable bit and returning
> directly after disabling the clock?

I'd rather keep an explicit disable, just in case one SoC is broken,
just like the DE is...

> >  }
> > -EXPORT_SYMBOL(sun4i_tcon_channel_enable);
> > +EXPORT_SYMBOL(sun4i_tcon_set_status);
> 
> The TCON and CRTC code are part of the same module.
> There is no need to export this function.

Ah, right. I'll remove it. Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 07/18] drm/sun4i: tcon: Don't rely on encoders to set the TCON mode

[Maxime Ripard]

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On Fri, Jul 14, 2017 at 11:56:18AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Just like we did for the TCON enable and disable, for historical reasons we
> > used to rely on the encoders calling the TCON mode_set function, while the
> > CRTC has a callback for that.
> >
> > Let's implement it in order to reduce the boilerplate code.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/gpu/drm/sun4i/sun4i_crtc.c          | 11 ++++-
> >  drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c  |  1 +-
> >  drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c      |  7 +---
> >  drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c |  1 +-
> >  drivers/gpu/drm/sun4i/sun4i_rgb.c           | 15 +------
> >  drivers/gpu/drm/sun4i/sun4i_tcon.c          | 56 ++++++++++------------
> >  drivers/gpu/drm/sun4i/sun4i_tcon.h          | 10 +----
> >  drivers/gpu/drm/sun4i/sun4i_tv.c            |  6 +--
> >  8 files changed, 40 insertions(+), 67 deletions(-)
> >
> 
> [...]
> 
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > index dc70bc2a42a5..c4407910dfaf 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > @@ -106,29 +106,6 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
> >  }
> >  EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
> >
> > -void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
> > -                       struct drm_encoder *encoder)
> > -{
> > -       u32 val;
> > -
> > -       if (!tcon->quirks->has_unknown_mux)
> > -               return;
> > -
> > -       if (channel != 1)
> > -               return;
> > -
> > -       if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
> > -               val = 1;
> > -       else
> > -               val = 0;
> > -
> > -       /*
> > -        * FIXME: Undocumented bits
> > -        */
> > -       regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
> > -}
> > -EXPORT_SYMBOL(sun4i_tcon_set_mux);
> > -
> >  static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
> >                                     int channel)
> >  {
> > @@ -147,8 +124,8 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
> >         return delay;
> >  }
> >
> > -void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> > -                         struct drm_display_mode *mode)
> > +static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> > +                                struct drm_display_mode *mode)
> 
> Nit on the side: maybe we could mark mode as constant?
> Since the function doesn't change it. Same applies to the
> other mode_set functions. But this could be left to another
> patch.

We totally should. I'll do it.

> >  {
> >         unsigned int bp, hsync, vsync;
> >         u8 clk_delay;
> > @@ -221,10 +198,9 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> >         /* Enable the output on the pins */
> >         regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
> >  }
> > -EXPORT_SYMBOL(sun4i_tcon0_mode_set);
> >
> > -void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
> > -                         struct drm_display_mode *mode)
> > +static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
> > +                                struct drm_display_mode *mode)
> >  {
> >         unsigned int bp, hsync, vsync, vtotal;
> >         u8 clk_delay;
> > @@ -312,7 +288,29 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
> >                            SUN4I_TCON_GCTL_IOMAP_MASK,
> >                            SUN4I_TCON_GCTL_IOMAP_TCON1);
> >  }
> > -EXPORT_SYMBOL(sun4i_tcon1_mode_set);
> > +
> > +void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
> > +                        struct drm_display_mode *mode)
> 
> (also mark encoder as const?)

Yep.

> > +{
> > +       switch (encoder->encoder_type) {
> > +       case DRM_MODE_ENCODER_NONE:
> > +               sun4i_tcon0_mode_set(tcon, mode);
> > +               break;
> > +       case DRM_MODE_ENCODER_TVDAC:
> > +               /*
> > +                * FIXME: Undocumented bits
> > +                */
> > +               if (tcon->quirks->has_unknown_mux)
> > +                       regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
> > +               /* Fallthrough */
> > +       case DRM_MODE_ENCODER_TMDS:
> > +               sun4i_tcon1_mode_set(tcon, mode);
> 
> IIRC you need to clear the mux bit here. So ...
> 
> > +               break;
> > +       default:
> > +               DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
> > +       }
> 
> I think keeping the muxing in a separate function would be cleaner.
> The above is already slightly messy if you add the bit clearing part.
> With all the other muxing possibilities in the other SoC this is
> going to get really messy.

Ok.

> > +}
> > +EXPORT_SYMBOL(sun4i_tcon_mode_set);
> >
> >  static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
> >                                         struct sun4i_crtc *scrtc)
> 
> [...]
> 
> Thanks for working on this. Now we've decoupled the TCON/CRTC code
> from all the encoders.

Yeah, I still have mixed feelings about this, but it was the sensible
thing I guess.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 13/18] dt-bindings: vendor: Add Huarui Lighting

[Maxime Ripard]

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Hi Chen-Yu,

On Fri, Jul 14, 2017 at 03:53:40PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Huarui Lighting makes display panel, add it to the list of panels.
> 
> I could not find any information on "Huarui Lighting" within the
> context of LCD panels. The company I found makes LED lighting
> fixtures, floodlights, and high power LED drivers.
> 
> This might not be a legitimate branding?

The references are sparse, but the only time I could find a vendor for
that part was here, page 51:
https://www.codico.com/shop/media/datasheets/Quectel_SC20_Hardware_Design_V1.2.pdf

But maybe it's wrong. And since it has a BPi logo on it, maybe we
should just use sinovoip as the vendor.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 10/18] drm/sun4i: tcon: Move out the tcon0 common setup

[Maxime Ripard]

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On Tue, Jul 18, 2017 at 11:41:36AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Some channel0 setup has to be done, no matter what the output interface is
> > (RGB, CPU, LVDS). Move that code into a common function in order to avoid
> > duplication.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 ++++++++++++++++----------
> >  1 file changed, 16 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > index a3bbf9994cfa..f051862d635e 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > @@ -125,15 +125,26 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
> >         return delay;
> >  }
> >
> > -static void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> > -                                struct drm_display_mode *mode)
> > +static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
> > +                                       struct drm_display_mode *mode)
> > +{
> > +       /* Configure the dot clock */
> > +       clk_set_rate_protect(tcon->dclk, mode->crtc_clock * 1000);
> 
> I'd prefer not changing APIs in a code move. It also means we could
> apply this sooner than later. Otherwise,

You're right, I've changed it.

> Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 11/18] dt-bindings: display: Add Allwinner MIPI-DSI bindings

[Maxime Ripard]

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Hi Rob,

On Mon, Jul 17, 2017 at 01:41:49PM -0500, Rob Herring wrote:
> On Thu, Jul 13, 2017 at 04:13:06PM +0200, Maxime Ripard wrote:
> > The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85 +++++++-
> >  1 file changed, 85 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > new file mode 100644
> > index 000000000000..2e7c5aa7020f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > @@ -0,0 +1,85 @@
> > +Allwinner A31 DSI Encoder
> > +=========================
> > +
> > +The DSI pipeline consists of two separate blocks: the DSI controller
> > +itself, and its associated D-PHY.
> > +
> > +DSI Encoder
> > +-----------
> > +
> > +The DSI Encoder generates the DSI signal from the TCON's.
> > +
> > +Required properties:
> > +  - compatible: value must be one of:
> > +    * allwinner,sun6i-a31-mipi-dsi
> > +  - reg: base address and size of memory-mapped region
> > +  - interrupts: interrupt associated to this IP
> > +  - clocks: phandles to the clocks feeding the DSI encoder
> > +    * bus: the DSI interface clock
> > +    * mod: the DSI module clock
> > +  - clock-names: the clock names mentioned above
> > +  - phys: phandle to the D-PHY
> > +  - phy-names: must be "dphy"
> > +  - resets: phandle to the reset controller driving the encoder
> > +
> > +  - ports: A ports node with endpoint definitions as defined in
> > +    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> > +    port should be the input endpoint, usually coming from the
> > +    associated TCON.
> 
> Output port for bridge/panel?

The DSI panels and bridges are subnodes of the DSI controller. But I
should mention that :)

> 
> > +
> > +D-PHY
> > +-----
> > +
> > +Required properties:
> > +  - compatible: value must be one of:
> > +    * allwinner,sun6i-a31-mipi-dphy
> > +  - reg: base address and size of memory-mapped region
> > +  - clocks: phandles to the clocks feeding the DSI encoder
> > +    * bus: the DSI interface clock
> > +    * mod: the DSI module clock
> > +  - clock-names: the clock names mentioned above
> > +  - resets: phandle to the reset controller driving the encoder
> > +
> > +Example:
> > +
> > +dsi0: dsi@01ca0000 {
> 
> Drop the leading 0.
> 
> > +	compatible = "allwinner,sun6i-a31-mipi-dsi";
> > +	reg = <0x01ca0000 0x1000>;
> > +	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > +	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > +		 <&ccu CLK_DSI_SCLK>;
> > +	clock-names = "bus", "mod";
> > +	resets = <&ccu RST_BUS_MIPI_DSI>;
> > +	phys = <&dphy0>;
> > +	phy-names = "dphy";
> 
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> 
> Not needed.
> 
> > +
> > +	ports {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		dsi0_in: port@0 {
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0>;
> > +
> > +			dsi0_in_tcon0: endpoint@0 {
> > +				reg = <0>;
> 
> Don't need reg when there's only 1 endpoint.
> 
> > +				remote-endpoint = <&tcon0_out_dsi0>;
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > +dphy0: d-phy@01ca1000 {
> 
> Drop leading 0.
> 
> > +	compatible = "allwinner,sun6i-a31-mipi-dphy";
> > +	reg = <0x01ca1000 0x1000>;
> > +	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > +		 <&ccu CLK_DSI_DPHY>;
> > +	clock-names = "bus", "mod";
> > +	resets = <&ccu RST_BUS_MIPI_DSI>;
> 
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> 
> For what?

I'll address those comments, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 11/18] dt-bindings: display: Add Allwinner MIPI-DSI bindings

[Maxime Ripard]

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Hi Laurent

On Tue, Jul 18, 2017 at 01:18:42PM +0300, Laurent Pinchart wrote:
> On Monday 17 Jul 2017 13:41:49 Rob Herring wrote:
> > On Thu, Jul 13, 2017 at 04:13:06PM +0200, Maxime Ripard wrote:
> > > The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.
> > > 
> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > > ---
> > > 
> > >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85
> > >  +++++++-
> > >  1 file changed, 85 insertions(+)
> > >  create mode 100644
> > >  Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt> 
> > > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > > b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt new file
> > > mode 100644
> > > index 000000000000..2e7c5aa7020f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt
> > > @@ -0,0 +1,85 @@
> > > +Allwinner A31 DSI Encoder
> > > +=========================
> > > +
> > > +The DSI pipeline consists of two separate blocks: the DSI controller
> > > +itself, and its associated D-PHY.
> > > +
> > > +DSI Encoder
> > > +-----------
> > > +
> > > +The DSI Encoder generates the DSI signal from the TCON's.
> > > +
> > > +Required properties:
> > > +  - compatible: value must be one of:
> > > +    * allwinner,sun6i-a31-mipi-dsi
> > > +  - reg: base address and size of memory-mapped region
> > > +  - interrupts: interrupt associated to this IP
> > > +  - clocks: phandles to the clocks feeding the DSI encoder
> > > +    * bus: the DSI interface clock
> > > +    * mod: the DSI module clock
> > > +  - clock-names: the clock names mentioned above
> > > +  - phys: phandle to the D-PHY
> > > +  - phy-names: must be "dphy"
> > > +  - resets: phandle to the reset controller driving the encoder
> > > +
> > > +  - ports: A ports node with endpoint definitions as defined in
> > > +    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> > > +    port should be the input endpoint, usually coming from the
> > > +    associated TCON.
> > 
> > Output port for bridge/panel?
> > 
> > > +
> > > +D-PHY
> > > +-----
> > > +
> > > +Required properties:
> > > +  - compatible: value must be one of:
> > > +    * allwinner,sun6i-a31-mipi-dphy
> > > +  - reg: base address and size of memory-mapped region
> > > +  - clocks: phandles to the clocks feeding the DSI encoder
> > > +    * bus: the DSI interface clock
> > > +    * mod: the DSI module clock
> > > +  - clock-names: the clock names mentioned above
> > > +  - resets: phandle to the reset controller driving the encoder
> > > +
> > > +Example:
> > > +
> > > +dsi0: dsi@01ca0000 {
> > 
> > Drop the leading 0.
> > 
> > > +	compatible = "allwinner,sun6i-a31-mipi-dsi";
> > > +	reg = <0x01ca0000 0x1000>;
> > > +	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > > +	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> > > +		 <&ccu CLK_DSI_SCLK>;
> > > +	clock-names = "bus", "mod";
> > > +	resets = <&ccu RST_BUS_MIPI_DSI>;
> > > +	phys = <&dphy0>;
> > > +	phy-names = "dphy";
> > > 
> > > +	#address-cells = <1>;
> > > +	#size-cells = <0>;
> > 
> > Not needed.
> > 
> > > +
> > > +	ports {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +
> > > +		dsi0_in: port@0 {
> 
> I don't think the label for the port is needed, you should only reference the 
> endpoint.
> 
> > > +			#address-cells = <1>;
> > > +			#size-cells = <0>;
> > > +			reg = <0>;
> > > +
> > > +			dsi0_in_tcon0: endpoint@0 {
> > > +				reg = <0>;
> > 
> > Don't need reg when there's only 1 endpoint.
> 
> And no reg for the port name either when there's a single port. This can all 
> be simplified to
> 
> dsi0: dsi@1ca0000 {
> 	compatible = "allwinner,sun6i-a31-mipi-dsi";
> 	reg = <0x01ca0000 0x1000>;
> 	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> 	clocks = <&ccu CLK_BUS_MIPI_DSI>,
> 		 <&ccu CLK_DSI_SCLK>;
> 	clock-names = "bus", "mod";
> 	resets = <&ccu RST_BUS_MIPI_DSI>;
> 	phys = <&dphy0>;
> 	phy-names = "dphy";
> 
> 	port {
> 		dsi0_in_tcon0: endpoint {
> 			remote-endpoint = <&tcon0_out_dsi0>;
> 		};
> 	};
> };

I'll change that. Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 01/18] regmap: mmio: Add function to attach a clock

[Maxime Ripard]

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On Tue, Jul 18, 2017 at 02:21:47PM +0100, Mark Brown wrote:
> On Mon, Jul 17, 2017 at 11:01:07AM +0200, Maxime Ripard wrote:
> > On Thu, Jul 13, 2017 at 05:01:42PM +0100, Mark Brown wrote:
> 
> > > > This might be problematic if the clock to enable is stored in another node.
> > > > Let's add a function that allows to attach a clock that has already been
> > > > retrieved to a regmap in order to fix this.
> 
> > > What is the use case for this?
> 
> > This is useful when the clock you want to be handled by the regmap is
> > not described in the device node that probed the driver, but one of
> > its subnode, or an another node entirely.
> 
> > We're in the latter case, where we have two controllers in the DT, but
> > are driven by the same driver. We'll create two regmaps, but one will
> > not have the proper of_node used to retrieve the clock.
> 
> I'm sorry but I'm still not seeing why you're doing this.  Can you be
> more concrete please?

We have two devices needed to bring DSI: the DSI controller itself and
its associated PHY.

The PHY configuration cannot be done through a framework because it
requires more information than the various phy frameworks allow to
pass through to the driver.

Therefore, we have a single driver, attached to the DSI controller,
which handles both the PHY and the DSI controller.

Both the PHY and the DSI controller are separate device, with
different memory regions. Therefore, we need to create two regmaps,
with clocks attached to them.

However, the default clock retrieval mechanism doesn't work for the
phy regmap, since only the DSI controller device of_node is
considered, while its clock is stored in a separate node.

I hope it's clearer,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 09/18] drm/sun4i: tcon: Adjust dotclock dividers range

[Maxime Ripard]

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On Fri, Jul 14, 2017 at 12:14:37PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > It seems like the dotclock dividers are a bit less strict range, and can
> > operate even with a smaller than 6 divider. Loose the boundaries a bit.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++++++++++++++++++-
> >  1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> > index d401156490f3..0b844c0dd102 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
> > @@ -77,7 +77,25 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
> >         u8 best_div = 1;
> >         int i;
> >
> > -       for (i = 6; i <= 127; i++) {
> > +       /*
> > +        * There's something odd here.
> > +        *
> > +        * In the A13 user manual, this is stated to be >= 6 when
> > +        * dclk1 and dclk2 are used (without any hint on how to use
> > +        * them), and >= 4 when only dclk is used.
> 
> You set it in TCON0_IO_POL_REG, which sets the clock phase delay.

oh, so it's d for delay? I assumed it was for dotclock.

> I think we were setting this before, but you removed it as part of
> the previous TCON clean up patches?

Hmmm, I might have.. :)

> In the A33, there are even more options, like DCLK / 2 (with 0 or 90
> degree phase delay).

Where did you find this documentation? I was under the impression that
all that DCLK stuff was in the higher bits of the DCLK register, but
apparently there's more to it.

> > +        *
> > +        * In the A33 user manual, when only dclk is used, it is set
> > +        * to be >= 6 in the former case, and >= 1 in the
> > +        * latter. There's also some (obscure) explanations about the
> > +        * dclk1 and dclk2 vs dclk that seems to be in the upper 4
> > +        * bits. What those clocks are and what bit does what is not
> > +        * really clear.
> 
> Looks like mux bits to me. How they differ from TCON0_IO_POL_REG is
> beyond me ATM.

It might be some additional dividers too.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 09/18] drm/sun4i: tcon: Adjust dotclock dividers range

[Chen-Yu Tsai]

On Thu, Jul 20, 2017 at 10:55 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Fri, Jul 14, 2017 at 12:14:37PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > It seems like the dotclock dividers are a bit less strict range, and can
>> > operate even with a smaller than 6 divider. Loose the boundaries a bit.
>> >
>> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> > ---
>> >  drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++++++++++++++++++-
>> >  1 file changed, 19 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
>> > index d401156490f3..0b844c0dd102 100644
>> > --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
>> > +++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
>> > @@ -77,7 +77,25 @@ static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
>> >         u8 best_div = 1;
>> >         int i;
>> >
>> > -       for (i = 6; i <= 127; i++) {
>> > +       /*
>> > +        * There's something odd here.
>> > +        *
>> > +        * In the A13 user manual, this is stated to be >= 6 when
>> > +        * dclk1 and dclk2 are used (without any hint on how to use
>> > +        * them), and >= 4 when only dclk is used.
>>
>> You set it in TCON0_IO_POL_REG, which sets the clock phase delay.
>
> oh, so it's d for delay? I assumed it was for dotclock.

The manual says "data clock" for register 0x44 (TCON0_DCLK_REG)

>
>> I think we were setting this before, but you removed it as part of
>> the previous TCON clean up patches?
>
> Hmmm, I might have.. :)
>
>> In the A33, there are even more options, like DCLK / 2 (with 0 or 90
>> degree phase delay).
>
> Where did you find this documentation? I was under the impression that
> all that DCLK stuff was in the higher bits of the DCLK register, but
> apparently there's more to it.

Same section, TCON0_IO_POL_REG register bits.

The bits in TCON0_IO_POL_REG are likely a mux, letting you select which
one that is actually used on the external (with regard to the TCON) pin.

>
>> > +        *
>> > +        * In the A33 user manual, when only dclk is used, it is set
>> > +        * to be >= 6 in the former case, and >= 1 in the
>> > +        * latter. There's also some (obscure) explanations about the
>> > +        * dclk1 and dclk2 vs dclk that seems to be in the upper 4
>> > +        * bits. What those clocks are and what bit does what is not
>> > +        * really clear.
>>
>> Looks like mux bits to me. How they differ from TCON0_IO_POL_REG is
>> beyond me ATM.
>
> It might be some additional dividers too.

Might be something like this:

TCON CH0 clk ----- dclk_en   - no delay        --------------[mux]--- dclk out
               \\- dclk1_en  - 1/3 phase delay --------------////
                \- dclk2_en  - 2/3 phase delay --------------///
                 \ dclkm2_en - /2 divider - no delay --------//
                                          \ 90 degree delay -/

ChenYu

>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com