* [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC @ 2022-05-30 18:03 Fabien Parent 2022-05-30 18:03 ` [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs Fabien Parent ` (3 more replies) 0 siblings, 4 replies; 10+ messages in thread From: Fabien Parent @ 2022-05-30 18:03 UTC (permalink / raw) To: Yong Wu, Joerg Roedel, Will Deacon, Rob Herring, Krzysztof Kozlowski, Matthias Brugger Cc: Fabien Parent, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel Add IOMMU binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> --- .../bindings/iommu/mediatek,iommu.yaml | 2 + include/dt-bindings/memory/mt8365-larb-port.h | 96 +++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 97e8c471a5e8..5ba688365da5 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -77,6 +77,7 @@ properties: - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two - mediatek,mt8192-m4u # generation two + - mediatek,mt8365-m4u # generation two - description: mt7623 generation one items: @@ -120,6 +121,7 @@ properties: dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, dt-binding/memory/mt8192-larb-port.h for mt8192. + dt-binding/memory/mt8365-larb-port.h for mt8365. power-domains: maxItems: 1 diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h new file mode 100644 index 000000000000..e7d5637aa38e --- /dev/null +++ b/include/dt-bindings/memory/mt8365-larb-port.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 +#define M4U_LARB6_ID 6 +#define M4U_LARB7_ID 7 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(0, 2) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(0, 3) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(0, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(0, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(0, 6) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(0, 7) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(0, 8) +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(0, 9) + +/* larb1 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(1, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(1, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(1, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(1, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(1, 4) +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(1, 5) +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(1, 6) +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(1, 7) +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(1, 8) +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(1, 9) +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(1, 10) +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(1, 11) +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(1, 12) +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(1, 13) +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(1, 14) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(1, 15) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(1, 16) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(1, 17) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(1, 18) + +/* larb2 */ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(2, 0) +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(2, 1) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(2, 2) +#define M4U_PORT_CAM_LCS MTK_M4U_ID(2, 3) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(2, 4) +#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(2, 5) +#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(2, 6) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(2, 7) +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(2, 8) +#define M4U_PORT_CAM_AFO MTK_M4U_ID(2, 9) +#define M4U_PORT_CAM_SPARE MTK_M4U_ID(2, 10) +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(2, 11) +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(2, 12) +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(2, 13) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(2, 14) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(2, 15) +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(2, 16) +#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(2, 17) +#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(2, 18) +#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(2, 19) +#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(2, 20) +#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(2, 21) +#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(2, 22) +#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(2, 23) + +/* larb3 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(3, 0) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(3, 1) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(3, 2) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(3, 3) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(3, 4) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(3, 5) +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(3, 6) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(3, 7) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(3, 8) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(3, 9) +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(3, 10) + +/* larb4 */ +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) + +#endif -- 2.36.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs 2022-05-30 18:03 [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Fabien Parent @ 2022-05-30 18:03 ` Fabien Parent 2022-06-02 6:18 ` Yong Wu 2022-05-30 18:03 ` [PATCH 3/3] iommu: mtk_iommu: add support for MT8365 SoC Fabien Parent ` (2 subsequent siblings) 3 siblings, 1 reply; 10+ messages in thread From: Fabien Parent @ 2022-05-30 18:03 UTC (permalink / raw) To: Yong Wu, Joerg Roedel, Will Deacon, Matthias Brugger Cc: Fabien Parent, iommu, linux-mediatek, linux-arm-kernel, linux-kernel Until now the port ID was always encoded as a 5-bit data. On MT8365, the port ID is encoded as a 6-bit data. This requires to rework the macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order to support 5-bit and 6-bit encoded port IDs. Signed-off-by: Fabien Parent <fparent@baylibre.com> --- drivers/iommu/mtk_iommu.c | 17 +++++++++++++---- drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 6fd75a60abd6..b692347d8d56 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -103,8 +103,10 @@ #define REG_MMU1_INT_ID 0x154 #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) -#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) -#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +#define F_MMU_INT_ID_LARB_ID(a, port_width) \ + ((a) >> ((port_width + 2) & 0x7)) +#define F_MMU_INT_ID_PORT_ID(a, port_width) \ + (((a) >> 2) & GENMASK(port_width - 1, 0)) #define MTK_PROTECT_PA_ALIGN 256 @@ -291,12 +293,13 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) fault_pa |= (u64)pa34_32 << 32; } - fault_port = F_MMU_INT_ID_PORT_ID(regval); + fault_port = F_MMU_INT_ID_PORT_ID(regval, data->plat_data->port_width); if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { fault_larb = F_MMU_INT_ID_COMM_ID(regval); sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); } else { - fault_larb = F_MMU_INT_ID_LARB_ID(regval); + fault_larb = F_MMU_INT_ID_LARB_ID(regval, + data->plat_data->port_width); } fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; @@ -1034,6 +1037,7 @@ static const struct mtk_iommu_plat_data mt2712_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, + .port_width = 5, }; static const struct mtk_iommu_plat_data mt6779_data = { @@ -1043,6 +1047,7 @@ static const struct mtk_iommu_plat_data mt6779_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, + .port_width = 5, }; static const struct mtk_iommu_plat_data mt8167_data = { @@ -1052,6 +1057,7 @@ static const struct mtk_iommu_plat_data mt8167_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ + .port_width = 5, }; static const struct mtk_iommu_plat_data mt8173_data = { @@ -1062,6 +1068,7 @@ static const struct mtk_iommu_plat_data mt8173_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ + .port_width = 5, }; static const struct mtk_iommu_plat_data mt8183_data = { @@ -1071,6 +1078,7 @@ static const struct mtk_iommu_plat_data mt8183_data = { .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, + .port_width = 5, }; static const struct mtk_iommu_plat_data mt8192_data = { @@ -1082,6 +1090,7 @@ static const struct mtk_iommu_plat_data mt8192_data = { .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, {0, 14, 16}, {0, 13, 18, 17}}, + .port_width = 5, }; static const struct of_device_id mtk_iommu_of_ids[] = { diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index b742432220c5..84cecaf6d61c 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -54,6 +54,7 @@ struct mtk_iommu_plat_data { enum mtk_iommu_plat m4u_plat; u32 flags; u32 inv_sel_reg; + u8 port_width; unsigned int iova_region_nr; const struct mtk_iommu_iova_region *iova_region; -- 2.36.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs 2022-05-30 18:03 ` [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs Fabien Parent @ 2022-06-02 6:18 ` Yong Wu 0 siblings, 0 replies; 10+ messages in thread From: Yong Wu @ 2022-06-02 6:18 UTC (permalink / raw) To: Fabien Parent Cc: Joerg Roedel, Will Deacon, Matthias Brugger, iommu, linux-mediatek, linux-arm-kernel, linux-kernel Hi Fabien, Thanks for very much for this patch. Retitle to iommu/mediatek: Xxx On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: > Until now the port ID was always encoded as a 5-bit data. On MT8365, > the port ID is encoded as a 6-bit data. This requires to rework the > macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order > to support 5-bit and 6-bit encoded port IDs. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > drivers/iommu/mtk_iommu.c | 17 +++++++++++++---- > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 6fd75a60abd6..b692347d8d56 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -103,8 +103,10 @@ > #define REG_MMU1_INT_ID 0x154 > #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & > 0x7) > #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) > -#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & > 0x7) > -#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & > 0x1f) > +#define F_MMU_INT_ID_LARB_ID(a, port_width) \ > + ((a) >> ((port_width + 2) & 0x7)) > +#define F_MMU_INT_ID_PORT_ID(a, port_width) \ > + (((a) >> 2) & GENMASK(port_width - 1, > 0)) Add () for port_width. > > #define MTK_PROTECT_PA_ALIGN 256 > > @@ -291,12 +293,13 @@ static irqreturn_t mtk_iommu_isr(int irq, void > *dev_id) > fault_pa |= (u64)pa34_32 << 32; > } > > - fault_port = F_MMU_INT_ID_PORT_ID(regval); > + fault_port = F_MMU_INT_ID_PORT_ID(regval, data->plat_data- > >port_width); > if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { > fault_larb = F_MMU_INT_ID_COMM_ID(regval); > sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); > } else { > - fault_larb = F_MMU_INT_ID_LARB_ID(regval); > + fault_larb = F_MMU_INT_ID_LARB_ID(regval, > + data->plat_data- > >port_width); > } > fault_larb = data->plat_data- > >larbid_remap[fault_larb][sub_comm]; > > @@ -1034,6 +1037,7 @@ static const struct mtk_iommu_plat_data > mt2712_data = { > .iova_region = single_domain, > .iova_region_nr = ARRAY_SIZE(single_domain), > .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, > + .port_width = 5, > }; > > static const struct mtk_iommu_plat_data mt6779_data = { > @@ -1043,6 +1047,7 @@ static const struct mtk_iommu_plat_data > mt6779_data = { > .iova_region = single_domain, > .iova_region_nr = ARRAY_SIZE(single_domain), > .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, > + .port_width = 5, > }; > > static const struct mtk_iommu_plat_data mt8167_data = { > @@ -1052,6 +1057,7 @@ static const struct mtk_iommu_plat_data > mt8167_data = { > .iova_region = single_domain, > .iova_region_nr = ARRAY_SIZE(single_domain), > .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ > + .port_width = 5, > }; > > static const struct mtk_iommu_plat_data mt8173_data = { > @@ -1062,6 +1068,7 @@ static const struct mtk_iommu_plat_data > mt8173_data = { > .iova_region = single_domain, > .iova_region_nr = ARRAY_SIZE(single_domain), > .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear > mapping. */ > + .port_width = 5, > }; > > static const struct mtk_iommu_plat_data mt8183_data = { > @@ -1071,6 +1078,7 @@ static const struct mtk_iommu_plat_data > mt8183_data = { > .iova_region = single_domain, > .iova_region_nr = ARRAY_SIZE(single_domain), > .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, > + .port_width = 5, > }; > > static const struct mtk_iommu_plat_data mt8192_data = { > @@ -1082,6 +1090,7 @@ static const struct mtk_iommu_plat_data > mt8192_data = { > .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), > .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, > {0, 14, 16}, {0, 13, 18, 17}}, > + .port_width = 5, > }; > > static const struct of_device_id mtk_iommu_of_ids[] = { > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index b742432220c5..84cecaf6d61c 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -54,6 +54,7 @@ struct mtk_iommu_plat_data { > enum mtk_iommu_plat m4u_plat; > u32 flags; > u32 inv_sel_reg; > + u8 port_width; Please help rename to int_id_port_width for more detailed from the register name (REG_MMU0_INT_ID). > > unsigned int iova_region_nr; > const struct mtk_iommu_iova_region *iova_region; > -- > 2.36.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] iommu: mtk_iommu: add support for MT8365 SoC 2022-05-30 18:03 [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Fabien Parent 2022-05-30 18:03 ` [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs Fabien Parent @ 2022-05-30 18:03 ` Fabien Parent 2022-07-20 8:52 ` Amjad Ouled-Ameur 2022-06-02 6:18 ` [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation " Yong Wu 2022-06-05 21:13 ` Rob Herring 3 siblings, 1 reply; 10+ messages in thread From: Fabien Parent @ 2022-05-30 18:03 UTC (permalink / raw) To: Yong Wu, Joerg Roedel, Will Deacon, Matthias Brugger Cc: Fabien Parent, iommu, linux-mediatek, linux-arm-kernel, linux-kernel Add IOMMU support for MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> --- drivers/iommu/mtk_iommu.c | 11 +++++++++++ drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index b692347d8d56..039b8f9d5022 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1093,6 +1093,16 @@ static const struct mtk_iommu_plat_data mt8192_data = { .port_width = 5, }; +static const struct mtk_iommu_plat_data mt8365_data = { + .m4u_plat = M4U_MT8365, + .flags = RESET_AXI, + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .iova_region = single_domain, + .iova_region_nr = ARRAY_SIZE(single_domain), + .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ + .port_width = 6, +}; + static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, @@ -1100,6 +1110,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, + { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data}, {} }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 84cecaf6d61c..cb174fa6f2ab 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -46,6 +46,7 @@ enum mtk_iommu_plat { M4U_MT8173, M4U_MT8183, M4U_MT8192, + M4U_MT8365, }; struct mtk_iommu_iova_region; -- 2.36.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] iommu: mtk_iommu: add support for MT8365 SoC 2022-05-30 18:03 ` [PATCH 3/3] iommu: mtk_iommu: add support for MT8365 SoC Fabien Parent @ 2022-07-20 8:52 ` Amjad Ouled-Ameur 0 siblings, 0 replies; 10+ messages in thread From: Amjad Ouled-Ameur @ 2022-07-20 8:52 UTC (permalink / raw) To: fparent Cc: iommu, joro, linux-arm-kernel, linux-kernel, linux-mediatek, matthias.bgg, will, yong.wu, Amjad Ouled-Ameur Hi Fabien, Thank you for the fix. The kernel would panic if you boot with this patchset because bank_nr and bank_enable are not set in mt8365_data. Please add this change: --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1538,6 +1538,8 @@ static const struct mtk_iommu_plat_data mt8365_data = { .m4u_plat = M4U_MT8365, .flags = RESET_AXI, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, + .banks_num = 1, + .banks_enable = {true}, .iova_region = single_domain, .iova_region_nr = ARRAY_SIZE(single_domain), .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ With this change, please add my: Reviewed-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Tested-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Regards, Amjad ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC 2022-05-30 18:03 [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Fabien Parent 2022-05-30 18:03 ` [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs Fabien Parent 2022-05-30 18:03 ` [PATCH 3/3] iommu: mtk_iommu: add support for MT8365 SoC Fabien Parent @ 2022-06-02 6:18 ` Yong Wu 2022-06-02 8:27 ` Macpaul Lin 2022-06-05 21:13 ` Rob Herring 3 siblings, 1 reply; 10+ messages in thread From: Yong Wu @ 2022-06-02 6:18 UTC (permalink / raw) To: Fabien Parent Cc: Joerg Roedel, Will Deacon, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: > Add IOMMU binding documentation for the MT8365 SoC. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > .../bindings/iommu/mediatek,iommu.yaml | 2 + > include/dt-bindings/memory/mt8365-larb-port.h | 96 > +++++++++++++++++++ > 2 files changed, 98 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h [snip...] > +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > + > +#include <dt-bindings/memory/mtk-memory-port.h> > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > +#define M4U_LARB3_ID 3 > +#define M4U_LARB4_ID 4 > +#define M4U_LARB5_ID 5 > +#define M4U_LARB6_ID 6 > +#define M4U_LARB7_ID 7 Remove these. they are no used, right? > + > +/* larb0 */ > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) [...] > > +/* larb4 */ > +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) > +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) Please remove these two APU definitions. currently these are not supported. Thanks. > + > +#endif ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC 2022-06-02 6:18 ` [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation " Yong Wu @ 2022-06-02 8:27 ` Macpaul Lin 2022-06-02 8:42 ` Macpaul Lin 0 siblings, 1 reply; 10+ messages in thread From: Macpaul Lin @ 2022-06-02 8:27 UTC (permalink / raw) To: Yong Wu, Fabien Parent Cc: Joerg Roedel, Will Deacon, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Bear Wang, Macross Chen, Kidd-KW Chen, Andy Hsieh, Pablo Sun On 6/2/22 2:18 PM, Yong Wu wrote: > On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: >> Add IOMMU binding documentation for the MT8365 SoC. >> >> Signed-off-by: Fabien Parent <fparent@baylibre.com> >> --- >> .../bindings/iommu/mediatek,iommu.yaml | 2 + >> include/dt-bindings/memory/mt8365-larb-port.h | 96 >> +++++++++++++++++++ >> 2 files changed, 98 insertions(+) >> create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h > > [snip...] > >> +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ >> +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ >> + >> +#include <dt-bindings/memory/mtk-memory-port.h> >> + >> +#define M4U_LARB0_ID 0 >> +#define M4U_LARB1_ID 1 >> +#define M4U_LARB2_ID 2 >> +#define M4U_LARB3_ID 3 >> +#define M4U_LARB4_ID 4 >> +#define M4U_LARB5_ID 5 >> +#define M4U_LARB6_ID 6 >> +#define M4U_LARB7_ID 7 > > Remove these. they are no used, right? AIOT and customers are using the modules and their related IOMMU modules. DISP0, VENC, VDEC, ISP (CAMSYS), and APU (as far as I know, which should be VP6?) were all supported. > >> + >> +/* larb0 */ >> +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) >> +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) > > [...] > >> >> +/* larb4 */ >> +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) >> +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) > > Please remove these two APU definitions. currently these are not > supported. Kidd, please help to check if APU use these definitions with Yong. However, I think these are all available to the customers. Thanks Macpaul Lin ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC 2022-06-02 8:27 ` Macpaul Lin @ 2022-06-02 8:42 ` Macpaul Lin 2022-06-02 9:26 ` Yong Wu 0 siblings, 1 reply; 10+ messages in thread From: Macpaul Lin @ 2022-06-02 8:42 UTC (permalink / raw) To: Yong Wu, Fabien Parent Cc: Joerg Roedel, Will Deacon, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Bear Wang, Macross Chen, Kidd-KW Chen, Andy Hsieh, Pablo Sun On 6/2/22 4:27 PM, Macpaul Lin wrote: > On 6/2/22 2:18 PM, Yong Wu wrote: >> On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: >>> Add IOMMU binding documentation for the MT8365 SoC. >>> >>> Signed-off-by: Fabien Parent <fparent@baylibre.com> >>> --- >>> .../bindings/iommu/mediatek,iommu.yaml | 2 + >>> include/dt-bindings/memory/mt8365-larb-port.h | 96 >>> +++++++++++++++++++ >>> 2 files changed, 98 insertions(+) >>> create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h >> >> [snip...] >> >>> +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ >>> +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ >>> + >>> +#include <dt-bindings/memory/mtk-memory-port.h> >>> + >>> +#define M4U_LARB0_ID 0 >>> +#define M4U_LARB1_ID 1 >>> +#define M4U_LARB2_ID 2 >>> +#define M4U_LARB3_ID 3 >>> +#define M4U_LARB4_ID 4 >>> +#define M4U_LARB5_ID 5 >>> +#define M4U_LARB6_ID 6 >>> +#define M4U_LARB7_ID 7 >> >> Remove these. they are no used, right? > > AIOT and customers are using the modules and their related IOMMU modules. > DISP0, VENC, VDEC, ISP (CAMSYS), and APU (as far as I know, which should > be VP6?) were all supported. Dear Yong, How about to replace the following definitions? For example, replace #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) to #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID , 0) >> >>> + >>> +/* larb0 */ >>> +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) >>> +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) >> >> [...] >> >>> >>> +/* larb4 */ >>> +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) >>> +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) >> >> Please remove these two APU definitions. currently these are not >> supported. > > Kidd, please help to check if APU use these definitions with Yong. > However, I think these are all available to the customers. > > Thanks > Macpaul Lin Thanks Macpaul Lin ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC 2022-06-02 8:42 ` Macpaul Lin @ 2022-06-02 9:26 ` Yong Wu 0 siblings, 0 replies; 10+ messages in thread From: Yong Wu @ 2022-06-02 9:26 UTC (permalink / raw) To: Macpaul Lin, Fabien Parent Cc: Joerg Roedel, Will Deacon, Rob Herring, Krzysztof Kozlowski, Matthias Brugger, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Bear Wang, Macross Chen, Kidd-KW Chen, Andy Hsieh, Pablo Sun On Thu, 2022-06-02 at 16:42 +0800, Macpaul Lin wrote: > On 6/2/22 4:27 PM, Macpaul Lin wrote: > > On 6/2/22 2:18 PM, Yong Wu wrote: > > > On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: > > > > Add IOMMU binding documentation for the MT8365 SoC. > > > > > > > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > > > > --- > > > > .../bindings/iommu/mediatek,iommu.yaml | 2 + > > > > include/dt-bindings/memory/mt8365-larb-port.h | 96 > > > > +++++++++++++++++++ > > > > 2 files changed, 98 insertions(+) > > > > create mode 100644 include/dt-bindings/memory/mt8365-larb- > > > > port.h > > > > > > [snip...] > > > > > > > +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > > > > +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ > > > > + > > > > +#include <dt-bindings/memory/mtk-memory-port.h> > > > > + > > > > +#define M4U_LARB0_ID 0 > > > > +#define M4U_LARB1_ID 1 > > > > +#define M4U_LARB2_ID 2 > > > > +#define M4U_LARB3_ID 3 > > > > +#define M4U_LARB4_ID 4 > > > > +#define M4U_LARB5_ID 5 > > > > +#define M4U_LARB6_ID 6 > > > > +#define M4U_LARB7_ID 7 > > > > > > Remove these. they are no used, right? > > > > AIOT and customers are using the modules and their related IOMMU > > modules. > > DISP0, VENC, VDEC, ISP (CAMSYS), and APU (as far as I know, which > > should > > be VP6?) were all supported. > > Dear Yong, > How about to replace the following definitions? > > For example, replace > #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) > to > #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID , 0) Yes. It is ok. > > > > > > > > + > > > > +/* larb0 */ > > > > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) > > > > +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1) > > > > > > [...] > > > > > > > > > > > +/* larb4 */ > > > > +#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0) > > > > +#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1) > > > > > > Please remove these two APU definitions. currently these are not > > > supported. > > > > Kidd, please help to check if APU use these definitions with Yong. > > However, I think these are all available to the customers. > > > > Thanks > > Macpaul Lin > > Thanks > Macpaul Lin ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC 2022-05-30 18:03 [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Fabien Parent ` (2 preceding siblings ...) 2022-06-02 6:18 ` [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation " Yong Wu @ 2022-06-05 21:13 ` Rob Herring 3 siblings, 0 replies; 10+ messages in thread From: Rob Herring @ 2022-06-05 21:13 UTC (permalink / raw) To: Fabien Parent Cc: Yong Wu, Joerg Roedel, Will Deacon, Krzysztof Kozlowski, Matthias Brugger, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel On Mon, May 30, 2022 at 08:03:26PM +0200, Fabien Parent wrote: > Add IOMMU binding documentation for the MT8365 SoC. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> > --- > .../bindings/iommu/mediatek,iommu.yaml | 2 + > include/dt-bindings/memory/mt8365-larb-port.h | 96 +++++++++++++++++++ > 2 files changed, 98 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > index 97e8c471a5e8..5ba688365da5 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -77,6 +77,7 @@ properties: > - mediatek,mt8173-m4u # generation two > - mediatek,mt8183-m4u # generation two > - mediatek,mt8192-m4u # generation two > + - mediatek,mt8365-m4u # generation two > > - description: mt7623 generation one > items: > @@ -120,6 +121,7 @@ properties: > dt-binding/memory/mt8173-larb-port.h for mt8173, > dt-binding/memory/mt8183-larb-port.h for mt8183, > dt-binding/memory/mt8192-larb-port.h for mt8192. > + dt-binding/memory/mt8365-larb-port.h for mt8365. > > power-domains: > maxItems: 1 > diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h > new file mode 100644 > index 000000000000..e7d5637aa38e > --- /dev/null > +++ b/include/dt-bindings/memory/mt8365-larb-port.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license please. Rob ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-07-20 8:59 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-30 18:03 [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Fabien Parent 2022-05-30 18:03 ` [PATCH 2/3] iommu: mtk_iommu: add support for 6-bit encoded port IDs Fabien Parent 2022-06-02 6:18 ` Yong Wu 2022-05-30 18:03 ` [PATCH 3/3] iommu: mtk_iommu: add support for MT8365 SoC Fabien Parent 2022-07-20 8:52 ` Amjad Ouled-Ameur 2022-06-02 6:18 ` [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation " Yong Wu 2022-06-02 8:27 ` Macpaul Lin 2022-06-02 8:42 ` Macpaul Lin 2022-06-02 9:26 ` Yong Wu 2022-06-05 21:13 ` Rob Herring
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