From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
To: Bhupesh Sharma <bhupesh.sharma@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org
Cc: bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, robh+dt@kernel.org,
agross@kernel.org, herbert@gondor.apana.org.au,
davem@davemloft.net, Thara Gopinath <thara.gopinath@linaro.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCH v4 14/20] crypto: qce: core: Add support to initialize interconnect path
Date: Wed, 13 Oct 2021 22:19:32 +0300 [thread overview]
Message-ID: <8f7eee67-7394-4938-7ace-f1dee397db2b@linaro.org> (raw)
In-Reply-To: <20211013105541.68045-15-bhupesh.sharma@linaro.org>
Hi Bhupesh,
On 10/13/21 1:55 PM, Bhupesh Sharma wrote:
> From: Thara Gopinath <thara.gopinath@linaro.org>
>
> Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
> etc. requires interconnect path between the engine and memory to be
> explicitly enabled and bandwidth set prior to any operations. Add support
> in the qce core to enable the interconnect path appropriately.
>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> [Make header file inclusion alphabetical]
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
> drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++-------
> drivers/crypto/qce/core.h | 1 +
> 2 files changed, 29 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index d3780be44a76..033c7278aa5d 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -5,6 +5,7 @@
>
> #include <linux/clk.h>
> #include <linux/dma-mapping.h>
> +#include <linux/interconnect.h>
> #include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/mod_devicetable.h>
> @@ -22,6 +23,8 @@
> #define QCE_MAJOR_VERSION5 0x05
> #define QCE_QUEUE_LENGTH 1
>
> +#define QCE_DEFAULT_MEM_BANDWIDTH 393600
> +
> static const struct qce_algo_ops *qce_ops[] = {
> #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
> &skcipher_ops,
> @@ -206,21 +209,35 @@ static int qce_crypto_probe(struct platform_device *pdev)
> if (ret < 0)
> return ret;
>
> + qce->mem_path = of_icc_get(qce->dev, "memory");
Please consider to use devm_of_icc_get() here also.
> + if (IS_ERR(qce->mem_path))
> + return PTR_ERR(qce->mem_path);
> +
> qce->core = devm_clk_get(qce->dev, "core");
> - if (IS_ERR(qce->core))
> - return PTR_ERR(qce->core);
> + if (IS_ERR(qce->core)) {
> + ret = PTR_ERR(qce->core);
> + goto err_mem_path_put;
> + }
>
> qce->iface = devm_clk_get(qce->dev, "iface");
> - if (IS_ERR(qce->iface))
> - return PTR_ERR(qce->iface);
> + if (IS_ERR(qce->iface)) {
> + ret = PTR_ERR(qce->iface);
> + goto err_mem_path_put;
> + }
>
> qce->bus = devm_clk_get(qce->dev, "bus");
> - if (IS_ERR(qce->bus))
> - return PTR_ERR(qce->bus);
> + if (IS_ERR(qce->bus)) {
> + ret = PTR_ERR(qce->bus);
> + goto err_mem_path_put;
> + }
> +
> + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> + if (ret)
> + goto err_mem_path_put;
>
> ret = clk_prepare_enable(qce->core);
> if (ret)
> - return ret;
> + goto err_mem_path_disable;
>
> ret = clk_prepare_enable(qce->iface);
> if (ret)
> @@ -260,6 +277,10 @@ static int qce_crypto_probe(struct platform_device *pdev)
> clk_disable_unprepare(qce->iface);
> err_clks_core:
> clk_disable_unprepare(qce->core);
> +err_mem_path_disable:
> + icc_set_bw(qce->mem_path, 0, 0);
> +err_mem_path_put:
> + icc_put(qce->mem_path);
> return ret;
> }
>
> diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> index 085774cdf641..228fcd69ec51 100644
> --- a/drivers/crypto/qce/core.h
> +++ b/drivers/crypto/qce/core.h
> @@ -35,6 +35,7 @@ struct qce_device {
> void __iomem *base;
> struct device *dev;
> struct clk *core, *iface, *bus;
> + struct icc_path *mem_path;
> struct qce_dma_data dma;
> int burst_size;
> unsigned int pipe_pair_id;
>
--
Best wishes,
Vladimir
next prev parent reply other threads:[~2021-10-13 19:19 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 10:55 [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 01/20] arm64/dts: qcom: Fix 'dma' & 'qcom,controlled-remotely' nodes in dts Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 02/20] arm64/dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 03/20] arm64/dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 04/20] dt-bindings: qcom-bam: Convert binding to YAML Bhupesh Sharma
2021-10-13 12:56 ` Vladimir Zapolskiy
2021-10-13 17:13 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 05/20] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Bhupesh Sharma
2021-10-13 13:03 ` Vladimir Zapolskiy
2021-10-13 17:14 ` Bhupesh Sharma
2021-10-13 18:39 ` Rob Herring
2021-10-14 7:03 ` Bhupesh Sharma
2021-10-24 13:55 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 06/20] dt-bindings: qcom-bam: Add 'iommus' " Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml Bhupesh Sharma
2021-10-13 13:05 ` Vladimir Zapolskiy
2021-10-13 17:15 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 08/20] dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties Bhupesh Sharma
2021-10-26 19:40 ` Rob Herring
2021-10-13 10:55 ` [PATCH v4 09/20] dt-bindings: qcom-qce: Add 'iommus' " Bhupesh Sharma
2021-10-26 19:40 ` Rob Herring
2021-10-13 10:55 ` [PATCH v4 10/20] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 11/20] dt-bindings: crypto : Add new compatible strings for qcom-qce Bhupesh Sharma
2021-10-18 18:26 ` Rob Herring
2021-10-13 10:55 ` [PATCH v4 12/20] arm64/dts: qcom: Use new compatibles for crypto nodes Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 13/20] dma: qcom: bam_dma: Add support to initialize interconnect path Bhupesh Sharma
2021-10-13 19:15 ` Vladimir Zapolskiy
2021-10-24 13:53 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 14/20] crypto: qce: core: " Bhupesh Sharma
2021-10-13 19:19 ` Vladimir Zapolskiy [this message]
2021-10-24 13:53 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 15/20] crypto: qce: Add new compatibles for qce crypto driver Bhupesh Sharma
2021-10-13 19:22 ` Vladimir Zapolskiy
2021-10-20 14:07 ` Thara Gopinath
2021-10-24 13:52 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 16/20] crypto: qce: core: Make clocks optional Bhupesh Sharma
2021-10-13 19:23 ` Vladimir Zapolskiy
2021-10-24 13:34 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 17/20] crypto: qce: Print a failure msg in case probe() fails Bhupesh Sharma
2021-10-13 19:26 ` Vladimir Zapolskiy
2021-10-24 13:33 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 18/20] crypto: qce: Defer probing if BAM dma channel is not yet initialized Bhupesh Sharma
2021-10-13 20:49 ` Vladimir Zapolskiy
2021-10-14 7:40 ` Bhupesh Sharma
2021-10-14 8:42 ` Vladimir Zapolskiy
2021-10-20 14:10 ` Thara Gopinath
2021-10-24 14:05 ` Bhupesh Sharma
2021-10-13 10:55 ` [PATCH v4 19/20] crypto: qce: Add 'sm8250-qce' compatible string check Bhupesh Sharma
2021-10-20 14:11 ` Thara Gopinath
2021-10-13 10:55 ` [PATCH v4 20/20] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine Bhupesh Sharma
2021-10-20 14:03 ` [PATCH v4 00/20] Enable Qualcomm Crypto Engine on sm8250 Thara Gopinath
2021-10-24 13:58 ` Bhupesh Sharma
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8f7eee67-7394-4938-7ace-f1dee397db2b@linaro.org \
--to=vladimir.zapolskiy@linaro.org \
--cc=agross@kernel.org \
--cc=bhupesh.linux@gmail.com \
--cc=bhupesh.sharma@linaro.org \
--cc=bjorn.andersson@linaro.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=herbert@gondor.apana.org.au \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=thara.gopinath@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).