* Re: [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations [not found] ` <1584172319-24843-3-git-send-email-wcheng@codeaurora.org> @ 2020-03-16 17:03 ` Stephen Boyd 2020-03-16 19:58 ` Wesley Cheng 0 siblings, 1 reply; 4+ messages in thread From: Stephen Boyd @ 2020-03-16 17:03 UTC (permalink / raw) To: Wesley Cheng, agross, bjorn.andersson, mark.rutland, mturquette, robh+dt Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Wesley Cheng Quoting Wesley Cheng (2020-03-14 00:51:58) > Add the USB3 PIPE clock structures, so that the USB driver can > vote for the GCC to enable/disable it when required. This clock > is needed for SSUSB operation. > > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > --- > drivers/clk/qcom/gcc-sm8150.c | 26 ++++++++++++++++++++++++++ Can you please combine these two patches and add sm8150 in the subject? > 1 file changed, 26 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c > index d0cd03d..ef98fdc 100644 > --- a/drivers/clk/qcom/gcc-sm8150.c > +++ b/drivers/clk/qcom/gcc-sm8150.c > @@ -3172,6 +3172,18 @@ enum { > }, > }; > > +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0xf058, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_usb3_prim_phy_pipe_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_usb3_sec_clkref_clk = { > .halt_reg = 0x8c028, > .halt_check = BRANCH_HALT, > @@ -3219,6 +3231,18 @@ enum { > }, > }; > > +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { > + .halt_check = BRANCH_HALT_SKIP, Sad to see that we'll never resolve this. ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations 2020-03-16 17:03 ` [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations Stephen Boyd @ 2020-03-16 19:58 ` Wesley Cheng 0 siblings, 0 replies; 4+ messages in thread From: Wesley Cheng @ 2020-03-16 19:58 UTC (permalink / raw) To: Stephen Boyd, agross, bjorn.andersson, mark.rutland, mturquette, robh+dt Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree Hi Stephen, Thanks for the feedback. On 3/16/2020 10:03 AM, Stephen Boyd wrote: > Quoting Wesley Cheng (2020-03-14 00:51:58) >> Add the USB3 PIPE clock structures, so that the USB driver can >> vote for the GCC to enable/disable it when required. This clock >> is needed for SSUSB operation. >> >> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> >> --- >> drivers/clk/qcom/gcc-sm8150.c | 26 ++++++++++++++++++++++++++ > > Can you please combine these two patches and add sm8150 in the subject? > Sure, I'll combine the two patches into one and include the SM8150 tag in the subject on the next patch series. >> 1 file changed, 26 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c >> index d0cd03d..ef98fdc 100644 >> --- a/drivers/clk/qcom/gcc-sm8150.c >> +++ b/drivers/clk/qcom/gcc-sm8150.c >> @@ -3172,6 +3172,18 @@ enum { >> }, >> }; >> >> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { >> + .halt_check = BRANCH_HALT_SKIP, >> + .clkr = { >> + .enable_reg = 0xf058, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_usb3_prim_phy_pipe_clk", >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_usb3_sec_clkref_clk = { >> .halt_reg = 0x8c028, >> .halt_check = BRANCH_HALT, >> @@ -3219,6 +3231,18 @@ enum { >> }, >> }; >> >> +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { >> + .halt_check = BRANCH_HALT_SKIP, > > Sad to see that we'll never resolve this. > -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <1584172319-24843-4-git-send-email-wcheng@codeaurora.org>]
* Re: [PATCH 3/3] arm64: dts: qcom: sm8150: Add USB and PHY device nodes [not found] ` <1584172319-24843-4-git-send-email-wcheng@codeaurora.org> @ 2020-03-16 22:24 ` Bjorn Andersson 2020-03-16 23:59 ` Wesley Cheng 0 siblings, 1 reply; 4+ messages in thread From: Bjorn Andersson @ 2020-03-16 22:24 UTC (permalink / raw) To: Wesley Cheng Cc: agross, mturquette, sboyd, robh+dt, mark.rutland, linux-arm-msm, linux-clk, linux-kernel, devicetree, Jack Pham On Sat 14 Mar 00:51 PDT 2020, Wesley Cheng wrote: > From: Jack Pham <jackp@codeaurora.org> > > Add device nodes for the USB3 controller, QMP SS PHY and > SNPS HS PHY. > > Signed-off-by: Jack Pham <jackp@codeaurora.org> > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 17 ++++++ > arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++++++ > 2 files changed, 109 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts > index 8ab1661..edf0abc 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts > @@ -408,3 +408,20 @@ > vdda-pll-supply = <&vreg_l3c_1p2>; > vdda-pll-max-microamp = <19000>; > }; > + > +&usb_1_hsphy { > + status = "okay"; > + vdda-pll-supply = <&vdd_usb_hs_core>; > + vdda33-supply = <&vdda_usb_hs_3p1>; > + vdda18-supply = <&vdda_usb_hs_1p8>; > +}; > + > +&usb_1_qmpphy { > + status = "okay"; > + vdda-phy-supply = <&vreg_l3c_1p2>; > + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; > +}; > + > +&usb_1 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 141c21d..cf58fb7 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -855,6 +855,98 @@ > > #freq-domain-cells = <1>; > }; > + > + usb_1_hsphy: phy@88e2000 { Please sort these nodes by address, i.e. this should come right after the cdsp remoteproc node. Apart from that this looks good, thank you! Regards, Bjorn > + compatible = "qcom,usb-snps-hs-7nm-phy", > + "qcom,sm8150-usb-hs-phy"; > + reg = <0 0x088e2000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_1_qmpphy: phy@88e9000 { > + compatible = "qcom,sm8150-qmp-usb3-phy"; > + reg = <0 0x088e9000 0 0x18c>, > + <0 0x088e8000 0 0x10>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #clock-cells = <1>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: lanes@88e9200 { > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x218>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB3_SEC_CLKREF_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep", "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <150000000>; > + > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xcd00>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; > + }; > }; > > timer { > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: sm8150: Add USB and PHY device nodes 2020-03-16 22:24 ` [PATCH 3/3] arm64: dts: qcom: sm8150: Add USB and PHY device nodes Bjorn Andersson @ 2020-03-16 23:59 ` Wesley Cheng 0 siblings, 0 replies; 4+ messages in thread From: Wesley Cheng @ 2020-03-16 23:59 UTC (permalink / raw) To: Bjorn Andersson Cc: agross, mturquette, sboyd, robh+dt, mark.rutland, linux-arm-msm, linux-clk, linux-kernel, devicetree, Jack Pham On 3/16/2020 3:24 PM, Bjorn Andersson wrote: > On Sat 14 Mar 00:51 PDT 2020, Wesley Cheng wrote: > >> From: Jack Pham <jackp@codeaurora.org> >> >> Add device nodes for the USB3 controller, QMP SS PHY and >> SNPS HS PHY. >> >> Signed-off-by: Jack Pham <jackp@codeaurora.org> >> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 17 ++++++ >> arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++++++ >> 2 files changed, 109 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts >> index 8ab1661..edf0abc 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts >> +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts >> @@ -408,3 +408,20 @@ >> vdda-pll-supply = <&vreg_l3c_1p2>; >> vdda-pll-max-microamp = <19000>; >> }; >> + >> +&usb_1_hsphy { >> + status = "okay"; >> + vdda-pll-supply = <&vdd_usb_hs_core>; >> + vdda33-supply = <&vdda_usb_hs_3p1>; >> + vdda18-supply = <&vdda_usb_hs_1p8>; >> +}; >> + >> +&usb_1_qmpphy { >> + status = "okay"; >> + vdda-phy-supply = <&vreg_l3c_1p2>; >> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; >> +}; >> + >> +&usb_1 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi >> index 141c21d..cf58fb7 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi >> @@ -855,6 +855,98 @@ >> >> #freq-domain-cells = <1>; >> }; >> + >> + usb_1_hsphy: phy@88e2000 { > > Please sort these nodes by address, i.e. this should come right after > the cdsp remoteproc node. > > > Apart from that this looks good, thank you! > > Regards, > Bjorn > Hi Bjorn, Thanks for the update, will remember this for future changes as well! Will update this in the next patch series. >> + compatible = "qcom,usb-snps-hs-7nm-phy", >> + "qcom,sm8150-usb-hs-phy"; >> + reg = <0 0x088e2000 0 0x400>; >> + status = "disabled"; >> + #phy-cells = <0>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "ref"; >> + >> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; >> + }; >> + >> + usb_1_qmpphy: phy@88e9000 { >> + compatible = "qcom,sm8150-qmp-usb3-phy"; >> + reg = <0 0x088e9000 0 0x18c>, >> + <0 0x088e8000 0 0x10>; >> + reg-names = "reg-base", "dp_com"; >> + status = "disabled"; >> + #clock-cells = <1>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, >> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; >> + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; >> + >> + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, >> + <&gcc GCC_USB3_PHY_PRIM_BCR>; >> + reset-names = "phy", "common"; >> + >> + usb_1_ssphy: lanes@88e9200 { >> + reg = <0 0x088e9200 0 0x200>, >> + <0 0x088e9400 0 0x200>, >> + <0 0x088e9c00 0 0x218>, >> + <0 0x088e9600 0 0x200>, >> + <0 0x088e9800 0 0x200>, >> + <0 0x088e9a00 0 0x100>; >> + #phy-cells = <0>; >> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >> + clock-names = "pipe0"; >> + clock-output-names = "usb3_phy_pipe_clk_src"; >> + }; >> + }; >> + >> + usb_1: usb@a6f8800 { >> + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; >> + reg = <0 0x0a6f8800 0 0x400>; >> + status = "disabled"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + dma-ranges; >> + >> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>, >> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, >> + <&gcc GCC_USB3_SEC_CLKREF_CLK>; >> + clock-names = "cfg_noc", "core", "iface", "mock_utmi", >> + "sleep", "xo"; >> + >> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>; >> + assigned-clock-rates = <19200000>, <150000000>; >> + >> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hs_phy_irq", "ss_phy_irq", >> + "dm_hs_phy_irq", "dp_hs_phy_irq"; >> + >> + power-domains = <&gcc USB30_PRIM_GDSC>; >> + >> + resets = <&gcc GCC_USB30_PRIM_BCR>; >> + >> + usb_1_dwc3: dwc3@a600000 { >> + compatible = "snps,dwc3"; >> + reg = <0 0x0a600000 0 0xcd00>; >> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_enblslpm_quirk; >> + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; >> + phy-names = "usb2-phy", "usb3-phy"; >> + }; >> + }; >> }; >> >> timer { >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> a Linux Foundation Collaborative Project -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-03-16 23:59 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <1584172319-24843-1-git-send-email-wcheng@codeaurora.org>
[not found] ` <1584172319-24843-3-git-send-email-wcheng@codeaurora.org>
2020-03-16 17:03 ` [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations Stephen Boyd
2020-03-16 19:58 ` Wesley Cheng
[not found] ` <1584172319-24843-4-git-send-email-wcheng@codeaurora.org>
2020-03-16 22:24 ` [PATCH 3/3] arm64: dts: qcom: sm8150: Add USB and PHY device nodes Bjorn Andersson
2020-03-16 23:59 ` Wesley Cheng
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).