RE: [PATCH v2 5/5] usb:cdns3 Add Cadence USB3 DRD Driver

From: Pawel Laszczak <pawell@cadence.com>
To: Peter Chen <peter.chen@nxp.com>, Peter Chen <hzpeterchen@gmail.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
	"hdegoede@redhat.com" <hdegoede@redhat.com>,
	Heikki Krogerus <heikki.krogerus@linux.intel.com>,
	"andy.shevchenko@gmail.com" <andy.shevchenko@gmail.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"rogerq@ti.com" <rogerq@ti.com>,
	lkml <linux-kernel@vger.kernel.org>,
	Alan Douglas <adouglas@cadence.com>,
	"jbergsagel@ti.com" <jbergsagel@ti.com>,
	"nsekhar@ti.com" <nsekhar@ti.com>, "nm@ti.com" <nm@ti.com>,
	Suresh Punnoose <sureshp@cadence.com>,
	Pawel Jez <pjez@cadence.com>, Rahul Kumar <kurahul@cadence.com>
Subject: RE: [PATCH v2 5/5] usb:cdns3 Add Cadence USB3 DRD Driver
Date: Mon, 31 Dec 2018 05:32:20 +0000	[thread overview]
Message-ID: <BYAPR07MB4709D8F210206B31093F9ACDDDB20@BYAPR07MB4709.namprd07.prod.outlook.com> (raw)
In-Reply-To: <VI1PR04MB53274270615A700AB36967F78BB70@VI1PR04MB5327.eurprd04.prod.outlook.com>

Hi Peter,
>
>> >
>> >@@ -299,6 +306,7 @@ int cdns3_drd_init(struct cdns3 *cdns)
>> >                cdns->version  = CDNS3_CONTROLLER_V0;
>> >                cdns->otg_v1_regs = NULL;
>> >                cdns->otg_regs = regs;
>> >+               writel(0x1, &cdns->otg_v0_regs->simulate);
>> >                dev_info(cdns->dev, "DRD version v0 (%08x)\n",
>> >                         readl(&cdns->otg_v0_regs->version));
>> >        } else {
>>
>> I have confirmation from HW team that time that driver should wait after de-
>> selecting mode is 2-3ms for simulate mode. It's time when FSM is in
>> DRD_H_WAIT_VBUS_FAIL.
>> Driver cannot re-enable the host/device mode before this time has elapsed.
>>
>> 3 ms is the maximum time. Additionally, you can confirm the current FSM state by
>> reading the host_otg_state (bit 5:3) or dev_otg_state (2:0)  from OTGSTATE
>> register.
>>
>> If bit 0 in simulate register is cleared the time is exactly 1s.
>>
>
>Thanks, Pawel.
>
>Would you please add below changes in your next revision?
>- Set bit 0 in simulate register
But it's used only for simulation environments to speed up simulation. 
On real platforms this bit should be cleared. I'm not sure if I can 
add some code related to simulation environment to driver. 
If yes then I must introduce the way, that allow to recognize this two modes. 
I could add module parameter or add additional config in Kconfig file.

>- timeout logic for waiting host_otg_state or dev_otg_state at OTGSTATE
>when switch to host or device.

I will add such code. 

Pawel