* Re: [PATCH v9 03/14] dt-bindings: mediatek: display: split each block to individual yaml
[not found] ` <20210825144833.7757-4-jason-jh.lin@mediatek.com>
@ 2021-09-03 23:08 ` Chun-Kuang Hu
0 siblings, 0 replies; 3+ messages in thread
From: Chun-Kuang Hu @ 2021-09-03 23:08 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
Enric Balletbo i Serra, Frank Wunderlich, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, fshao, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月25日 週三 下午10:48寫道：
>
> 1. Remove mediatek,dislpay.txt
> 2. Split each display function block to individual yaml file.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,aal.yaml | 75 ++++++
> .../display/mediatek/mediatek,ccorr.yaml | 69 ++++++
> .../display/mediatek/mediatek,color.yaml | 84 +++++++
> .../display/mediatek/mediatek,disp.txt | 219 ------------------
> .../display/mediatek/mediatek,dither.yaml | 70 ++++++
> .../display/mediatek/mediatek,gamma.yaml | 71 ++++++
> .../display/mediatek/mediatek,merge.yaml | 66 ++++++
> .../display/mediatek/mediatek,mutex.yaml | 77 ++++++
> .../display/mediatek/mediatek,od.yaml | 52 +++++
> .../display/mediatek/mediatek,ovl-2l.yaml | 86 +++++++
> .../display/mediatek/mediatek,ovl.yaml | 96 ++++++++
> .../display/mediatek/mediatek,rdma.yaml | 110 +++++++++
> .../display/mediatek/mediatek,split.yaml | 56 +++++
> .../display/mediatek/mediatek,ufoe.yaml | 59 +++++
> .../display/mediatek/mediatek,wdma.yaml | 86 +++++++
> 15 files changed, 1057 insertions(+), 219 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
Because mutex does not only control display function block, but also
control mdp function block, so move mutex binding document to the same
folder of mmsys.
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
>
[snip]
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> new file mode 100644
> index 000000000000..939dff14d989
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek display mutex
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + The mediatek display mutex is used to send the triggers signals called
> + Start Of Frame (SOF)/ Error Of Frame (EOF) to each sub-modules on the
EOF is End of Frame.
> + display data path
In some SoC, such as mt2701, MUTEX could be a hardware mutex which
protect the shadow register. Please describe this because this is a
main function and this is why it's called MUTEX.
Regards,
Chun-Kuang.
.
> + MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> + For a description of the MMSYS_CONFIG binding, see
> + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: mediatek,mt2701-disp-mutex
> + - items:
> + - const: mediatek,mt2712-disp-mutex
> + - items:
> + - const: mediatek,mt8167-disp-mutex
> + - items:
> + - const: mediatek,mt8173-disp-mutex
> + - items:
> + - const: mediatek,mt8183-disp-mutex
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + description: A phandle and PM domain specifier as defined by bindings of
> + the power controller specified by phandle. See
> + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> + clocks:
> + items:
> + - description: MUTEX Clock
> +
> + mediatek,gce-events:
> + description:
> + The event id which is mapping to the specific hardware event signal to gce.
> + The event id is defined in the gce header
> + include/include/dt-bindings/gce/<chip>-gce.h of each chips.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + mutex: mutex@14020000 {
> + compatible = "mediatek,mt8173-disp-mutex";
> + reg = <0 0x14020000 0 0x1000>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> + };
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v9 04/14] dt-bindings: mediatek: add mediatek,dsc.yaml for mt8195 SoC binding
[not found] ` <20210825144833.7757-5-jason-jh.lin@mediatek.com>
@ 2021-09-05 4:11 ` Chun-Kuang Hu
0 siblings, 0 replies; 3+ messages in thread
From: Chun-Kuang Hu @ 2021-09-05 4:11 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
Enric Balletbo i Serra, Frank Wunderlich, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, fshao, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月25日 週三 下午10:48寫道：
>
> 1. Add mediatek,dsc.yaml to describe DSC module in details.
> 2. Add mt8195 SoC binding to mediatek,dsc.yaml.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,dsc.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> new file mode 100644
> index 000000000000..f26e3010d5f4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek display DSC controller
Mediatek
Regards,
Chun-Kuang.
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + The DSC standard is a specification of the algorithms used for
> + compressing and decompressing image display streams, including
> + the specification of the syntax and semantics of the compressed
> + video bit stream. DSC is designed for real-time systems with
> + real-time compression, transmission, decompression and Display.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: mediatek,mt8195-disp-dsc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: DSC Wrapper Clock
> +
> + power-domains:
> + description: A phandle and PM domain specifier as defined by bindings of
> + the power controller specified by phandle. See
> + Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +
> + mediatek,gce-client-reg:
> + description:
> + The register of client driver can be configured by gce with 4 arguments defined
> + in this property, such as phandle of gce, subsys id, register offset and size.
> + Each subsys id is mapping to a base address of display function blocks register
> + which is defined in the gce header include/include/dt-bindings/gce/<chip>-gce.h.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + dsc0: disp_dsc_wrap@1c009000 {
> + compatible = "mediatek,mt8195-disp-dsc";
> + reg = <0 0x1c009000 0 0x1000>;
> + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
> + };
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v9 09/14] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c
[not found] ` <20210825144833.7757-10-jason-jh.lin@mediatek.com>
@ 2021-09-05 4:18 ` Chun-Kuang Hu
0 siblings, 0 replies; 3+ messages in thread
From: Chun-Kuang Hu @ 2021-09-05 4:18 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
Enric Balletbo i Serra, Frank Wunderlich, David Airlie,
Daniel Vetter, Fabien Parent, Hsin-Yi Wang, fshao, Yongqiang Niu,
Jitao shi, Nancy Lin, singo.chang, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年8月25日 週三 下午10:48寫道：
>
> Remove the unsed define in mtk_drm_ddp_comp.c
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> rebase on [1] series
> [1] drm/mediatek: Separate aal module
> - https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 99cbf44463e4..484080a0defa 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -21,8 +21,6 @@
> #include "mtk_drm_crtc.h"
>
> #define DISP_OD_EN 0x0000
> -#define DISP_OD_INTEN 0x0008
> -#define DISP_OD_INTSTA 0x000c
> #define DISP_OD_CFG 0x0020
> #define DISP_OD_SIZE 0x0030
> #define DISP_DITHER_5 0x0114
> @@ -39,26 +37,18 @@
> #define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
>
> -#define LUT_10BIT_MASK 0x03ff
> -
> #define OD_RELAYMODE BIT(0)
>
> #define UFO_BYPASS BIT(2)
>
> #define DISP_DITHERING BIT(2)
> #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
> #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
> #define DITHER_NEW_BIT_MODE BIT(0)
> #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
> -#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
> #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
> -#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
> #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> -#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
> #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> -#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
>
> struct mtk_ddp_comp_dev {
> struct clk *clk;
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <20210825144833.7757-1-jason-jh.lin@mediatek.com>
[not found] ` <20210825144833.7757-4-jason-jh.lin@mediatek.com>
2021-09-03 23:08 ` [PATCH v9 03/14] dt-bindings: mediatek: display: split each block to individual yaml Chun-Kuang Hu
[not found] ` <20210825144833.7757-5-jason-jh.lin@mediatek.com>
2021-09-05 4:11 ` [PATCH v9 04/14] dt-bindings: mediatek: add mediatek,dsc.yaml for mt8195 SoC binding Chun-Kuang Hu
[not found] ` <20210825144833.7757-10-jason-jh.lin@mediatek.com>
2021-09-05 4:18 ` [PATCH v9 09/14] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c Chun-Kuang Hu
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