From: Stephane Eranian <eranian@google.com>
To: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <andi@firstfloor.org>,
Peter Zijlstra <peterz@infradead.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake
Date: Fri, 17 Jul 2015 13:41:04 -0700 [thread overview]
Message-ID: <CABPqkBSotpuiithZ4MQ7N4=Sawsrc5DSH+Den6oBQn1kB_fNDg@mail.gmail.com> (raw)
In-Reply-To: <20150717200900.GE7380@tassilo.jf.intel.com>
Andi,
On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen <ak@linux.intel.com> wrote:
>> I believe this mask of 0x3fff17 is wrong and should instead be
>> 0x7fffff based on the description of the FRONTEND
>> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
>> valid latency values may be rejected.
>
> No, my mask is correct.
>
Ok, so your event mask (0x17) really only allows what's defined
instead the full width of the field.
As for the IDQ_BUBBLE_WIDTH, you only allow 2 bits out of 3, so
maximum bubble threshold is 3
instead of 7. I assume this is because you know that it cannot have
more than 3 simultaneously then.
Would be good to explain this a bit more in the code.
> --
> ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2015-07-17 20:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-29 21:22 [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel Andi Kleen
2015-06-29 21:22 ` [PATCH 2/3] x86, perf: Support custom test values for extra_regs Andi Kleen
2015-06-30 11:19 ` Peter Zijlstra
2015-06-30 15:44 ` Andi Kleen
2015-06-29 21:22 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen
2015-07-17 19:47 ` Stephane Eranian
2015-07-17 20:09 ` Andi Kleen
2015-07-17 20:11 ` Thomas Gleixner
2015-07-17 20:33 ` Andi Kleen
2015-07-17 21:01 ` Stephane Eranian
2015-07-17 21:19 ` Andi Kleen
2015-07-17 22:00 ` Stephane Eranian
2015-07-17 23:31 ` Andi Kleen
2015-07-17 23:52 ` Stephane Eranian
2015-07-18 14:23 ` Andi Kleen
2015-07-17 22:16 ` Thomas Gleixner
2015-07-17 20:41 ` Stephane Eranian [this message]
2015-07-17 20:52 ` Andi Kleen
2015-07-17 21:05 ` Peter Zijlstra
2015-07-17 21:18 ` Andi Kleen
2015-07-17 22:23 ` Thomas Gleixner
2015-08-04 9:00 ` [tip:perf/core] perf/x86: Make merge_attr() global to use from perf_event_intel tip-bot for Andi Kleen
2015-06-30 23:33 Updated Skylake Frontend profiling patchkit Andi Kleen
2015-06-30 23:33 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen
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