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From: Thomas Gleixner <tglx@linutronix.de>
To: Andi Kleen <ak@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>,
	Andi Kleen <andi@firstfloor.org>,
	Peter Zijlstra <peterz@infradead.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake
Date: Sat, 18 Jul 2015 00:16:26 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.11.1507172351010.18576@nanos> (raw)
In-Reply-To: <20150717203315.GI7380@tassilo.jf.intel.com>

On Fri, 17 Jul 2015, Andi Kleen wrote:
> On Fri, Jul 17, 2015 at 10:11:28PM +0200, Thomas Gleixner wrote:
> > On Fri, 17 Jul 2015, Andi Kleen wrote:
> > 
> > > > I believe this mask of 0x3fff17 is wrong and should instead be
> > > > 0x7fffff based on the description of the FRONTEND
> > > > MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
> > > > valid latency values may be rejected.
> > > 
> > > No, my mask is correct.
> > 
> > Provide a proper argument for that. Just claiming 'my mask is correct'
> > definitely falls not into that category.
> 
> Because I actually tested the code unlike you or Stephane.

You know fcking well that I cannot test on skylake and probably
Stephane can't either.
 
> # wrmsr 0x3f7 0x3fff17
> # wrmsr 0x3f7 0x7fffff
> wrmsr: CPU 0 cannot set MSR 0x000003f7 to 0x00000000007fffff
> # 

So you think that's an explanation? No, it is NOT. It's merily an
observation on some particular piece of HW to which you have access
to exclusively.

Nobody asks you to reveal NDA information, but you should at least
have the courtesy to provide an explanation which is understandable to
others. The minimal explanation you could have provided would have been:

  "On my test machine the valid mask is 0x3fff17 contrary to the SDM
   which defines the valid mask as 0x7fffff"

'My mask is correct' is definitely not an explanation at all.

Thanks,

	tglx


  parent reply	other threads:[~2015-07-17 22:16 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-29 21:22 [PATCH 1/3] x86, perf: Make merge_attr global to use from perf_event_intel Andi Kleen
2015-06-29 21:22 ` [PATCH 2/3] x86, perf: Support custom test values for extra_regs Andi Kleen
2015-06-30 11:19   ` Peter Zijlstra
2015-06-30 15:44     ` Andi Kleen
2015-06-29 21:22 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen
2015-07-17 19:47   ` Stephane Eranian
2015-07-17 20:09     ` Andi Kleen
2015-07-17 20:11       ` Thomas Gleixner
2015-07-17 20:33         ` Andi Kleen
2015-07-17 21:01           ` Stephane Eranian
2015-07-17 21:19             ` Andi Kleen
2015-07-17 22:00               ` Stephane Eranian
2015-07-17 23:31                 ` Andi Kleen
2015-07-17 23:52                   ` Stephane Eranian
2015-07-18 14:23                     ` Andi Kleen
2015-07-17 22:16           ` Thomas Gleixner [this message]
2015-07-17 20:41       ` Stephane Eranian
2015-07-17 20:52         ` Andi Kleen
2015-07-17 21:05           ` Peter Zijlstra
2015-07-17 21:18             ` Andi Kleen
2015-07-17 22:23               ` Thomas Gleixner
2015-08-04  9:00 ` [tip:perf/core] perf/x86: Make merge_attr() global to use from perf_event_intel tip-bot for Andi Kleen
2015-06-30 23:33 Updated Skylake Frontend profiling patchkit Andi Kleen
2015-06-30 23:33 ` [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake Andi Kleen

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