* [PATCH v5 0/4] mailbox: imx: bug fix and add support for imx v1 mu @ 2019-08-05 4:52 Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 1/4] mailbox: imx: Fix Tx doorbell shutdown path Richard Zhu ` (3 more replies) 0 siblings, 4 replies; 12+ messages in thread From: Richard Zhu @ 2019-08-05 4:52 UTC (permalink / raw) To: jassisinghbrar, o.rempel, daniel.baluta, aisheng.dong Cc: linux-imx, linux-kernel, linux-arm-kernel, Richard Zhu Change logs: v4 --> v5: - Include Daniel's patch-set into this one. v3 --> v4: - Change "version1.0" to "version 1.0" in the commit log. - Update the devicetree binding document to support the imx7ulp mu. - Rebase the patch refer to the following bug-fixs patch-set issued by Daniel Baluta <daniel.baluta@gmail.com>. "https://patchwork.kernel.org/patch/11069479/" v2 --> v3: - Format the patch-set refer to Oleksij's guidance. - Init the register array by a simple way recommended by Oleksij. - Add Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> tag. v1 --> v2: - Use to have the register layout linked on probe, suggested by Oleksij Rempel <o.rempel@pengutronix.de>. - Add Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> tag. Daniel Baluta (2): mailbox: imx: Fix Tx doorbell shutdown path mailbox: imx: Clear the right interrupts at shutdown Richard Zhu (2): dt-bindings: mailbox: imx-mu: add imx7ulp MU support mailbox: imx: add support for imx v1 mu .../devicetree/bindings/mailbox/fsl,mu.txt | 2 + drivers/mailbox/imx-mailbox.c | 74 ++++++++++++++++------ 2 files changed, 56 insertions(+), 20 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [RESEND PATCH v5 1/4] mailbox: imx: Fix Tx doorbell shutdown path 2019-08-05 4:52 [PATCH v5 0/4] mailbox: imx: bug fix and add support for imx v1 mu Richard Zhu @ 2019-08-05 4:52 ` Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 2/4] mailbox: imx: Clear the right interrupts at shutdown Richard Zhu ` (2 subsequent siblings) 3 siblings, 0 replies; 12+ messages in thread From: Richard Zhu @ 2019-08-05 4:52 UTC (permalink / raw) To: jassisinghbrar, o.rempel, daniel.baluta, aisheng.dong Cc: linux-imx, linux-kernel, linux-arm-kernel, Richard Zhu From: Daniel Baluta <daniel.baluta@nxp.com> Tx doorbell is handled by txdb_tasklet and doesn't have an associated IRQ. Anyhow, imx_mu_shutdown ignores this and tries to free an IRQ that wasn't requested for Tx DB resulting in the following warning: [ 1.967644] Trying to free already-free IRQ 26 [ 1.972108] WARNING: CPU: 2 PID: 157 at kernel/irq/manage.c:1708 __free_irq+0xc0/0x358 [ 1.980024] Modules linked in: [ 1.983088] CPU: 2 PID: 157 Comm: kworker/2:1 Tainted: G [ 1.993524] Hardware name: Freescale i.MX8QXP MEK (DT) [ 1.998668] Workqueue: events deferred_probe_work_func [ 2.003812] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 2.008607] pc : __free_irq+0xc0/0x358 [ 2.012364] lr : __free_irq+0xc0/0x358 [ 2.016111] sp : ffff00001179b7e0 [ 2.019422] x29: ffff00001179b7e0 x28: 0000000000000018 [ 2.024736] x27: ffff000011233000 x26: 0000000000000004 [ 2.030053] x25: 000000000000001a x24: ffff80083bec74d4 [ 2.035369] x23: 0000000000000000 x22: ffff80083bec7588 [ 2.040686] x21: ffff80083b1fe8d8 x20: ffff80083bec7400 [ 2.046003] x19: 0000000000000000 x18: ffffffffffffffff [ 2.051320] x17: 0000000000000000 x16: 0000000000000000 [ 2.056637] x15: ffff0000111296c8 x14: ffff00009179b517 [ 2.061953] x13: ffff00001179b525 x12: ffff000011142000 [ 2.067270] x11: ffff000011129f20 x10: ffff0000105da970 [ 2.072587] x9 : 00000000ffffffd0 x8 : 0000000000000194 [ 2.077903] x7 : 612065657266206f x6 : ffff0000111e7b09 [ 2.083220] x5 : 0000000000000003 x4 : 0000000000000000 [ 2.088537] x3 : 0000000000000000 x2 : 00000000ffffffff [ 2.093854] x1 : 28b70f0a2b60a500 x0 : 0000000000000000 [ 2.099173] Call trace: [ 2.101618] __free_irq+0xc0/0x358 [ 2.105021] free_irq+0x38/0x98 [ 2.108170] imx_mu_shutdown+0x90/0xb0 [ 2.111921] mbox_free_channel.part.2+0x24/0xb8 [ 2.116453] mbox_free_channel+0x18/0x28 This bug is present from the beginning of times. Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- drivers/mailbox/imx-mailbox.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 25be8bb..1eeabc5 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -214,8 +214,10 @@ static void imx_mu_shutdown(struct mbox_chan *chan) struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; - if (cp->type == IMX_MU_TYPE_TXDB) + if (cp->type == IMX_MU_TYPE_TXDB) { tasklet_kill(&cp->txdb_tasklet); + return; + } imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx)); -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RESEND PATCH v5 2/4] mailbox: imx: Clear the right interrupts at shutdown 2019-08-05 4:52 [PATCH v5 0/4] mailbox: imx: bug fix and add support for imx v1 mu Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 1/4] mailbox: imx: Fix Tx doorbell shutdown path Richard Zhu @ 2019-08-05 4:52 ` Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu Richard Zhu 3 siblings, 0 replies; 12+ messages in thread From: Richard Zhu @ 2019-08-05 4:52 UTC (permalink / raw) To: jassisinghbrar, o.rempel, daniel.baluta, aisheng.dong Cc: linux-imx, linux-kernel, linux-arm-kernel, Richard Zhu From: Daniel Baluta <daniel.baluta@nxp.com> Make sure to only clear enabled interrupts keeping count of the connection type. Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- drivers/mailbox/imx-mailbox.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 1eeabc5..afe625e 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -219,8 +219,19 @@ static void imx_mu_shutdown(struct mbox_chan *chan) return; } - imx_mu_xcr_rmw(priv, 0, - IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx)); + switch (cp->type) { + case IMX_MU_TYPE_TX: + imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); + break; + case IMX_MU_TYPE_RX: + imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx)); + break; + case IMX_MU_TYPE_RXDB: + imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx)); + break; + default: + break; + } free_irq(priv->irq, chan); } -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support 2019-08-05 4:52 [PATCH v5 0/4] mailbox: imx: bug fix and add support for imx v1 mu Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 1/4] mailbox: imx: Fix Tx doorbell shutdown path Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 2/4] mailbox: imx: Clear the right interrupts at shutdown Richard Zhu @ 2019-08-05 4:52 ` Richard Zhu 2019-08-05 19:20 ` Daniel Baluta 2019-08-05 4:52 ` [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu Richard Zhu 3 siblings, 1 reply; 12+ messages in thread From: Richard Zhu @ 2019-08-05 4:52 UTC (permalink / raw) To: jassisinghbrar, o.rempel, daniel.baluta, aisheng.dong Cc: linux-imx, linux-kernel, linux-arm-kernel, Richard Zhu There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" compatible to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index f3cf77e..9c43357 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -21,6 +21,8 @@ Required properties: imx6sx, imx7s, imx8qxp, imx8qm. The "fsl,imx6sx-mu" compatible is seen as generic and should be included together with SoC specific compatible. + There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" + compatible to support it. - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support 2019-08-05 4:52 ` [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support Richard Zhu @ 2019-08-05 19:20 ` Daniel Baluta 0 siblings, 0 replies; 12+ messages in thread From: Daniel Baluta @ 2019-08-05 19:20 UTC (permalink / raw) To: Richard Zhu Cc: jassisinghbrar, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel, Rob Herring, Devicetree List + Rob On Mon, Aug 5, 2019 at 8:18 AM Richard Zhu <hongxing.zhu@nxp.com> wrote: > > There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" compatible > to support it. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> > --- > Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt > index f3cf77e..9c43357 100644 > --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt > +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt > @@ -21,6 +21,8 @@ Required properties: > imx6sx, imx7s, imx8qxp, imx8qm. > The "fsl,imx6sx-mu" compatible is seen as generic and should > be included together with SoC specific compatible. > + There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" > + compatible to support it. > - reg : Should contain the registers location and length > - interrupts : Interrupt number. The interrupt specifier format depends > on the interrupt controller parent. > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu 2019-08-05 4:52 [PATCH v5 0/4] mailbox: imx: bug fix and add support for imx v1 mu Richard Zhu ` (2 preceding siblings ...) 2019-08-05 4:52 ` [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support Richard Zhu @ 2019-08-05 4:52 ` Richard Zhu 2019-08-05 19:21 ` Daniel Baluta [not found] ` <CAEnQRZDk4TjU0nWgGXEV06ZygvSyuPHc61_uT7KRu0j2Aaxj7w@mail.gmail.com> 3 siblings, 2 replies; 12+ messages in thread From: Richard Zhu @ 2019-08-05 4:52 UTC (permalink / raw) To: jassisinghbrar, o.rempel, daniel.baluta, aisheng.dong Cc: linux-imx, linux-kernel, linux-arm-kernel, Richard Zhu There is a version 1.0 MU on i.MX7ULP platform. One new version ID register is added, and it's offset is 0. TRn registers are defined at the offset 0x20 ~ 0x2C. RRn registers are defined at the offset 0x40 ~ 0x4C. SR/CR registers are defined at 0x60/0x64. Extend this driver to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> --- drivers/mailbox/imx-mailbox.c | 55 ++++++++++++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index afe625e..2cdcdc5 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -12,19 +12,11 @@ #include <linux/of_device.h> #include <linux/slab.h> -/* Transmit Register */ -#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) -/* Receive Register */ -#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) -/* Status Register */ -#define IMX_MU_xSR 0x20 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) #define IMX_MU_xSR_BRDIP BIT(9) -/* Control Register */ -#define IMX_MU_xCR 0x24 /* General Purpose Interrupt Enable */ #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) /* Receive Interrupt Enable */ @@ -44,6 +36,13 @@ enum imx_mu_chan_type { IMX_MU_TYPE_RXDB, /* Rx doorbell */ }; +struct imx_mu_dcfg { + u32 xTR[4]; /* Transmit Registers */ + u32 xRR[4]; /* Receive Registers */ + u32 xSR; /* Status Register */ + u32 xCR; /* Control Register */ +}; + struct imx_mu_con_priv { unsigned int idx; char irq_desc[IMX_MU_CHAN_NAME_SIZE]; @@ -61,12 +60,27 @@ struct imx_mu_priv { struct mbox_chan mbox_chans[IMX_MU_CHANS]; struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; + const struct imx_mu_dcfg *dcfg; struct clk *clk; int irq; bool side_b; }; +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { + .xTR = {0x0, 0x4, 0x8, 0xc}, + .xRR = {0x10, 0x14, 0x18, 0x1c}, + .xSR = 0x20, + .xCR = 0x24, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { + .xTR = {0x20, 0x24, 0x28, 0x2c}, + .xRR = {0x40, 0x44, 0x48, 0x4c}, + .xSR = 0x60, + .xCR = 0x64, +}; + static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) { return container_of(mbox, struct imx_mu_priv, mbox); @@ -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) u32 val; spin_lock_irqsave(&priv->xcr_lock, flags); - val = imx_mu_read(priv, IMX_MU_xCR); + val = imx_mu_read(priv, priv->dcfg->xCR); val &= ~clr; val |= set; - imx_mu_write(priv, val, IMX_MU_xCR); + imx_mu_write(priv, val, priv->dcfg->xCR); spin_unlock_irqrestore(&priv->xcr_lock, flags); return val; @@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) struct imx_mu_con_priv *cp = chan->con_priv; u32 val, ctrl, dat; - ctrl = imx_mu_read(priv, IMX_MU_xCR); - val = imx_mu_read(priv, IMX_MU_xSR); + ctrl = imx_mu_read(priv, priv->dcfg->xCR); + val = imx_mu_read(priv, priv->dcfg->xSR); switch (cp->type) { case IMX_MU_TYPE_TX: @@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p) imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); mbox_chan_txdone(chan, 0); } else if (val == IMX_MU_xSR_RFn(cp->idx)) { - dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); + dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); mbox_chan_received_data(chan, (void *)&dat); } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { - imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR); + imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); mbox_chan_received_data(chan, NULL); } else { dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); @@ -159,7 +173,7 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data) switch (cp->type) { case IMX_MU_TYPE_TX: - imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); + imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); break; case IMX_MU_TYPE_TXDB: @@ -270,7 +284,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) return; /* Set default MU configuration */ - imx_mu_write(priv, 0, IMX_MU_xCR); + imx_mu_write(priv, 0, priv->dcfg->xCR); } static int imx_mu_probe(struct platform_device *pdev) @@ -278,6 +292,7 @@ static int imx_mu_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct imx_mu_priv *priv; + const struct imx_mu_dcfg *dcfg; unsigned int i; int ret; @@ -295,6 +310,11 @@ static int imx_mu_probe(struct platform_device *pdev) if (priv->irq < 0) return priv->irq; + dcfg = of_device_get_match_data(dev); + if (!dcfg) + return -EINVAL; + priv->dcfg = dcfg; + priv->clk = devm_clk_get(dev, NULL); if (IS_ERR(priv->clk)) { if (PTR_ERR(priv->clk) != -ENOENT) @@ -348,7 +368,8 @@ static int imx_mu_remove(struct platform_device *pdev) } static const struct of_device_id imx_mu_dt_ids[] = { - { .compatible = "fsl,imx6sx-mu" }, + { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, + { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, { }, }; MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); -- 2.7.4 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu 2019-08-05 4:52 ` [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu Richard Zhu @ 2019-08-05 19:21 ` Daniel Baluta 2019-10-08 7:25 ` Daniel Baluta [not found] ` <CAEnQRZDk4TjU0nWgGXEV06ZygvSyuPHc61_uT7KRu0j2Aaxj7w@mail.gmail.com> 1 sibling, 1 reply; 12+ messages in thread From: Daniel Baluta @ 2019-08-05 19:21 UTC (permalink / raw) To: Richard Zhu Cc: jassisinghbrar, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu <hongxing.zhu@nxp.com> wrote: > > There is a version 1.0 MU on i.MX7ULP platform. > One new version ID register is added, and it's offset is 0. > TRn registers are defined at the offset 0x20 ~ 0x2C. > RRn registers are defined at the offset 0x40 ~ 0x4C. > SR/CR registers are defined at 0x60/0x64. > Extend this driver to support it. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Very clean solution. Thanks Richard! Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> > --- > drivers/mailbox/imx-mailbox.c | 55 ++++++++++++++++++++++++++++++------------- > 1 file changed, 38 insertions(+), 17 deletions(-) > > diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c > index afe625e..2cdcdc5 100644 > --- a/drivers/mailbox/imx-mailbox.c > +++ b/drivers/mailbox/imx-mailbox.c > @@ -12,19 +12,11 @@ > #include <linux/of_device.h> > #include <linux/slab.h> > > -/* Transmit Register */ > -#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) > -/* Receive Register */ > -#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) > -/* Status Register */ > -#define IMX_MU_xSR 0x20 > #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) > #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) > #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) > #define IMX_MU_xSR_BRDIP BIT(9) > > -/* Control Register */ > -#define IMX_MU_xCR 0x24 > /* General Purpose Interrupt Enable */ > #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) > /* Receive Interrupt Enable */ > @@ -44,6 +36,13 @@ enum imx_mu_chan_type { > IMX_MU_TYPE_RXDB, /* Rx doorbell */ > }; > > +struct imx_mu_dcfg { > + u32 xTR[4]; /* Transmit Registers */ > + u32 xRR[4]; /* Receive Registers */ > + u32 xSR; /* Status Register */ > + u32 xCR; /* Control Register */ > +}; > + > struct imx_mu_con_priv { > unsigned int idx; > char irq_desc[IMX_MU_CHAN_NAME_SIZE]; > @@ -61,12 +60,27 @@ struct imx_mu_priv { > struct mbox_chan mbox_chans[IMX_MU_CHANS]; > > struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; > + const struct imx_mu_dcfg *dcfg; > struct clk *clk; > int irq; > > bool side_b; > }; > > +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { > + .xTR = {0x0, 0x4, 0x8, 0xc}, > + .xRR = {0x10, 0x14, 0x18, 0x1c}, > + .xSR = 0x20, > + .xCR = 0x24, > +}; > + > +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { > + .xTR = {0x20, 0x24, 0x28, 0x2c}, > + .xRR = {0x40, 0x44, 0x48, 0x4c}, > + .xSR = 0x60, > + .xCR = 0x64, > +}; > + > static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) > { > return container_of(mbox, struct imx_mu_priv, mbox); > @@ -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) > u32 val; > > spin_lock_irqsave(&priv->xcr_lock, flags); > - val = imx_mu_read(priv, IMX_MU_xCR); > + val = imx_mu_read(priv, priv->dcfg->xCR); > val &= ~clr; > val |= set; > - imx_mu_write(priv, val, IMX_MU_xCR); > + imx_mu_write(priv, val, priv->dcfg->xCR); > spin_unlock_irqrestore(&priv->xcr_lock, flags); > > return val; > @@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > struct imx_mu_con_priv *cp = chan->con_priv; > u32 val, ctrl, dat; > > - ctrl = imx_mu_read(priv, IMX_MU_xCR); > - val = imx_mu_read(priv, IMX_MU_xSR); > + ctrl = imx_mu_read(priv, priv->dcfg->xCR); > + val = imx_mu_read(priv, priv->dcfg->xSR); > > switch (cp->type) { > case IMX_MU_TYPE_TX: > @@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); > mbox_chan_txdone(chan, 0); > } else if (val == IMX_MU_xSR_RFn(cp->idx)) { > - dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); > + dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); > mbox_chan_received_data(chan, (void *)&dat); > } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { > - imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR); > + imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); > mbox_chan_received_data(chan, NULL); > } else { > dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); > @@ -159,7 +173,7 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data) > > switch (cp->type) { > case IMX_MU_TYPE_TX: > - imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); > + imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); > imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); > break; > case IMX_MU_TYPE_TXDB: > @@ -270,7 +284,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) > return; > > /* Set default MU configuration */ > - imx_mu_write(priv, 0, IMX_MU_xCR); > + imx_mu_write(priv, 0, priv->dcfg->xCR); > } > > static int imx_mu_probe(struct platform_device *pdev) > @@ -278,6 +292,7 @@ static int imx_mu_probe(struct platform_device *pdev) > struct device *dev = &pdev->dev; > struct device_node *np = dev->of_node; > struct imx_mu_priv *priv; > + const struct imx_mu_dcfg *dcfg; > unsigned int i; > int ret; > > @@ -295,6 +310,11 @@ static int imx_mu_probe(struct platform_device *pdev) > if (priv->irq < 0) > return priv->irq; > > + dcfg = of_device_get_match_data(dev); > + if (!dcfg) > + return -EINVAL; > + priv->dcfg = dcfg; > + > priv->clk = devm_clk_get(dev, NULL); > if (IS_ERR(priv->clk)) { > if (PTR_ERR(priv->clk) != -ENOENT) > @@ -348,7 +368,8 @@ static int imx_mu_remove(struct platform_device *pdev) > } > > static const struct of_device_id imx_mu_dt_ids[] = { > - { .compatible = "fsl,imx6sx-mu" }, > + { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, > + { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, > { }, > }; > MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu 2019-08-05 19:21 ` Daniel Baluta @ 2019-10-08 7:25 ` Daniel Baluta 2019-10-09 1:47 ` [EXT] " Richard Zhu 0 siblings, 1 reply; 12+ messages in thread From: Daniel Baluta @ 2019-10-08 7:25 UTC (permalink / raw) To: Richard Zhu Cc: jassisinghbrar, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel Hi Richard, Can you please rebase and resend this patch series? On Mon, Aug 5, 2019 at 10:21 PM Daniel Baluta <daniel.baluta@gmail.com> wrote: > > On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu <hongxing.zhu@nxp.com> wrote: > > > > There is a version 1.0 MU on i.MX7ULP platform. > > One new version ID register is added, and it's offset is 0. > > TRn registers are defined at the offset 0x20 ~ 0x2C. > > RRn registers are defined at the offset 0x40 ~ 0x4C. > > SR/CR registers are defined at 0x60/0x64. > > Extend this driver to support it. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> > > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > > Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> > > Very clean solution. Thanks Richard! > > Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> > > > --- > > drivers/mailbox/imx-mailbox.c | 55 ++++++++++++++++++++++++++++++------------- > > 1 file changed, 38 insertions(+), 17 deletions(-) > > > > diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c > > index afe625e..2cdcdc5 100644 > > --- a/drivers/mailbox/imx-mailbox.c > > +++ b/drivers/mailbox/imx-mailbox.c > > @@ -12,19 +12,11 @@ > > #include <linux/of_device.h> > > #include <linux/slab.h> > > > > -/* Transmit Register */ > > -#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) > > -/* Receive Register */ > > -#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) > > -/* Status Register */ > > -#define IMX_MU_xSR 0x20 > > #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) > > #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) > > #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) > > #define IMX_MU_xSR_BRDIP BIT(9) > > > > -/* Control Register */ > > -#define IMX_MU_xCR 0x24 > > /* General Purpose Interrupt Enable */ > > #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) > > /* Receive Interrupt Enable */ > > @@ -44,6 +36,13 @@ enum imx_mu_chan_type { > > IMX_MU_TYPE_RXDB, /* Rx doorbell */ > > }; > > > > +struct imx_mu_dcfg { > > + u32 xTR[4]; /* Transmit Registers */ > > + u32 xRR[4]; /* Receive Registers */ > > + u32 xSR; /* Status Register */ > > + u32 xCR; /* Control Register */ > > +}; > > + > > struct imx_mu_con_priv { > > unsigned int idx; > > char irq_desc[IMX_MU_CHAN_NAME_SIZE]; > > @@ -61,12 +60,27 @@ struct imx_mu_priv { > > struct mbox_chan mbox_chans[IMX_MU_CHANS]; > > > > struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; > > + const struct imx_mu_dcfg *dcfg; > > struct clk *clk; > > int irq; > > > > bool side_b; > > }; > > > > +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { > > + .xTR = {0x0, 0x4, 0x8, 0xc}, > > + .xRR = {0x10, 0x14, 0x18, 0x1c}, > > + .xSR = 0x20, > > + .xCR = 0x24, > > +}; > > + > > +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { > > + .xTR = {0x20, 0x24, 0x28, 0x2c}, > > + .xRR = {0x40, 0x44, 0x48, 0x4c}, > > + .xSR = 0x60, > > + .xCR = 0x64, > > +}; > > + > > static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) > > { > > return container_of(mbox, struct imx_mu_priv, mbox); > > @@ -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr) > > u32 val; > > > > spin_lock_irqsave(&priv->xcr_lock, flags); > > - val = imx_mu_read(priv, IMX_MU_xCR); > > + val = imx_mu_read(priv, priv->dcfg->xCR); > > val &= ~clr; > > val |= set; > > - imx_mu_write(priv, val, IMX_MU_xCR); > > + imx_mu_write(priv, val, priv->dcfg->xCR); > > spin_unlock_irqrestore(&priv->xcr_lock, flags); > > > > return val; > > @@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > > struct imx_mu_con_priv *cp = chan->con_priv; > > u32 val, ctrl, dat; > > > > - ctrl = imx_mu_read(priv, IMX_MU_xCR); > > - val = imx_mu_read(priv, IMX_MU_xSR); > > + ctrl = imx_mu_read(priv, priv->dcfg->xCR); > > + val = imx_mu_read(priv, priv->dcfg->xSR); > > > > switch (cp->type) { > > case IMX_MU_TYPE_TX: > > @@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > > imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); > > mbox_chan_txdone(chan, 0); > > } else if (val == IMX_MU_xSR_RFn(cp->idx)) { > > - dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); > > + dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); > > mbox_chan_received_data(chan, (void *)&dat); > > } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { > > - imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR); > > + imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); > > mbox_chan_received_data(chan, NULL); > > } else { > > dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); > > @@ -159,7 +173,7 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data) > > > > switch (cp->type) { > > case IMX_MU_TYPE_TX: > > - imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); > > + imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); > > imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); > > break; > > case IMX_MU_TYPE_TXDB: > > @@ -270,7 +284,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) > > return; > > > > /* Set default MU configuration */ > > - imx_mu_write(priv, 0, IMX_MU_xCR); > > + imx_mu_write(priv, 0, priv->dcfg->xCR); > > } > > > > static int imx_mu_probe(struct platform_device *pdev) > > @@ -278,6 +292,7 @@ static int imx_mu_probe(struct platform_device *pdev) > > struct device *dev = &pdev->dev; > > struct device_node *np = dev->of_node; > > struct imx_mu_priv *priv; > > + const struct imx_mu_dcfg *dcfg; > > unsigned int i; > > int ret; > > > > @@ -295,6 +310,11 @@ static int imx_mu_probe(struct platform_device *pdev) > > if (priv->irq < 0) > > return priv->irq; > > > > + dcfg = of_device_get_match_data(dev); > > + if (!dcfg) > > + return -EINVAL; > > + priv->dcfg = dcfg; > > + > > priv->clk = devm_clk_get(dev, NULL); > > if (IS_ERR(priv->clk)) { > > if (PTR_ERR(priv->clk) != -ENOENT) > > @@ -348,7 +368,8 @@ static int imx_mu_remove(struct platform_device *pdev) > > } > > > > static const struct of_device_id imx_mu_dt_ids[] = { > > - { .compatible = "fsl,imx6sx-mu" }, > > + { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, > > + { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, > > { }, > > }; > > MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu 2019-10-08 7:25 ` Daniel Baluta @ 2019-10-09 1:47 ` Richard Zhu 2019-10-12 1:12 ` Richard Zhu 0 siblings, 1 reply; 12+ messages in thread From: Richard Zhu @ 2019-10-09 1:47 UTC (permalink / raw) To: Daniel Baluta Cc: jassisinghbrar, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel Hi Daniel: > -----Original Message----- > From: Daniel Baluta <daniel.baluta@gmail.com> > Sent: 2019年10月8日 15:26 > To: Richard Zhu <hongxing.zhu@nxp.com> > Cc: jassisinghbrar@gmail.com; Oleksij Rempel <o.rempel@pengutronix.de>; > Daniel Baluta <daniel.baluta@nxp.com>; Aisheng Dong > <aisheng.dong@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; Linux Kernel > Mailing List <linux-kernel@vger.kernel.org>; linux-arm-kernel > <linux-arm-kernel@lists.infradead.org> > Subject: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 > mu > > > Hi Richard, > > Can you please rebase and resend this patch series? > [Richard Zhu] No problem, I would resend this patch-set later. Best Regards Richard Zhu > On Mon, Aug 5, 2019 at 10:21 PM Daniel Baluta <daniel.baluta@gmail.com> > wrote: > > > > On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu <hongxing.zhu@nxp.com> > wrote: > > > > > > There is a version 1.0 MU on i.MX7ULP platform. > > > One new version ID register is added, and it's offset is 0. > > > TRn registers are defined at the offset 0x20 ~ 0x2C. > > > RRn registers are defined at the offset 0x40 ~ 0x4C. > > > SR/CR registers are defined at 0x60/0x64. > > > Extend this driver to support it. > > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > > Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> > > > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > > > Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> > > > > Very clean solution. Thanks Richard! > > > > Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> > > > > > --- > > > drivers/mailbox/imx-mailbox.c | 55 > > > ++++++++++++++++++++++++++++++------------- > > > 1 file changed, 38 insertions(+), 17 deletions(-) > > > > > > diff --git a/drivers/mailbox/imx-mailbox.c > > > b/drivers/mailbox/imx-mailbox.c index afe625e..2cdcdc5 100644 > > > --- a/drivers/mailbox/imx-mailbox.c > > > +++ b/drivers/mailbox/imx-mailbox.c > > > @@ -12,19 +12,11 @@ > > > #include <linux/of_device.h> > > > #include <linux/slab.h> > > > > > > -/* Transmit Register */ > > > -#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) > > > -/* Receive Register */ > > > -#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) > > > -/* Status Register */ > > > -#define IMX_MU_xSR 0x20 > > > #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) > > > #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) > > > #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) > > > #define IMX_MU_xSR_BRDIP BIT(9) > > > > > > -/* Control Register */ > > > -#define IMX_MU_xCR 0x24 > > > /* General Purpose Interrupt Enable */ > > > #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) > > > /* Receive Interrupt Enable */ > > > @@ -44,6 +36,13 @@ enum imx_mu_chan_type { > > > IMX_MU_TYPE_RXDB, /* Rx doorbell */ > > > }; > > > > > > +struct imx_mu_dcfg { > > > + u32 xTR[4]; /* Transmit Registers */ > > > + u32 xRR[4]; /* Receive Registers */ > > > + u32 xSR; /* Status Register */ > > > + u32 xCR; /* Control Register */ > > > +}; > > > + > > > struct imx_mu_con_priv { > > > unsigned int idx; > > > char > irq_desc[IMX_MU_CHAN_NAME_SIZE]; > > > @@ -61,12 +60,27 @@ struct imx_mu_priv { > > > struct mbox_chan mbox_chans[IMX_MU_CHANS]; > > > > > > struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; > > > + const struct imx_mu_dcfg *dcfg; > > > struct clk *clk; > > > int irq; > > > > > > bool side_b; > > > }; > > > > > > +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { > > > + .xTR = {0x0, 0x4, 0x8, 0xc}, > > > + .xRR = {0x10, 0x14, 0x18, 0x1c}, > > > + .xSR = 0x20, > > > + .xCR = 0x24, > > > +}; > > > + > > > +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { > > > + .xTR = {0x20, 0x24, 0x28, 0x2c}, > > > + .xRR = {0x40, 0x44, 0x48, 0x4c}, > > > + .xSR = 0x60, > > > + .xCR = 0x64, > > > +}; > > > + > > > static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller > > > *mbox) { > > > return container_of(mbox, struct imx_mu_priv, mbox); @@ > > > -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, > u32 set, u32 clr) > > > u32 val; > > > > > > spin_lock_irqsave(&priv->xcr_lock, flags); > > > - val = imx_mu_read(priv, IMX_MU_xCR); > > > + val = imx_mu_read(priv, priv->dcfg->xCR); > > > val &= ~clr; > > > val |= set; > > > - imx_mu_write(priv, val, IMX_MU_xCR); > > > + imx_mu_write(priv, val, priv->dcfg->xCR); > > > spin_unlock_irqrestore(&priv->xcr_lock, flags); > > > > > > return val; > > > @@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > > > struct imx_mu_con_priv *cp = chan->con_priv; > > > u32 val, ctrl, dat; > > > > > > - ctrl = imx_mu_read(priv, IMX_MU_xCR); > > > - val = imx_mu_read(priv, IMX_MU_xSR); > > > + ctrl = imx_mu_read(priv, priv->dcfg->xCR); > > > + val = imx_mu_read(priv, priv->dcfg->xSR); > > > > > > switch (cp->type) { > > > case IMX_MU_TYPE_TX: > > > @@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > > > imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); > > > mbox_chan_txdone(chan, 0); > > > } else if (val == IMX_MU_xSR_RFn(cp->idx)) { > > > - dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); > > > + dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); > > > mbox_chan_received_data(chan, (void *)&dat); > > > } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { > > > - imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), > IMX_MU_xSR); > > > + imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), > > > + priv->dcfg->xSR); > > > mbox_chan_received_data(chan, NULL); > > > } else { > > > dev_warn_ratelimited(priv->dev, "Not handled > > > interrupt\n"); @@ -159,7 +173,7 @@ static int > > > imx_mu_send_data(struct mbox_chan *chan, void *data) > > > > > > switch (cp->type) { > > > case IMX_MU_TYPE_TX: > > > - imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); > > > + imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); > > > imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); > > > break; > > > case IMX_MU_TYPE_TXDB: > > > @@ -270,7 +284,7 @@ static void imx_mu_init_generic(struct imx_mu_priv > *priv) > > > return; > > > > > > /* Set default MU configuration */ > > > - imx_mu_write(priv, 0, IMX_MU_xCR); > > > + imx_mu_write(priv, 0, priv->dcfg->xCR); > > > } > > > > > > static int imx_mu_probe(struct platform_device *pdev) @@ -278,6 > > > +292,7 @@ static int imx_mu_probe(struct platform_device *pdev) > > > struct device *dev = &pdev->dev; > > > struct device_node *np = dev->of_node; > > > struct imx_mu_priv *priv; > > > + const struct imx_mu_dcfg *dcfg; > > > unsigned int i; > > > int ret; > > > > > > @@ -295,6 +310,11 @@ static int imx_mu_probe(struct platform_device > *pdev) > > > if (priv->irq < 0) > > > return priv->irq; > > > > > > + dcfg = of_device_get_match_data(dev); > > > + if (!dcfg) > > > + return -EINVAL; > > > + priv->dcfg = dcfg; > > > + > > > priv->clk = devm_clk_get(dev, NULL); > > > if (IS_ERR(priv->clk)) { > > > if (PTR_ERR(priv->clk) != -ENOENT) @@ -348,7 +368,8 > > > @@ static int imx_mu_remove(struct platform_device *pdev) } > > > > > > static const struct of_device_id imx_mu_dt_ids[] = { > > > - { .compatible = "fsl,imx6sx-mu" }, > > > + { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp }, > > > + { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx > > > + }, > > > { }, > > > }; > > > MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); > > > -- > > > 2.7.4 > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu 2019-10-09 1:47 ` [EXT] " Richard Zhu @ 2019-10-12 1:12 ` Richard Zhu 2019-10-12 7:24 ` Daniel Baluta 0 siblings, 1 reply; 12+ messages in thread From: Richard Zhu @ 2019-10-12 1:12 UTC (permalink / raw) To: Daniel Baluta Cc: jassisinghbrar, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel Hi Daniel: New version patch-set had been sent out on Oct9. https://patchwork.kernel.org/cover/11180683/ Best Regards Richard Zhu > -----Original Message----- > From: Richard Zhu > Sent: 2019年10月9日 9:48 > To: Daniel Baluta <daniel.baluta@gmail.com> > Cc: jassisinghbrar@gmail.com; Oleksij Rempel <o.rempel@pengutronix.de>; > Daniel Baluta <daniel.baluta@nxp.com>; Aisheng Dong > <aisheng.dong@nxp.com>; dl-linux-imx <linux-imx@nxp.com>; Linux Kernel > Mailing List <linux-kernel@vger.kernel.org>; linux-arm-kernel > <linux-arm-kernel@lists.infradead.org> > Subject: RE: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for > imx v1 mu > > Hi Daniel: > > > > -----Original Message----- > > From: Daniel Baluta <daniel.baluta@gmail.com> > > Sent: 2019年10月8日 15:26 > > To: Richard Zhu <hongxing.zhu@nxp.com> > > Cc: jassisinghbrar@gmail.com; Oleksij Rempel > > <o.rempel@pengutronix.de>; Daniel Baluta <daniel.baluta@nxp.com>; > > Aisheng Dong <aisheng.dong@nxp.com>; dl-linux-imx > <linux-imx@nxp.com>; > > Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; > > linux-arm-kernel <linux-arm-kernel@lists.infradead.org> > > Subject: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for > > imx v1 mu > > > > > > Hi Richard, > > > > Can you please rebase and resend this patch series? > > > [Richard Zhu] No problem, I would resend this patch-set later. > > > Best Regards > Richard Zhu > > > On Mon, Aug 5, 2019 at 10:21 PM Daniel Baluta > > <daniel.baluta@gmail.com> > > wrote: > > > > > > On Mon, Aug 5, 2019 at 8:16 AM Richard Zhu <hongxing.zhu@nxp.com> > > wrote: > > > > > > > > There is a version 1.0 MU on i.MX7ULP platform. > > > > One new version ID register is added, and it's offset is 0. > > > > TRn registers are defined at the offset 0x20 ~ 0x2C. > > > > RRn registers are defined at the offset 0x40 ~ 0x4C. > > > > SR/CR registers are defined at 0x60/0x64. > > > > Extend this driver to support it. > > > > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > > > Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> > > > > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > > > > Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> > > > > > > Very clean solution. Thanks Richard! > > > > > > Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> > > > > > > > --- > > > > drivers/mailbox/imx-mailbox.c | 55 > > > > ++++++++++++++++++++++++++++++------------- > > > > 1 file changed, 38 insertions(+), 17 deletions(-) > > > > > > > > diff --git a/drivers/mailbox/imx-mailbox.c > > > > b/drivers/mailbox/imx-mailbox.c index afe625e..2cdcdc5 100644 > > > > --- a/drivers/mailbox/imx-mailbox.c > > > > +++ b/drivers/mailbox/imx-mailbox.c > > > > @@ -12,19 +12,11 @@ > > > > #include <linux/of_device.h> > > > > #include <linux/slab.h> > > > > > > > > -/* Transmit Register */ > > > > -#define IMX_MU_xTRn(x) (0x00 + 4 * (x)) > > > > -/* Receive Register */ > > > > -#define IMX_MU_xRRn(x) (0x10 + 4 * (x)) > > > > -/* Status Register */ > > > > -#define IMX_MU_xSR 0x20 > > > > #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x))) > > > > #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x))) > > > > #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x))) > > > > #define IMX_MU_xSR_BRDIP BIT(9) > > > > > > > > -/* Control Register */ > > > > -#define IMX_MU_xCR 0x24 > > > > /* General Purpose Interrupt Enable */ > > > > #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x))) > > > > /* Receive Interrupt Enable */ > > > > @@ -44,6 +36,13 @@ enum imx_mu_chan_type { > > > > IMX_MU_TYPE_RXDB, /* Rx doorbell */ > > > > }; > > > > > > > > +struct imx_mu_dcfg { > > > > + u32 xTR[4]; /* Transmit Registers */ > > > > + u32 xRR[4]; /* Receive Registers */ > > > > + u32 xSR; /* Status Register */ > > > > + u32 xCR; /* Control Register */ > > > > +}; > > > > + > > > > struct imx_mu_con_priv { > > > > unsigned int idx; > > > > char > > irq_desc[IMX_MU_CHAN_NAME_SIZE]; > > > > @@ -61,12 +60,27 @@ struct imx_mu_priv { > > > > struct mbox_chan mbox_chans[IMX_MU_CHANS]; > > > > > > > > struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; > > > > + const struct imx_mu_dcfg *dcfg; > > > > struct clk *clk; > > > > int irq; > > > > > > > > bool side_b; > > > > }; > > > > > > > > +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { > > > > + .xTR = {0x0, 0x4, 0x8, 0xc}, > > > > + .xRR = {0x10, 0x14, 0x18, 0x1c}, > > > > + .xSR = 0x20, > > > > + .xCR = 0x24, > > > > +}; > > > > + > > > > +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { > > > > + .xTR = {0x20, 0x24, 0x28, 0x2c}, > > > > + .xRR = {0x40, 0x44, 0x48, 0x4c}, > > > > + .xSR = 0x60, > > > > + .xCR = 0x64, > > > > +}; > > > > + > > > > static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller > > > > *mbox) { > > > > return container_of(mbox, struct imx_mu_priv, mbox); @@ > > > > -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv > > > > *priv, > > u32 set, u32 clr) > > > > u32 val; > > > > > > > > spin_lock_irqsave(&priv->xcr_lock, flags); > > > > - val = imx_mu_read(priv, IMX_MU_xCR); > > > > + val = imx_mu_read(priv, priv->dcfg->xCR); > > > > val &= ~clr; > > > > val |= set; > > > > - imx_mu_write(priv, val, IMX_MU_xCR); > > > > + imx_mu_write(priv, val, priv->dcfg->xCR); > > > > spin_unlock_irqrestore(&priv->xcr_lock, flags); > > > > > > > > return val; > > > > @@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > > > > struct imx_mu_con_priv *cp = chan->con_priv; > > > > u32 val, ctrl, dat; > > > > > > > > - ctrl = imx_mu_read(priv, IMX_MU_xCR); > > > > - val = imx_mu_read(priv, IMX_MU_xSR); > > > > + ctrl = imx_mu_read(priv, priv->dcfg->xCR); > > > > + val = imx_mu_read(priv, priv->dcfg->xSR); > > > > > > > > switch (cp->type) { > > > > case IMX_MU_TYPE_TX: > > > > @@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p) > > > > imx_mu_xcr_rmw(priv, 0, > IMX_MU_xCR_TIEn(cp->idx)); > > > > mbox_chan_txdone(chan, 0); > > > > } else if (val == IMX_MU_xSR_RFn(cp->idx)) { > > > > - dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); > > > > + dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); > > > > mbox_chan_received_data(chan, (void *)&dat); > > > > } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { > > > > - imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), > > IMX_MU_xSR); > > > > + imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), > > > > + priv->dcfg->xSR); > > > > mbox_chan_received_data(chan, NULL); > > > > } else { > > > > dev_warn_ratelimited(priv->dev, "Not handled > > > > interrupt\n"); @@ -159,7 +173,7 @@ static int > > > > imx_mu_send_data(struct mbox_chan *chan, void *data) > > > > > > > > switch (cp->type) { > > > > case IMX_MU_TYPE_TX: > > > > - imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); > > > > + imx_mu_write(priv, *arg, > > > > + priv->dcfg->xTR[cp->idx]); > > > > imx_mu_xcr_rmw(priv, > IMX_MU_xCR_TIEn(cp->idx), 0); > > > > break; > > > > case IMX_MU_TYPE_TXDB: > > > > @@ -270,7 +284,7 @@ static void imx_mu_init_generic(struct > > > > imx_mu_priv > > *priv) > > > > return; > > > > > > > > /* Set default MU configuration */ > > > > - imx_mu_write(priv, 0, IMX_MU_xCR); > > > > + imx_mu_write(priv, 0, priv->dcfg->xCR); > > > > } > > > > > > > > static int imx_mu_probe(struct platform_device *pdev) @@ -278,6 > > > > +292,7 @@ static int imx_mu_probe(struct platform_device *pdev) > > > > struct device *dev = &pdev->dev; > > > > struct device_node *np = dev->of_node; > > > > struct imx_mu_priv *priv; > > > > + const struct imx_mu_dcfg *dcfg; > > > > unsigned int i; > > > > int ret; > > > > > > > > @@ -295,6 +310,11 @@ static int imx_mu_probe(struct > > > > platform_device > > *pdev) > > > > if (priv->irq < 0) > > > > return priv->irq; > > > > > > > > + dcfg = of_device_get_match_data(dev); > > > > + if (!dcfg) > > > > + return -EINVAL; > > > > + priv->dcfg = dcfg; > > > > + > > > > priv->clk = devm_clk_get(dev, NULL); > > > > if (IS_ERR(priv->clk)) { > > > > if (PTR_ERR(priv->clk) != -ENOENT) @@ -348,7 > > > > +368,8 @@ static int imx_mu_remove(struct platform_device *pdev) > > > > } > > > > > > > > static const struct of_device_id imx_mu_dt_ids[] = { > > > > - { .compatible = "fsl,imx6sx-mu" }, > > > > + { .compatible = "fsl,imx7ulp-mu", .data = > &imx_mu_cfg_imx7ulp }, > > > > + { .compatible = "fsl,imx6sx-mu", .data = > > > > + &imx_mu_cfg_imx6sx }, > > > > { }, > > > > }; > > > > MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); > > > > -- > > > > 2.7.4 > > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [EXT] Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu 2019-10-12 1:12 ` Richard Zhu @ 2019-10-12 7:24 ` Daniel Baluta 0 siblings, 0 replies; 12+ messages in thread From: Daniel Baluta @ 2019-10-12 7:24 UTC (permalink / raw) To: Richard Zhu Cc: jassisinghbrar, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel On Sat, Oct 12, 2019 at 4:12 AM Richard Zhu <hongxing.zhu@nxp.com> wrote: > > Hi Daniel: > New version patch-set had been sent out on Oct9. > https://patchwork.kernel.org/cover/11180683/ Thanks Richard. Jassi, care to have a look? Daniel ^ permalink raw reply [flat|nested] 12+ messages in thread
[parent not found: <CAEnQRZDk4TjU0nWgGXEV06ZygvSyuPHc61_uT7KRu0j2Aaxj7w@mail.gmail.com>]
* Re: [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu [not found] ` <CAEnQRZDk4TjU0nWgGXEV06ZygvSyuPHc61_uT7KRu0j2Aaxj7w@mail.gmail.com> @ 2019-10-29 21:02 ` Jassi Brar 0 siblings, 0 replies; 12+ messages in thread From: Jassi Brar @ 2019-10-29 21:02 UTC (permalink / raw) To: Daniel Baluta Cc: Richard Zhu, Oleksij Rempel, Daniel Baluta, Aisheng Dong, dl-linux-imx, Linux Kernel Mailing List, linux-arm-kernel, Shawn Guo On Tue, Oct 29, 2019 at 4:07 AM Daniel Baluta <daniel.baluta@gmail.com> wrote: > > Since we got no answer from Jassi in 4 months I think it is safe > to assume that we can get this through Shawn's tree. > Please don't top post. This patchset doesn't lack my love. It contains support for a new platform and was sent after last merge window. I send new features/support only for next release. If you want some urgent bugfixes picked , please send them separately. Cheers! ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-10-29 21:02 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-08-05 4:52 [PATCH v5 0/4] mailbox: imx: bug fix and add support for imx v1 mu Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 1/4] mailbox: imx: Fix Tx doorbell shutdown path Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 2/4] mailbox: imx: Clear the right interrupts at shutdown Richard Zhu 2019-08-05 4:52 ` [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support Richard Zhu 2019-08-05 19:20 ` Daniel Baluta 2019-08-05 4:52 ` [RESEND PATCH v5 4/4] mailbox: imx: add support for imx v1 mu Richard Zhu 2019-08-05 19:21 ` Daniel Baluta 2019-10-08 7:25 ` Daniel Baluta 2019-10-09 1:47 ` [EXT] " Richard Zhu 2019-10-12 1:12 ` Richard Zhu 2019-10-12 7:24 ` Daniel Baluta [not found] ` <CAEnQRZDk4TjU0nWgGXEV06ZygvSyuPHc61_uT7KRu0j2Aaxj7w@mail.gmail.com> 2019-10-29 21:02 ` Jassi Brar
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