[PATCH] ARM: aspeed: g5: Do not set sirq polarity

[PATCH] ARM: aspeed: g5: Do not set sirq polarity

[Joel Stanley]

A feature was added to the aspeed vuart driver to configure the vuart
interrupt (sirq) polarity according to the LPC/eSPI strapping register.

Systems that depend on a active low behaviour (sirq_polarity set to 0)
such as OpenPower boxes also use LPC, so this relationship does not
hold.

The property was added for a Tyan S7106 system which is not supported
in the kernel tree. Should this or other systems wish to use this
feature of the driver they should add it to the machine specific device
tree.

Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...")
Cc: stable@vger.kernel.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 27e5c5cf7712..664630a0e084 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -410,7 +410,6 @@ vuart: serial@1e787000 {
 				interrupts = <8>;
 				clocks = <&syscon ASPEED_CLK_APB>;
 				no-loopback-test;
-				aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
 				status = "disabled";
 			};
 
-- 
2.28.0

Re: [PATCH] ARM: aspeed: g5: Do not set sirq polarity

[Jeremy Kerr]

Hi Joel,

> A feature was added to the aspeed vuart driver to configure the vuart
> interrupt (sirq) polarity according to the LPC/eSPI strapping register.
> 
> Systems that depend on a active low behaviour (sirq_polarity set to 0)
> such as OpenPower boxes also use LPC, so this relationship does not
> hold.
> 
> The property was added for a Tyan S7106 system which is not supported
> in the kernel tree. Should this or other systems wish to use this
> feature of the driver they should add it to the machine specific device
> tree.
> 
> Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...")
> Cc: stable@vger.kernel.org
> Signed-off-by: Joel Stanley <joel@jms.id.au>

LGTM. I've tested this on the s2600st, which is strapped for eSPI. All
good there too, as expected.

Tested-by: Jeremy Kerr <jk@ozlabs.org>

and/or:

Reviewed-by: Jeremy Kerr <jk@ozlabs.org>

Cheers,


Jeremy

Re: [PATCH] ARM: aspeed: g5: Do not set sirq polarity

[Joel Stanley]

On Thu, 27 Aug 2020 at 06:27, Jeremy Kerr <jk@ozlabs.org> wrote:
>
> Hi Joel,
>
> > A feature was added to the aspeed vuart driver to configure the vuart
> > interrupt (sirq) polarity according to the LPC/eSPI strapping register.
> >
> > Systems that depend on a active low behaviour (sirq_polarity set to 0)
> > such as OpenPower boxes also use LPC, so this relationship does not
> > hold.
> >
> > The property was added for a Tyan S7106 system which is not supported
> > in the kernel tree. Should this or other systems wish to use this
> > feature of the driver they should add it to the machine specific device
> > tree.
> >
> > Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
>
> LGTM. I've tested this on the s2600st, which is strapped for eSPI. All
> good there too, as expected.
>
> Tested-by: Jeremy Kerr <jk@ozlabs.org>
>
> and/or:
>
> Reviewed-by: Jeremy Kerr <jk@ozlabs.org>

Thanks Jeremy. I have queued this for 5.10 and applied it to the openbmc tree.

We should also remove the code from the aspeed-vuart driver, as it is
not correct. Better would be a property that is set according to the
system's hardware design.

Cheers,

Joel