Re: PCMCIA not working on Panasonic Toughbook CF-29

Re: PCMCIA not working on Panasonic Toughbook CF-29

[Dominik Brodowski]

On Tue, Oct 15, 2019 at 05:04:28PM +1100, Michael . wrote:
> Good afternoon kernel developers
> Please accept my apology for contacting you directly about this. A
> small group of friends, some of whom are CCed here, have come together
> to try and find a solution to a problem that originated with the
> demise of kernel 2.6:32. First some background to the issue. We are
> all users of Panasonic Toughbook CF-29 models (ranging from Mark 1
> through to Mark 5). These Toughbooks have 2 PCMCIA card slots which
> are used by a variety of people for different purposes. On the CF-29
> Mark 1 through to Mark 3 these slots work without problem. On the
> CF-29 Mark 4 and Mark 5 the last known kernel the top slot worked with
> was 2.6:32. This has been confirmed all all major distros by most of
> the small group of friends I mentioned earlier.
> 
> Thinking it was just a kernel config issue I did some comparisons
> between Debian 6 (Squeeze), Debian 7 (Wheezy), Ubuntu 10.04, and
> Ubuntu 10.10. On all machines both slots functioned as they should
> with Debian 6 and Ubuntu 10.04 but the top slot stopped working on
> Mark 4 and Mark 5 machines on the next release with the next kernel. I
> also tested Ubuntu 10.04 and 10.10 with the 2.6:32 and 2.6:35 kernel
> and both slots worked with the 2.6:32 kernel but not the 2.6:35
> kernel.With my comparisons I merged the config from 2.6:32 into the
> current kernel for Debian 4.19 and rebuilt the kernel, no matter what
> configuration changes I made the top slot still doesn't function on
> Mark 4 and Mark 5 machines.
> 
> This issue, and its apparent start, has been confirmed on all major
> distro family groups. So this brings me, actually the small group of
> dedicated Linux users who own Panasonic Toughbook CF-29s, to contact
> you to ask for help in resolving this issue. I have some questions,
> and I realise the 2.6:32 kernel is long gone now but I'm hoping this
> is not a lost cause, what changes would have occurred between 2.6:32
> and 2.6:33 that would have stopped the hardware working on Mark 4 and
> Mark 5 CF-29 Toughbooks but not Mark 1 through to Mark 3? Would it be
> possible to correct the problem so that the hardware on our machines
> works as it should. While we are not kernel devs or even programmers
> we are enthusiasts who love Linux and our machines and we are hoping
> that together with you and the kernel dev group we can fix this issue
> together.
> 
> I have attached various tar.gz files with ls* outputs so you can see
> the information we have so far. Thank you for taking the time to read
> this.

Is this with 16-bit PCMCIA cards, or with 32-bit CardBus cards? Either case,
please provide the output of

	dmesg

	lspci -vvv

and

	lspcmcia -v -v

(ideally all for a working and non-working configuration).

Thanks,
	Dominik

Re: PCMCIA not working on Panasonic Toughbook CF-29

[Michael .]

Thank you for your prompt reply Dominik, I have asked everyone in the
discussion on Notebook review to gather the information required and
either post it there so I can reply or post it here in the list if it
is from someone in the CC list.

Also thank you for replying to us all and not just on-list, none of us
are subscribed to teh list so if a reply is only on-list none of us
will receive it.

Cheers.
Michael.

On 15/10/2019, Dominik Brodowski <linux@dominikbrodowski.net> wrote:
> On Tue, Oct 15, 2019 at 05:04:28PM +1100, Michael . wrote:
>> Good afternoon kernel developers
>> Please accept my apology for contacting you directly about this. A
>> small group of friends, some of whom are CCed here, have come together
>> to try and find a solution to a problem that originated with the
>> demise of kernel 2.6:32. First some background to the issue. We are
>> all users of Panasonic Toughbook CF-29 models (ranging from Mark 1
>> through to Mark 5). These Toughbooks have 2 PCMCIA card slots which
>> are used by a variety of people for different purposes. On the CF-29
>> Mark 1 through to Mark 3 these slots work without problem. On the
>> CF-29 Mark 4 and Mark 5 the last known kernel the top slot worked with
>> was 2.6:32. This has been confirmed all all major distros by most of
>> the small group of friends I mentioned earlier.
>>
>> Thinking it was just a kernel config issue I did some comparisons
>> between Debian 6 (Squeeze), Debian 7 (Wheezy), Ubuntu 10.04, and
>> Ubuntu 10.10. On all machines both slots functioned as they should
>> with Debian 6 and Ubuntu 10.04 but the top slot stopped working on
>> Mark 4 and Mark 5 machines on the next release with the next kernel. I
>> also tested Ubuntu 10.04 and 10.10 with the 2.6:32 and 2.6:35 kernel
>> and both slots worked with the 2.6:32 kernel but not the 2.6:35
>> kernel.With my comparisons I merged the config from 2.6:32 into the
>> current kernel for Debian 4.19 and rebuilt the kernel, no matter what
>> configuration changes I made the top slot still doesn't function on
>> Mark 4 and Mark 5 machines.
>>
>> This issue, and its apparent start, has been confirmed on all major
>> distro family groups. So this brings me, actually the small group of
>> dedicated Linux users who own Panasonic Toughbook CF-29s, to contact
>> you to ask for help in resolving this issue. I have some questions,
>> and I realise the 2.6:32 kernel is long gone now but I'm hoping this
>> is not a lost cause, what changes would have occurred between 2.6:32
>> and 2.6:33 that would have stopped the hardware working on Mark 4 and
>> Mark 5 CF-29 Toughbooks but not Mark 1 through to Mark 3? Would it be
>> possible to correct the problem so that the hardware on our machines
>> works as it should. While we are not kernel devs or even programmers
>> we are enthusiasts who love Linux and our machines and we are hoping
>> that together with you and the kernel dev group we can fix this issue
>> together.
>>
>> I have attached various tar.gz files with ls* outputs so you can see
>> the information we have so far. Thank you for taking the time to read
>> this.
>
> Is this with 16-bit PCMCIA cards, or with 32-bit CardBus cards? Either
> case,
> please provide the output of
>
> 	dmesg
>
> 	lspci -vvv
>
> and
>
> 	lspcmcia -v -v
>
> (ideally all for a working and non-working configuration).
>
> Thanks,
> 	Dominik
>

PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Dominik Brodowski]

On the basis of the additional information (thanks), there might be a
more specific path to investigate: It is that the PCI code does not
enumerate the second cardbus bridge PCI function in the more recent 4.19
kernel compared to the anvient (and working) 2.6 kernel.

Namely, only one CardBus bridge is recognized

...
06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
06:01.1 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 11)
06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection (rev 05)
...

instead of the two which really should be present:

...
06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
06:01.1 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
06:01.2 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 11)
06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection (rev 05)
...

To the PCI folks: any idea on what may cause the second cardbus bridge PCI
device function to be missed? Are there any command line options the users
who reported this issue[*] may try?

As this isn't really a PCMCIA (16bit) issue, but a PCI enumeration issue,
this issue is outside my area of expertise.

Thanks,
	Dominik

[*] For more information, see this thread:
	https://lore.kernel.org/lkml/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Bjorn Helgaas]

On Sun, Oct 20, 2019 at 11:08:00AM +0200, Dominik Brodowski wrote:
> On the basis of the additional information (thanks), there might be a
> more specific path to investigate: It is that the PCI code does not
> enumerate the second cardbus bridge PCI function in the more recent 4.19
> kernel compared to the anvient (and working) 2.6 kernel.
> 
> Namely, only one CardBus bridge is recognized
> 
> ...
> 06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
> 06:01.1 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 11)
> 06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection (rev 05)
> ...
> 
> instead of the two which really should be present:
> 
> ...
> 06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
> 06:01.1 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
> 06:01.2 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 11)
> 06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection (rev 05)
> ...
> 
> To the PCI folks: any idea on what may cause the second cardbus bridge PCI
> device function to be missed? Are there any command line options the users
> who reported this issue[*] may try?

Thanks for the report.  Could you try disabling
ricoh_mmc_fixup_rl5c476(), e.g., with the patch below (this is based
on v5.4-rc1, but you can use v4.9 if that's easier for you)?  This
isn't a fix; it's just something that looks like it might be related.

> [*] For more information, see this thread:
> 	https://lore.kernel.org/lkml/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/


diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 320255e5e8f8..7a1e1a242506 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3036,38 +3036,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
  * #1, and this will confuse the PCI core.
  */
 #ifdef CONFIG_MMC_RICOH_MMC
-static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
-{
-	u8 write_enable;
-	u8 write_target;
-	u8 disable;
-
-	/*
-	 * Disable via CardBus interface
-	 *
-	 * This must be done via function #0
-	 */
-	if (PCI_FUNC(dev->devfn))
-		return;
-
-	pci_read_config_byte(dev, 0xB7, &disable);
-	if (disable & 0x02)
-		return;
-
-	pci_read_config_byte(dev, 0x8E, &write_enable);
-	pci_write_config_byte(dev, 0x8E, 0xAA);
-	pci_read_config_byte(dev, 0x8D, &write_target);
-	pci_write_config_byte(dev, 0x8D, 0xB7);
-	pci_write_config_byte(dev, 0xB7, disable | 0x02);
-	pci_write_config_byte(dev, 0x8E, write_enable);
-	pci_write_config_byte(dev, 0x8D, write_target);
-
-	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
-	pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
-}
-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
-
 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
 {
 	u8 write_enable;

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Thank you Dominik for looking at this for us and passing it on.

Good morning Bjorn, thank you also for looking into this for us and
thank you for CCing us into this as non of us are on the mailing list.
One question how do we apply this patch or is this for Dominik to try?

Cheers.
Michael

On 22/10/2019, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Sun, Oct 20, 2019 at 11:08:00AM +0200, Dominik Brodowski wrote:
>> On the basis of the additional information (thanks), there might be a
>> more specific path to investigate: It is that the PCI code does not
>> enumerate the second cardbus bridge PCI function in the more recent 4.19
>> kernel compared to the anvient (and working) 2.6 kernel.
>>
>> Namely, only one CardBus bridge is recognized
>>
>> ...
>> 06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
>> 06:01.1 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host
>> Adapter (rev 11)
>> 06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG
>> [Calexico2] Network Connection (rev 05)
>> ...
>>
>> instead of the two which really should be present:
>>
>> ...
>> 06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
>> 06:01.1 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
>> 06:01.2 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host
>> Adapter (rev 11)
>> 06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG
>> [Calexico2] Network Connection (rev 05)
>> ...
>>
>> To the PCI folks: any idea on what may cause the second cardbus bridge
>> PCI
>> device function to be missed? Are there any command line options the
>> users
>> who reported this issue[*] may try?
>
> Thanks for the report.  Could you try disabling
> ricoh_mmc_fixup_rl5c476(), e.g., with the patch below (this is based
> on v5.4-rc1, but you can use v4.9 if that's easier for you)?  This
> isn't a fix; it's just something that looks like it might be related.
>
>> [*] For more information, see this thread:
>> 	https://lore.kernel.org/lkml/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
>
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 320255e5e8f8..7a1e1a242506 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -3036,38 +3036,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020,
> quirk_hotplug_bridge);
>   * #1, and this will confuse the PCI core.
>   */
>  #ifdef CONFIG_MMC_RICOH_MMC
> -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
> -{
> -	u8 write_enable;
> -	u8 write_target;
> -	u8 disable;
> -
> -	/*
> -	 * Disable via CardBus interface
> -	 *
> -	 * This must be done via function #0
> -	 */
> -	if (PCI_FUNC(dev->devfn))
> -		return;
> -
> -	pci_read_config_byte(dev, 0xB7, &disable);
> -	if (disable & 0x02)
> -		return;
> -
> -	pci_read_config_byte(dev, 0x8E, &write_enable);
> -	pci_write_config_byte(dev, 0x8E, 0xAA);
> -	pci_read_config_byte(dev, 0x8D, &write_target);
> -	pci_write_config_byte(dev, 0x8D, 0xB7);
> -	pci_write_config_byte(dev, 0xB7, disable | 0x02);
> -	pci_write_config_byte(dev, 0x8E, write_enable);
> -	pci_write_config_byte(dev, 0x8D, write_target);
> -
> -	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus
> function)\n");
> -	pci_notice(dev, "MMC cards are now supported by standard SDHCI
> controller\n");
> -}
> -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
> ricoh_mmc_fixup_rl5c476);
> -DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH,
> PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
> -
>  static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
>  {
>  	u8 write_enable;
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Dominik Brodowski]

On Tue, Oct 22, 2019 at 05:17:12AM +1100, Michael . wrote:
> Thank you Dominik for looking at this for us and passing it on.
> 
> Good morning Bjorn, thank you also for looking into this for us and
> thank you for CCing us into this as non of us are on the mailing list.
> One question how do we apply this patch or is this for Dominik to try?

That's for you and/or other users of this hardware; I cannot test this
myself, sorry. As to how to apply the patch: you'd need to apply the patch
for the linux kernel sources, and then build a custom kernel. Some hints on
that (details depend on the distribtion):

	https://wiki.ubuntu.com/Kernel/BuildYourOwnKernel
	https://wiki.ubuntu.com/KernelTeam/GitKernelBuild
	https://wiki.archlinux.org/index.php/Kernels/Arch_Build_System
	https://kernelnewbies.org/KernelBuild

Best,
	Dominik

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Thanks Domunik I'll get onto this and report back the results.

On 22/10/2019, Dominik Brodowski <linux@dominikbrodowski.net> wrote:
> On Tue, Oct 22, 2019 at 05:17:12AM +1100, Michael . wrote:
>> Thank you Dominik for looking at this for us and passing it on.
>>
>> Good morning Bjorn, thank you also for looking into this for us and
>> thank you for CCing us into this as non of us are on the mailing list.
>> One question how do we apply this patch or is this for Dominik to try?
>
> That's for you and/or other users of this hardware; I cannot test this
> myself, sorry. As to how to apply the patch: you'd need to apply the patch
> for the linux kernel sources, and then build a custom kernel. Some hints on
> that (details depend on the distribtion):
>
> 	https://wiki.ubuntu.com/Kernel/BuildYourOwnKernel
> 	https://wiki.ubuntu.com/KernelTeam/GitKernelBuild
> 	https://wiki.archlinux.org/index.php/Kernels/Arch_Build_System
> 	https://kernelnewbies.org/KernelBuild
>
> Best,
> 	Dominik
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

[-- Attachment #1: Type: text/plain, Size: 3940 bytes --]

I just tried to do a kernel compile on Debian Sid running kernel 5.2.
Downloaded 4.19.80 modded the quirks file, please find modded file
attached, and started the compile.
About an hour into it it fails with:
  CC      drivers/pci/quirks.o
drivers/pci/quirks.c:2945:1: error: expected identifier or ‘(’ before ‘-’ token
 2945 | -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
      | ^
drivers/pci/quirks.c:2974:1: error: expected identifier or ‘(’ before ‘-’ token
 2974 | -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
      | ^
drivers/pci/quirks.c:2975:1: error: expected identifier or ‘(’ before ‘-’ token
 2975 | -DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
      | ^
drivers/pci/quirks.c:2976:1: error: expected identifier or ‘(’ before ‘-’ token
 2976 | -
      | ^
In file included from ./include/linux/export.h:45,
                 from ./include/linux/linkage.h:7,
                 from ./include/linux/kernel.h:7,
                 from drivers/pci/quirks.c:16:
drivers/pci/quirks.c:3026:74: error: ‘ricoh_mmc_fixup_r5c832’
undeclared here (not in a function)
 3026 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
      |
          ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/compiler.h:296:53: note: in definition of macro ‘__ADDRESSABLE’
  296 |   __PASTE(__addressable_##sym, __LINE__) = (void *)&sym;
      |                                                     ^~~
./include/linux/pci.h:1847:2: note: in expansion of macro
‘__DECLARE_PCI_FIXUP_SECTION’
 1847 |  __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
      |  ^~~~~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/pci.h:1892:2: note: in expansion of macro
‘DECLARE_PCI_FIXUP_SECTION’
 1892 |  DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,   \
      |  ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pci/quirks.c:3026:1: note: in expansion of macro
‘DECLARE_PCI_FIXUP_EARLY’
 3026 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
      | ^~~~~~~~~~~~~~~~~~~~~~~
make[5]: *** [scripts/Makefile.build:304: drivers/pci/quirks.o] Error 1
make[4]: *** [scripts/Makefile.build:544: drivers/pci] Error 2
make[3]: *** [Makefile:1046: drivers] Error 2
make[2]: *** [debian/rules:4: build] Error 2
dpkg-buildpackage: error: debian/rules build subprocess returned exit status 2
make[1]: *** [scripts/package/Makefile:75: deb-pkg] Error 2
make: *** [Makefile:1359: deb-pkg] Error 2
root@michael-desktop:/home/michael/Debian/linux-4.19.80#

I will try later with the latest 5.4-rc to see if the diff is
incompatible with 4.19.
Cheers.
Michael

On 22/10/2019, Michael . <keltoiboy@gmail.com> wrote:
> Thanks Domunik I'll get onto this and report back the results.
>
> On 22/10/2019, Dominik Brodowski <linux@dominikbrodowski.net> wrote:
>> On Tue, Oct 22, 2019 at 05:17:12AM +1100, Michael . wrote:
>>> Thank you Dominik for looking at this for us and passing it on.
>>>
>>> Good morning Bjorn, thank you also for looking into this for us and
>>> thank you for CCing us into this as non of us are on the mailing list.
>>> One question how do we apply this patch or is this for Dominik to try?
>>
>> That's for you and/or other users of this hardware; I cannot test this
>> myself, sorry. As to how to apply the patch: you'd need to apply the
>> patch
>> for the linux kernel sources, and then build a custom kernel. Some hints
>> on
>> that (details depend on the distribtion):
>>
>> 	https://wiki.ubuntu.com/Kernel/BuildYourOwnKernel
>> 	https://wiki.ubuntu.com/KernelTeam/GitKernelBuild
>> 	https://wiki.archlinux.org/index.php/Kernels/Arch_Build_System
>> 	https://kernelnewbies.org/KernelBuild
>>
>> Best,
>> 	Dominik
>>
>

[-- Attachment #2: quirks.c --]
[-- Type: text/x-csrc, Size: 186451 bytes --]

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains work-arounds for many known PCI hardware bugs.
 * Devices present only on certain architectures (host bridges et cetera)
 * should be handled in arch-specific code.
 *
 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
 *
 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
 *
 * Init/reset quirks for USB host controllers should be in the USB quirks
 * file, where their drivers can use them.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/pci-aspm.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/switchtec.h>
#include <asm/dma.h>	/* isa_dma_bridge_buggy */
#include "pci.h"

static ktime_t fixup_debug_start(struct pci_dev *dev,
				 void (*fn)(struct pci_dev *dev))
{
	if (initcall_debug)
		pci_info(dev, "calling  %pF @ %i\n", fn, task_pid_nr(current));

	return ktime_get();
}

static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
			       void (*fn)(struct pci_dev *dev))
{
	ktime_t delta, rettime;
	unsigned long long duration;

	rettime = ktime_get();
	delta = ktime_sub(rettime, calltime);
	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
	if (initcall_debug || duration > 10000)
		pci_info(dev, "%pF took %lld usecs\n", fn, duration);
}

static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
			  struct pci_fixup *end)
{
	ktime_t calltime;

	for (; f < end; f++)
		if ((f->class == (u32) (dev->class >> f->class_shift) ||
		     f->class == (u32) PCI_ANY_ID) &&
		    (f->vendor == dev->vendor ||
		     f->vendor == (u16) PCI_ANY_ID) &&
		    (f->device == dev->device ||
		     f->device == (u16) PCI_ANY_ID)) {
			void (*hook)(struct pci_dev *dev);
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
			hook = offset_to_ptr(&f->hook_offset);
#else
			hook = f->hook;
#endif
			calltime = fixup_debug_start(dev, hook);
			hook(dev);
			fixup_debug_report(dev, calltime, hook);
		}
}

extern struct pci_fixup __start_pci_fixups_early[];
extern struct pci_fixup __end_pci_fixups_early[];
extern struct pci_fixup __start_pci_fixups_header[];
extern struct pci_fixup __end_pci_fixups_header[];
extern struct pci_fixup __start_pci_fixups_final[];
extern struct pci_fixup __end_pci_fixups_final[];
extern struct pci_fixup __start_pci_fixups_enable[];
extern struct pci_fixup __end_pci_fixups_enable[];
extern struct pci_fixup __start_pci_fixups_resume[];
extern struct pci_fixup __end_pci_fixups_resume[];
extern struct pci_fixup __start_pci_fixups_resume_early[];
extern struct pci_fixup __end_pci_fixups_resume_early[];
extern struct pci_fixup __start_pci_fixups_suspend[];
extern struct pci_fixup __end_pci_fixups_suspend[];
extern struct pci_fixup __start_pci_fixups_suspend_late[];
extern struct pci_fixup __end_pci_fixups_suspend_late[];

static bool pci_apply_fixup_final_quirks;

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
{
	struct pci_fixup *start, *end;

	switch (pass) {
	case pci_fixup_early:
		start = __start_pci_fixups_early;
		end = __end_pci_fixups_early;
		break;

	case pci_fixup_header:
		start = __start_pci_fixups_header;
		end = __end_pci_fixups_header;
		break;

	case pci_fixup_final:
		if (!pci_apply_fixup_final_quirks)
			return;
		start = __start_pci_fixups_final;
		end = __end_pci_fixups_final;
		break;

	case pci_fixup_enable:
		start = __start_pci_fixups_enable;
		end = __end_pci_fixups_enable;
		break;

	case pci_fixup_resume:
		start = __start_pci_fixups_resume;
		end = __end_pci_fixups_resume;
		break;

	case pci_fixup_resume_early:
		start = __start_pci_fixups_resume_early;
		end = __end_pci_fixups_resume_early;
		break;

	case pci_fixup_suspend:
		start = __start_pci_fixups_suspend;
		end = __end_pci_fixups_suspend;
		break;

	case pci_fixup_suspend_late:
		start = __start_pci_fixups_suspend_late;
		end = __end_pci_fixups_suspend_late;
		break;

	default:
		/* stupid compiler warning, you would think with an enum... */
		return;
	}
	pci_do_fixups(dev, start, end);
}
EXPORT_SYMBOL(pci_fixup_device);

static int __init pci_apply_final_quirks(void)
{
	struct pci_dev *dev = NULL;
	u8 cls = 0;
	u8 tmp;

	if (pci_cache_line_size)
		printk(KERN_DEBUG "PCI: CLS %u bytes\n",
		       pci_cache_line_size << 2);

	pci_apply_fixup_final_quirks = true;
	for_each_pci_dev(dev) {
		pci_fixup_device(pci_fixup_final, dev);
		/*
		 * If arch hasn't set it explicitly yet, use the CLS
		 * value shared by all PCI devices.  If there's a
		 * mismatch, fall back to the default value.
		 */
		if (!pci_cache_line_size) {
			pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
			if (!cls)
				cls = tmp;
			if (!tmp || cls == tmp)
				continue;

			printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
			       cls << 2, tmp << 2,
			       pci_dfl_cache_line_size << 2);
			pci_cache_line_size = pci_dfl_cache_line_size;
		}
	}

	if (!pci_cache_line_size) {
		printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
		       cls << 2, pci_dfl_cache_line_size << 2);
		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
	}

	return 0;
}
fs_initcall_sync(pci_apply_final_quirks);

/*
 * Decoding should be disabled for a PCI device during BAR sizing to avoid
 * conflict. But doing so may cause problems on host bridge and perhaps other
 * key system devices. For devices that need to have mmio decoding always-on,
 * we need to set the dev->mmio_always_on bit.
 */
static void quirk_mmio_always_on(struct pci_dev *dev)
{
	dev->mmio_always_on = 1;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
				PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);

/*
 * The Mellanox Tavor device gives false positive parity errors.  Mark this
 * device with a broken_parity_status to allow PCI scanning code to "skip"
 * this now blacklisted device.
 */
static void quirk_mellanox_tavor(struct pci_dev *dev)
{
	dev->broken_parity_status = 1;	/* This device gives false positives */
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);

/*
 * Deal with broken BIOSes that neglect to enable passive release,
 * which can cause problems in combination with the 82441FX/PPro MTRRs
 */
static void quirk_passive_release(struct pci_dev *dev)
{
	struct pci_dev *d = NULL;
	unsigned char dlc;

	/*
	 * We have to make sure a particular bit is set in the PIIX3
	 * ISA bridge, so we have to go out and find it.
	 */
	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
		pci_read_config_byte(d, 0x82, &dlc);
		if (!(dlc & 1<<1)) {
			pci_info(d, "PIIX3: Enabling Passive Release\n");
			dlc |= 1<<1;
			pci_write_config_byte(d, 0x82, dlc);
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);

/*
 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
 * workaround but VIA don't answer queries. If you happen to have good
 * contacts at VIA ask them for me please -- Alan
 *
 * This appears to be BIOS not version dependent. So presumably there is a
 * chipset level fix.
 */
static void quirk_isa_dma_hangs(struct pci_dev *dev)
{
	if (!isa_dma_bridge_buggy) {
		isa_dma_bridge_buggy = 1;
		pci_info(dev, "Activating ISA DMA hang workarounds\n");
	}
}
/*
 * It's not totally clear which chipsets are the problematic ones.  We know
 * 82C586 and 82C596 variants are affected.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_0,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C596,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1533,		quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_1,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs);

/*
 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
 * for some HT machines to use C4 w/o hanging.
 */
static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
{
	u32 pmbase;
	u16 pm1a;

	pci_read_config_dword(dev, 0x40, &pmbase);
	pmbase = pmbase & 0xff80;
	pm1a = inw(pmbase);

	if (pm1a & 0x10) {
		pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
		outw(0x10, pmbase);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);

/* Chipsets where PCI->PCI transfers vanish or hang */
static void quirk_nopcipci(struct pci_dev *dev)
{
	if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
		pci_info(dev, "Disabling direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_FAIL;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci);

static void quirk_nopciamd(struct pci_dev *dev)
{
	u8 rev;
	pci_read_config_byte(dev, 0x08, &rev);
	if (rev == 0x13) {
		/* Erratum 24 */
		pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
		pci_pci_problems |= PCIAGP_FAIL;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopciamd);

/* Triton requires workarounds to be used by the drivers */
static void quirk_triton(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_TRITON;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437VX,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439TX,	quirk_triton);

/*
 * VIA Apollo KT133 needs PCI latency patch
 * Made according to a Windows driver-based patch by George E. Breese;
 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
 * which Mr Breese based his work.
 *
 * Updated based on further information from the site and also on
 * information provided by VIA
 */
static void quirk_vialatency(struct pci_dev *dev)
{
	struct pci_dev *p;
	u8 busarb;

	/*
	 * Ok, we have a potential problem chipset here. Now see if we have
	 * a buggy southbridge.
	 */
	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
	if (p != NULL) {

		/*
		 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
		 * thanks Dan Hollis.
		 * Check for buggy part revisions
		 */
		if (p->revision < 0x40 || p->revision > 0x42)
			goto exit;
	} else {
		p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
		if (p == NULL)	/* No problem parts */
			goto exit;

		/* Check for buggy part revisions */
		if (p->revision < 0x10 || p->revision > 0x12)
			goto exit;
	}

	/*
	 * Ok we have the problem. Now set the PCI master grant to occur
	 * every master grant. The apparent bug is that under high PCI load
	 * (quite common in Linux of course) you can get data loss when the
	 * CPU is held off the bus for 3 bus master requests.  This happens
	 * to include the IDE controllers....
	 *
	 * VIA only apply this fix when an SB Live! is present but under
	 * both Linux and Windows this isn't enough, and we have seen
	 * corruption without SB Live! but with things like 3 UDMA IDE
	 * controllers. So we ignore that bit of the VIA recommendation..
	 */
	pci_read_config_byte(dev, 0x76, &busarb);

	/*
	 * Set bit 4 and bit 5 of byte 76 to 0x01
	 * "Master priority rotation on every PCI master grant"
	 */
	busarb &= ~(1<<5);
	busarb |= (1<<4);
	pci_write_config_byte(dev, 0x76, busarb);
	pci_info(dev, "Applying VIA southbridge workaround\n");
exit:
	pci_dev_put(p);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
/* Must restore this on a resume from RAM */
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);

/* VIA Apollo VP3 needs ETBF on BT848/878 */
static void quirk_viaetbf(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_VIAETBF;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_viaetbf);

static void quirk_vsfx(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_VSFX;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx);

/*
 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
 * space. Latency must be set to 0xA and Triton workaround applied too.
 * [Info kindly provided by ALi]
 */
static void quirk_alimagik(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1647,		quirk_alimagik);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagik);

/* Natoma has some interesting boundary conditions with Zoran stuff at least */
static void quirk_natoma(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_NATOMA;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_0,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_1,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_0,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_1,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_2,	quirk_natoma);

/*
 * This chip can cause PCI parity errors if config register 0xA0 is read
 * while DMAs are occurring.
 */
static void quirk_citrine(struct pci_dev *dev)
{
	dev->cfg_size = 0xA0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine);

/*
 * This chip can cause bus lockups if config addresses above 0x600
 * are read or written.
 */
static void quirk_nfp6000(struct pci_dev *dev)
{
	dev->cfg_size = 0x600;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP4000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP5000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000_VF,	quirk_nfp6000);

/*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
static void quirk_extend_bar_to_page(struct pci_dev *dev)
{
	int i;

	for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
		struct resource *r = &dev->resource[i];

		if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
			r->end = PAGE_SIZE - 1;
			r->start = 0;
			r->flags |= IORESOURCE_UNSET;
			pci_info(dev, "expanded BAR %d to page size: %pR\n",
				 i, r);
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);

/*
 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 * If it's needed, re-allocate the region.
 */
static void quirk_s3_64M(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[0];

	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
		r->flags |= IORESOURCE_UNSET;
		r->start = 0;
		r->end = 0x3ffffff;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_868,		quirk_s3_64M);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_968,		quirk_s3_64M);

static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
		     const char *name)
{
	u32 region;
	struct pci_bus_region bus_region;
	struct resource *res = dev->resource + pos;

	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);

	if (!region)
		return;

	res->name = pci_name(dev);
	res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
	res->flags |=
		(IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
	region &= ~(size - 1);

	/* Convert from PCI bus to resource space */
	bus_region.start = region;
	bus_region.end = region + size - 1;
	pcibios_bus_to_resource(dev->bus, res, &bus_region);

	pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
		 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
}

/*
 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
 * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
 * (which conflicts w/ BAR1's memory range).
 *
 * CS553x's ISA PCI BARs may also be read-only (ref:
 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
 */
static void quirk_cs5536_vsa(struct pci_dev *dev)
{
	static char *name = "CS5536 ISA bridge";

	if (pci_resource_len(dev, 0) != 8) {
		quirk_io(dev, 0,   8, name);	/* SMB */
		quirk_io(dev, 1, 256, name);	/* GPIO */
		quirk_io(dev, 2,  64, name);	/* MFGPT */
		pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
			 name);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);

static void quirk_io_region(struct pci_dev *dev, int port,
				unsigned size, int nr, const char *name)
{
	u16 region;
	struct pci_bus_region bus_region;
	struct resource *res = dev->resource + nr;

	pci_read_config_word(dev, port, &region);
	region &= ~(size - 1);

	if (!region)
		return;

	res->name = pci_name(dev);
	res->flags = IORESOURCE_IO;

	/* Convert from PCI bus to resource space */
	bus_region.start = region;
	bus_region.end = region + size - 1;
	pcibios_bus_to_resource(dev->bus, res, &bus_region);

	if (!pci_claim_resource(dev, nr))
		pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
}

/*
 * ATI Northbridge setups MCE the processor if you even read somewhere
 * between 0x3b0->0x3bb or read 0x3d3
 */
static void quirk_ati_exploding_mce(struct pci_dev *dev)
{
	pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
	/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
	request_region(0x3b0, 0x0C, "RadeonIGP");
	request_region(0x3d3, 0x01, "RadeonIGP");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);

/*
 * In the AMD NL platform, this device ([1022:7912]) has a class code of
 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
 * claim it.
 *
 * But the dwc3 driver is a more specific driver for this device, and we'd
 * prefer to use it instead of xhci. To prevent xhci from claiming the
 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
 * defines as "USB device (not host controller)". The dwc3 driver can then
 * claim it based on its Vendor and Device ID.
 */
static void quirk_amd_nl_class(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	/* Use "USB Device (not host controller)" class */
	pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
	pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
		 class, pdev->class);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
		quirk_amd_nl_class);

/*
 * Let's make the southbridge information explicit instead of having to
 * worry about people probing the ACPI areas, for example.. (Yes, it
 * happens, and if you read the wrong ACPI register it will put the machine
 * to sleep with no way of waking it up again. Bummer).
 *
 * ALI M7101: Two IO regions pointed to by words at
 *	0xE0 (64 bytes of ACPI registers)
 *	0xE2 (32 bytes of SMB registers)
 */
static void quirk_ali7101_acpi(struct pci_dev *dev)
{
	quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
	quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi);

static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
{
	u32 devres;
	u32 mask, size, base;

	pci_read_config_dword(dev, port, &devres);
	if ((devres & enable) != enable)
		return;
	mask = (devres >> 16) & 15;
	base = devres & 0xffff;
	size = 16;
	for (;;) {
		unsigned bit = size >> 1;
		if ((bit & mask) == bit)
			break;
		size = bit;
	}
	/*
	 * For now we only print it out. Eventually we'll want to
	 * reserve it (at least if it's in the 0x1000+ range), but
	 * let's get enough confirmation reports first.
	 */
	base &= -size;
	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
}

static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
{
	u32 devres;
	u32 mask, size, base;

	pci_read_config_dword(dev, port, &devres);
	if ((devres & enable) != enable)
		return;
	base = devres & 0xffff0000;
	mask = (devres & 0x3f) << 16;
	size = 128 << 16;
	for (;;) {
		unsigned bit = size >> 1;
		if ((bit & mask) == bit)
			break;
		size = bit;
	}

	/*
	 * For now we only print it out. Eventually we'll want to
	 * reserve it, but let's get enough confirmation reports first.
	 */
	base &= -size;
	pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
}

/*
 * PIIX4 ACPI: Two IO regions pointed to by longwords at
 *	0x40 (64 bytes of ACPI registers)
 *	0x90 (16 bytes of SMB registers)
 * and a few strange programmable PIIX4 device resources.
 */
static void quirk_piix4_acpi(struct pci_dev *dev)
{
	u32 res_a;

	quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");

	/* Device resource A has enables for some of the other ones */
	pci_read_config_dword(dev, 0x5c, &res_a);

	piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
	piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);

	/* Device resource D is just bitfields for static resources */

	/* Device 12 enabled? */
	if (res_a & (1 << 29)) {
		piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
		piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
	}
	/* Device 13 enabled? */
	if (res_a & (1 << 30)) {
		piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
		piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
	}
	piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
	piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_3,	quirk_piix4_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443MX_3,	quirk_piix4_acpi);

#define ICH_PMBASE	0x40
#define ICH_ACPI_CNTL	0x44
#define  ICH4_ACPI_EN	0x10
#define  ICH6_ACPI_EN	0x80
#define ICH4_GPIOBASE	0x58
#define ICH4_GPIO_CNTL	0x5c
#define  ICH4_GPIO_EN	0x10
#define ICH6_GPIOBASE	0x48
#define ICH6_GPIO_CNTL	0x4c
#define  ICH6_GPIO_EN	0x10

/*
 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 *	0x40 (128 bytes of ACPI, GPIO & TCO registers)
 *	0x58 (64 bytes of GPIO I/O space)
 */
static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
{
	u8 enable;

	/*
	 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
	 * with low legacy (and fixed) ports. We don't know the decoding
	 * priority and can't tell whether the legacy device or the one created
	 * here is really at that address.  This happens on boards with broken
	 * BIOSes.
	 */
	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
	if (enable & ICH4_ACPI_EN)
		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
				 "ICH4 ACPI/GPIO/TCO");

	pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
	if (enable & ICH4_GPIO_EN)
		quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
				"ICH4 GPIO");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi);

static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
{
	u8 enable;

	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
	if (enable & ICH6_ACPI_EN)
		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
				 "ICH6 ACPI/GPIO/TCO");

	pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
	if (enable & ICH6_GPIO_EN)
		quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
				"ICH6 GPIO");
}

static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
				    const char *name, int dynsize)
{
	u32 val;
	u32 size, base;

	pci_read_config_dword(dev, reg, &val);

	/* Enabled? */
	if (!(val & 1))
		return;
	base = val & 0xfffc;
	if (dynsize) {
		/*
		 * This is not correct. It is 16, 32 or 64 bytes depending on
		 * register D31:F0:ADh bits 5:4.
		 *
		 * But this gets us at least _part_ of it.
		 */
		size = 16;
	} else {
		size = 128;
	}
	base &= ~(size-1);

	/*
	 * Just print it out for now. We should reserve it after more
	 * debugging.
	 */
	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
}

static void quirk_ich6_lpc(struct pci_dev *dev)
{
	/* Shared ACPI/GPIO decode with all ICH6+ */
	ich6_lpc_acpi_gpio(dev);

	/* ICH6-specific generic IO decode */
	ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
	ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);

static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
				    const char *name)
{
	u32 val;
	u32 mask, base;

	pci_read_config_dword(dev, reg, &val);

	/* Enabled? */
	if (!(val & 1))
		return;

	/* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
	base = val & 0xfffc;
	mask = (val >> 16) & 0xfc;
	mask |= 3;

	/*
	 * Just print it out for now. We should reserve it after more
	 * debugging.
	 */
	pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
}

/* ICH7-10 has the same common LPC generic IO decode registers */
static void quirk_ich7_lpc(struct pci_dev *dev)
{
	/* We share the common ACPI/GPIO decode with ICH6 */
	ich6_lpc_acpi_gpio(dev);

	/* And have 4 ICH7+ generic decodes */
	ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
	ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
	ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
	ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);

/*
 * VIA ACPI: One IO region pointed to by longword at
 *	0x48 or 0x20 (256 bytes of ACPI registers)
 */
static void quirk_vt82c586_acpi(struct pci_dev *dev)
{
	if (dev->revision & 0x10)
		quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
				"vt82c586 ACPI");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_vt82c586_acpi);

/*
 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 *	0x48 (256 bytes of ACPI registers)
 *	0x70 (128 bytes of hardware monitoring register)
 *	0x90 (16 bytes of SMB registers)
 */
static void quirk_vt82c686_acpi(struct pci_dev *dev)
{
	quirk_vt82c586_acpi(dev);

	quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
				 "vt82c686 HW-mon");

	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi);

/*
 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 *	0x88 (128 bytes of power management registers)
 *	0xd0 (16 bytes of SMB registers)
 */
static void quirk_vt8235_acpi(struct pci_dev *dev)
{
	quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
	quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);

/*
 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
 * back-to-back: Disable fast back-to-back on the secondary bus segment
 */
static void quirk_xio2000a(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 command;

	pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
	list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
		pci_read_config_word(pdev, PCI_COMMAND, &command);
		if (command & PCI_COMMAND_FAST_BACK)
			pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
			quirk_xio2000a);

#ifdef CONFIG_X86_IO_APIC

#include <asm/io_apic.h>

/*
 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 * devices to the external APIC.
 *
 * TODO: When we have device-specific interrupt routers, this code will go
 * away from quirks.
 */
static void quirk_via_ioapic(struct pci_dev *dev)
{
	u8 tmp;

	if (nr_ioapics < 1)
		tmp = 0;    /* nothing routed to external APIC */
	else
		tmp = 0x1f; /* all known bits (4-0) routed to external APIC */

	pci_info(dev, "%sbling VIA external APIC routing\n",
	       tmp == 0 ? "Disa" : "Ena");

	/* Offset 0x58: External APIC IRQ output control */
	pci_write_config_byte(dev, 0x58, tmp);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);

/*
 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
 * This leads to doubled level interrupt rates.
 * Set this bit to get rid of cycle wastage.
 * Otherwise uncritical.
 */
static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
{
	u8 misc_control2;
#define BYPASS_APIC_DEASSERT 8

	pci_read_config_byte(dev, 0x5B, &misc_control2);
	if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
		pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
		pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

/*
 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
 * We check all revs >= B0 (yet not in the pre production!) as the bug
 * is currently marked NoFix
 *
 * We have multiple reports of hangs with this chipset that went away with
 * noapic specified. For the moment we assume it's the erratum. We may be wrong
 * of course. However the advice is demonstrably good even if so.
 */
static void quirk_amd_ioapic(struct pci_dev *dev)
{
	if (dev->revision >= 0x02) {
		pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
		pci_warn(dev, "        : booting with the \"noapic\" option\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);
#endif /* CONFIG_X86_IO_APIC */

#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)

static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
{
	/* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
	if (dev->subsystem_device == 0xa118)
		dev->sriov->link = dev->devfn;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
#endif

/*
 * Some settings of MMRBC can lead to data corruption so block changes.
 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
 */
static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
{
	if (dev->subordinate && dev->revision <= 0x12) {
		pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
			 dev->revision);
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);

/*
 * FIXME: it is questionable that quirk_via_acpi() is needed.  It shows up
 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
 * at all.  Therefore it seems like setting the pci_dev's IRQ to the value
 * of the ACPI SCI interrupt is only done for convenience.
 *	-jgarzik
 */
static void quirk_via_acpi(struct pci_dev *d)
{
	u8 irq;

	/* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
	pci_read_config_byte(d, 0x42, &irq);
	irq &= 0xf;
	if (irq && (irq != 2))
		d->irq = irq;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi);

/* VIA bridges which have VLink */
static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;

static void quirk_via_bridge(struct pci_dev *dev)
{
	/* See what bridge we have and find the device ranges */
	switch (dev->device) {
	case PCI_DEVICE_ID_VIA_82C686:
		/*
		 * The VT82C686 is special; it attaches to PCI and can have
		 * any device number. All its subdevices are functions of
		 * that single device.
		 */
		via_vlink_dev_lo = PCI_SLOT(dev->devfn);
		via_vlink_dev_hi = PCI_SLOT(dev->devfn);
		break;
	case PCI_DEVICE_ID_VIA_8237:
	case PCI_DEVICE_ID_VIA_8237A:
		via_vlink_dev_lo = 15;
		break;
	case PCI_DEVICE_ID_VIA_8235:
		via_vlink_dev_lo = 16;
		break;
	case PCI_DEVICE_ID_VIA_8231:
	case PCI_DEVICE_ID_VIA_8233_0:
	case PCI_DEVICE_ID_VIA_8233A:
	case PCI_DEVICE_ID_VIA_8233C_0:
		via_vlink_dev_lo = 17;
		break;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8231,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233_0,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233A,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233C_0,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237A,	quirk_via_bridge);

/*
 * quirk_via_vlink		-	VIA VLink IRQ number update
 * @dev: PCI device
 *
 * If the device we are dealing with is on a PIC IRQ we need to ensure that
 * the IRQ line register which usually is not relevant for PCI cards, is
 * actually written so that interrupts get sent to the right place.
 *
 * We only do this on systems where a VIA south bridge was detected, and
 * only for VIA devices on the motherboard (see quirk_via_bridge above).
 */
static void quirk_via_vlink(struct pci_dev *dev)
{
	u8 irq, new_irq;

	/* Check if we have VLink at all */
	if (via_vlink_dev_lo == -1)
		return;

	new_irq = dev->irq;

	/* Don't quirk interrupts outside the legacy IRQ range */
	if (!new_irq || new_irq > 15)
		return;

	/* Internal device ? */
	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
	    PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
		return;

	/*
	 * This is an internal VLink device on a PIC interrupt. The BIOS
	 * ought to have set this but may not have, so we redo it.
	 */
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	if (new_irq != irq) {
		pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
			irq, new_irq);
		udelay(15);	/* unknown if delay really needed */
		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);

/*
 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
 * of VT82C597 for backward compatibility.  We need to switch it off to be
 * able to recognize the real type of the chip.
 */
static void quirk_vt82c598_id(struct pci_dev *dev)
{
	pci_write_config_byte(dev, 0xfc, 0);
	pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_vt82c598_id);

/*
 * CardBus controllers have a legacy base address that enables them to
 * respond as i82365 pcmcia controllers.  We don't want them to do this
 * even if the Linux CardBus driver is not loaded, because the Linux i82365
 * driver does not (and should not) handle CardBus.
 */
static void quirk_cardbus_legacy(struct pci_dev *dev)
{
	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);

/*
 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
 * what the designers were smoking but let's not inhale...
 *
 * To be fair to AMD, it follows the spec by default, it's BIOS people who
 * turn it off!
 */
static void quirk_amd_ordering(struct pci_dev *dev)
{
	u32 pcic;
	pci_read_config_dword(dev, 0x4C, &pcic);
	if ((pcic & 6) != 6) {
		pcic |= 6;
		pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
		pci_write_config_dword(dev, 0x4C, pcic);
		pci_read_config_dword(dev, 0x84, &pcic);
		pcic |= (1 << 23);	/* Required in this mode */
		pci_write_config_dword(dev, 0x84, pcic);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);

/*
 * DreamWorks-provided workaround for Dunord I-3000 problem
 *
 * This card decodes and responds to addresses not apparently assigned to
 * it.  We force a larger allocation to ensure that nothing gets put too
 * close to it.
 */
static void quirk_dunord(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[1];

	r->flags |= IORESOURCE_UNSET;
	r->start = 0;
	r->end = 0xffffff;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,	PCI_DEVICE_ID_DUNORD_I3000,	quirk_dunord);

/*
 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
 * decoding (transparent), and does indicate this in the ProgIf.
 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
 */
static void quirk_transparent_bridge(struct pci_dev *dev)
{
	dev->transparent = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82380FB,	quirk_transparent_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA,	0x605,	quirk_transparent_bridge);

/*
 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
 * PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1 datasheets
 * found at http://www.national.com/analog for info on what these bits do.
 * <christer@weinigel.se>
 */
static void quirk_mediagx_master(struct pci_dev *dev)
{
	u8 reg;

	pci_read_config_byte(dev, 0x41, &reg);
	if (reg & 2) {
		reg &= ~2;
		pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
			 reg);
		pci_write_config_byte(dev, 0x41, reg);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);

/*
 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
 * in the odd case it is not the results are corruption hence the presence
 * of a Linux check.
 */
static void quirk_disable_pxb(struct pci_dev *pdev)
{
	u16 config;

	if (pdev->revision != 0x04)		/* Only C0 requires this */
		return;
	pci_read_config_word(pdev, 0x40, &config);
	if (config & (1<<6)) {
		config &= ~(1<<6);
		pci_write_config_word(pdev, 0x40, config);
		pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);

static void quirk_amd_ide_mode(struct pci_dev *pdev)
{
	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
	u8 tmp;

	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
	if (tmp == 0x01) {
		pci_read_config_byte(pdev, 0x40, &tmp);
		pci_write_config_byte(pdev, 0x40, tmp|1);
		pci_write_config_byte(pdev, 0x9, 1);
		pci_write_config_byte(pdev, 0xa, 6);
		pci_write_config_byte(pdev, 0x40, tmp);

		pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
		pci_info(pdev, "set SATA to AHCI mode\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);

/* Serverworks CSB5 IDE does not fully support native mode */
static void quirk_svwks_csb5ide(struct pci_dev *pdev)
{
	u8 prog;
	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
	if (prog & 5) {
		prog &= ~5;
		pdev->class &= ~5;
		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
		/* PCI layer will sort out resources */
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);

/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
static void quirk_ide_samemode(struct pci_dev *pdev)
{
	u8 prog;

	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);

	if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
		pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
		prog &= ~5;
		pdev->class &= ~5;
		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);

/* Some ATA devices break if put into D3 */
static void quirk_no_ata_d3(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
}
/* Quirk the legacy ATA devices only. The AHCI ones are ok */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
/* ALi loses some register settings that we cannot then restore */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
   occur when mode detecting */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);

/*
 * This was originally an Alpha-specific thing, but it really fits here.
 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
 */
static void quirk_eisa_bridge(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82375,	quirk_eisa_bridge);

/*
 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
 * is not activated. The myth is that Asus said that they do not want the
 * users to be irritated by just another PCI Device in the Win98 device
 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
 * package 2.7.0 for details)
 *
 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
 * becomes necessary to do this tweak in two steps -- the chosen trigger
 * is either the Host bridge (preferred) or on-board VGA controller.
 *
 * Note that we used to unhide the SMBus that way on Toshiba laptops
 * (Satellite A40 and Tecra M2) but then found that the thermal management
 * was done by SMM code, which could cause unsynchronized concurrent
 * accesses to the SMBus registers, with potentially bad effects. Thus you
 * should be very careful when adding new entries: if SMM is accessing the
 * Intel SMBus, this is a very good reason to leave it hidden.
 *
 * Likewise, many recent laptops use ACPI for thermal management. If the
 * ACPI DSDT code accesses the SMBus, then Linux should not access it
 * natively, and keeping the SMBus hidden is the right thing to do. If you
 * are about to add an entry in the table below, please first disassemble
 * the DSDT and double-check that there is no code accessing the SMBus.
 */
static int asus_hides_smbus;

static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
{
	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
		if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
			switch (dev->subsystem_device) {
			case 0x8025: /* P4B-LX */
			case 0x8070: /* P4B */
			case 0x8088: /* P4B533 */
			case 0x1626: /* L3C notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
			switch (dev->subsystem_device) {
			case 0x80b1: /* P4GE-V */
			case 0x80b2: /* P4PE */
			case 0x8093: /* P4B533-V */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
			switch (dev->subsystem_device) {
			case 0x8030: /* P4T533 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
			switch (dev->subsystem_device) {
			case 0x8070: /* P4G8X Deluxe */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
			switch (dev->subsystem_device) {
			case 0x80c9: /* PU-DLS */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
			switch (dev->subsystem_device) {
			case 0x1751: /* M2N notebook */
			case 0x1821: /* M5N notebook */
			case 0x1897: /* A6L notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x184b: /* W1N notebook */
			case 0x186a: /* M6Ne notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
			switch (dev->subsystem_device) {
			case 0x80f2: /* P4P800-X */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
			switch (dev->subsystem_device) {
			case 0x1882: /* M6V notebook */
			case 0x1977: /* A6VA notebook */
				asus_hides_smbus = 1;
			}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x088C: /* HP Compaq nc8000 */
			case 0x0890: /* HP Compaq nc6000 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
			switch (dev->subsystem_device) {
			case 0x12bc: /* HP D330L */
			case 0x12bd: /* HP D530 */
			case 0x006a: /* HP Compaq nx9500 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
			switch (dev->subsystem_device) {
			case 0x12bf: /* HP xw4100 */
				asus_hides_smbus = 1;
			}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0xC00C: /* Samsung P35 notebook */
				asus_hides_smbus = 1;
		}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x0058: /* Compaq Evo N620c */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
			switch (dev->subsystem_device) {
			case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
				/* Motherboard doesn't have Host bridge
				 * subvendor/subdevice IDs, therefore checking
				 * its on-board VGA controller */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
			switch (dev->subsystem_device) {
			case 0x00b8: /* Compaq Evo D510 CMT */
			case 0x00b9: /* Compaq Evo D510 SFF */
			case 0x00ba: /* Compaq Evo D510 USDT */
				/* Motherboard doesn't have Host bridge
				 * subvendor/subdevice IDs and on-board VGA
				 * controller is disabled if an AGP card is
				 * inserted, therefore checking USB UHCI
				 * Controller #1 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
			switch (dev->subsystem_device) {
			case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
				/* Motherboard doesn't have host bridge
				 * subvendor/subdevice IDs, therefore checking
				 * its on-board VGA controller */
				asus_hides_smbus = 1;
			}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845G_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82850_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82865_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82875_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_7205_0,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7501_MCH,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855PM_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82810_IG3,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_2,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82815_CGC,	asus_hides_smbus_hostbridge);

static void asus_hides_smbus_lpc(struct pci_dev *dev)
{
	u16 val;

	if (likely(!asus_hides_smbus))
		return;

	pci_read_config_word(dev, 0xF2, &val);
	if (val & 0x8) {
		pci_write_config_word(dev, 0xF2, val & (~0x8));
		pci_read_config_word(dev, 0xF2, &val);
		if (val & 0x8)
			pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
				 val);
		else
			pci_info(dev, "Enabled i801 SMBus device\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);

/* It appears we just have one such device. If not, we have a warning */
static void __iomem *asus_rcba_base;
static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
{
	u32 rcba;

	if (likely(!asus_hides_smbus))
		return;
	WARN_ON(asus_rcba_base);

	pci_read_config_dword(dev, 0xF0, &rcba);
	/* use bits 31:14, 16 kB aligned */
	asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
	if (asus_rcba_base == NULL)
		return;
}

static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
{
	u32 val;

	if (likely(!asus_hides_smbus || !asus_rcba_base))
		return;

	/* read the Function Disable register, dword mode only */
	val = readl(asus_rcba_base + 0x3418);

	/* enable the SMBus device */
	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
}

static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
{
	if (likely(!asus_hides_smbus || !asus_rcba_base))
		return;

	iounmap(asus_rcba_base);
	asus_rcba_base = NULL;
	pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
}

static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
{
	asus_hides_smbus_lpc_ich6_suspend(dev);
	asus_hides_smbus_lpc_ich6_resume_early(dev);
	asus_hides_smbus_lpc_ich6_resume(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6);
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_suspend);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume_early);

/* SiS 96x south bridge: BIOS typically hides SMBus device...  */
static void quirk_sis_96x_smbus(struct pci_dev *dev)
{
	u8 val = 0;
	pci_read_config_byte(dev, 0x77, &val);
	if (val & 0x10) {
		pci_info(dev, "Enabling SiS 96x SMBus\n");
		pci_write_config_byte(dev, 0x77, val & ~0x10);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);

/*
 * ... This is further complicated by the fact that some SiS96x south
 * bridges pretend to be 85C503/5513 instead.  In that case see if we
 * spotted a compatible north bridge to make sure.
 * (pci_find_device() doesn't work yet)
 *
 * We can also enable the sis96x bit in the discovery register..
 */
#define SIS_DETECT_REGISTER 0x40

static void quirk_sis_503(struct pci_dev *dev)
{
	u8 reg;
	u16 devid;

	pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
	pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
	pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
	if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
		pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
		return;
	}

	/*
	 * Ok, it now shows up as a 96x.  Run the 96x quirk by hand in case
	 * it has already been processed.  (Depends on link order, which is
	 * apparently not guaranteed)
	 */
	dev->device = devid;
	quirk_sis_96x_smbus(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);

/*
 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
 * and MC97 modem controller are disabled when a second PCI soundcard is
 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
 * -- bjd
 */
static void asus_hides_ac97_lpc(struct pci_dev *dev)
{
	u8 val;
	int asus_hides_ac97 = 0;

	if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
		if (dev->device == PCI_DEVICE_ID_VIA_8237)
			asus_hides_ac97 = 1;
	}

	if (!asus_hides_ac97)
		return;

	pci_read_config_byte(dev, 0x50, &val);
	if (val & 0xc0) {
		pci_write_config_byte(dev, 0x50, val & (~0xc0));
		pci_read_config_byte(dev, 0x50, &val);
		if (val & 0xc0)
			pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
				 val);
		else
			pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);

#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)

/*
 * If we are using libata we can drive this chip properly but must do this
 * early on to make the additional device appear during the PCI scanning.
 */
static void quirk_jmicron_ata(struct pci_dev *pdev)
{
	u32 conf1, conf5, class;
	u8 hdr;

	/* Only poke fn 0 */
	if (PCI_FUNC(pdev->devfn))
		return;

	pci_read_config_dword(pdev, 0x40, &conf1);
	pci_read_config_dword(pdev, 0x80, &conf5);

	conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
	conf5 &= ~(1 << 24);  /* Clear bit 24 */

	switch (pdev->device) {
	case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
	case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
	case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
		/* The controller should be in single function ahci mode */
		conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
		break;

	case PCI_DEVICE_ID_JMICRON_JMB365:
	case PCI_DEVICE_ID_JMICRON_JMB366:
		/* Redirect IDE second PATA port to the right spot */
		conf5 |= (1 << 24);
		/* Fall through */
	case PCI_DEVICE_ID_JMICRON_JMB361:
	case PCI_DEVICE_ID_JMICRON_JMB363:
	case PCI_DEVICE_ID_JMICRON_JMB369:
		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
		/* Set the class codes correctly and then direct IDE 0 */
		conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
		break;

	case PCI_DEVICE_ID_JMICRON_JMB368:
		/* The controller should be in single function IDE mode */
		conf1 |= 0x00C00000; /* Set 22, 23 */
		break;
	}

	pci_write_config_dword(pdev, 0x40, conf1);
	pci_write_config_dword(pdev, 0x80, conf5);

	/* Update pdev accordingly */
	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
	pdev->hdr_type = hdr & 0x7f;
	pdev->multifunction = !!(hdr & 0x80);

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
	pdev->class = class >> 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);

#endif

static void quirk_jmicron_async_suspend(struct pci_dev *dev)
{
	if (dev->multifunction) {
		device_disable_async_suspend(&dev->dev);
		pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
	}
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);

#ifdef CONFIG_X86_IO_APIC
static void quirk_alder_ioapic(struct pci_dev *pdev)
{
	int i;

	if ((pdev->class >> 8) != 0xff00)
		return;

	/*
	 * The first BAR is the location of the IO-APIC... we must
	 * not touch this (and it's already covered by the fixmap), so
	 * forcibly insert it into the resource tree.
	 */
	if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
		insert_resource(&iomem_resource, &pdev->resource[0]);

	/*
	 * The next five BARs all seem to be rubbish, so just clean
	 * them out.
	 */
	for (i = 1; i < 6; i++)
		memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_EESSC,	quirk_alder_ioapic);
#endif

static void quirk_pcie_mch(struct pci_dev *pdev)
{
	pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7520_MCH,	quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7320_MCH,	quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7525_MCH,	quirk_pcie_mch);

DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);

/*
 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
 * together on certain PXH-based systems.
 */
static void quirk_pcie_pxh(struct pci_dev *dev)
{
	dev->no_msi = 1;
	pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_0,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_1,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_pcie_pxh);

/*
 * Some Intel PCI Express chipsets have trouble with downstream device
 * power management.
 */
static void quirk_intel_pcie_pm(struct pci_dev *dev)
{
	pci_pm_d3_delay = 120;
	dev->no_d1d2 = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e2, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e3, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e4, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e5, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e6, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e7, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f7, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f8, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f9, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25fa, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2601, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2602, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2603, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2604, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2605, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2606, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2607, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2608, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);

static void quirk_radeon_pm(struct pci_dev *dev)
{
	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
	    dev->subsystem_device == 0x00e2) {
		if (dev->d3_delay < 20) {
			dev->d3_delay = 20;
			pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
				 dev->d3_delay);
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);

#ifdef CONFIG_X86_IO_APIC
static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
{
	noioapicreroute = 1;
	pr_info("%s detected: disable boot interrupt reroute\n", d->ident);

	return 0;
}

static const struct dmi_system_id boot_interrupt_dmi_table[] = {
	/*
	 * Systems to exclude from boot interrupt reroute quirks
	 */
	{
		.callback = dmi_disable_ioapicreroute,
		.ident = "ASUSTek Computer INC. M2N-LR",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
			DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
		},
	},
	{}
};

/*
 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
 * remap the original interrupt in the Linux kernel to the boot interrupt, so
 * that a PCI device's interrupt handler is installed on the boot interrupt
 * line instead.
 */
static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
{
	dmi_check_system(boot_interrupt_dmi_table);
	if (noioapicquirk || noioapicreroute)
		return;

	dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
	pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);

/*
 * On some chipsets we can disable the generation of legacy INTx boot
 * interrupts.
 */

/*
 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
 * 300641-004US, section 5.7.3.
 */
#define INTEL_6300_IOAPIC_ABAR		0x40
#define INTEL_6300_DISABLE_BOOT_IRQ	(1<<14)

static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
{
	u16 pci_config_word;

	if (noioapicquirk)
		return;

	pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
	pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
	pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,	quirk_disable_intel_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,	quirk_disable_intel_boot_interrupt);

/* Disable boot interrupts on HT-1000 */
#define BC_HT1000_FEATURE_REG		0x64
#define BC_HT1000_PIC_REGS_ENABLE	(1<<0)
#define BC_HT1000_MAP_IDX		0xC00
#define BC_HT1000_MAP_DATA		0xC01

static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
{
	u32 pci_config_dword;
	u8 irq;

	if (noioapicquirk)
		return;

	pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
			BC_HT1000_PIC_REGS_ENABLE);

	for (irq = 0x10; irq < 0x10 + 32; irq++) {
		outb(irq, BC_HT1000_MAP_IDX);
		outb(0x00, BC_HT1000_MAP_DATA);
	}

	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);

/* Disable boot interrupts on AMD and ATI chipsets */

/*
 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
 * (due to an erratum).
 */
#define AMD_813X_MISC			0x40
#define AMD_813X_NOIOAMODE		(1<<0)
#define AMD_813X_REV_B1			0x12
#define AMD_813X_REV_B2			0x13

static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
{
	u32 pci_config_dword;

	if (noioapicquirk)
		return;
	if ((dev->revision == AMD_813X_REV_B1) ||
	    (dev->revision == AMD_813X_REV_B2))
		return;

	pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
	pci_config_dword &= ~AMD_813X_NOIOAMODE;
	pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);

#define AMD_8111_PCI_IRQ_ROUTING	0x56

static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
{
	u16 pci_config_word;

	if (noioapicquirk)
		return;

	pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
	if (!pci_config_word) {
		pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
			 dev->vendor, dev->device);
		return;
	}
	pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
#endif /* CONFIG_X86_IO_APIC */

/*
 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
 * Re-allocate the region if needed...
 */
static void quirk_tc86c001_ide(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[0];

	if (r->start & 0x8) {
		r->flags |= IORESOURCE_UNSET;
		r->start = 0;
		r->end = 0xf;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
			 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
			 quirk_tc86c001_ide);

/*
 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
 * being read correctly if bit 7 of the base address is set.
 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
 * Re-allocate the regions to a 256-byte boundary if necessary.
 */
static void quirk_plx_pci9050(struct pci_dev *dev)
{
	unsigned int bar;

	/* Fixed in revision 2 (PCI 9052). */
	if (dev->revision >= 2)
		return;
	for (bar = 0; bar <= 1; bar++)
		if (pci_resource_len(dev, bar) == 0x80 &&
		    (pci_resource_start(dev, bar) & 0x80)) {
			struct resource *r = &dev->resource[bar];
			pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
				 bar);
			r->flags |= IORESOURCE_UNSET;
			r->start = 0;
			r->end = 0xff;
		}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
			 quirk_plx_pci9050);
/*
 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
 *
 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
 * driver.
 */
DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);

static void quirk_netmos(struct pci_dev *dev)
{
	unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
	unsigned int num_serial = dev->subsystem_device & 0xf;

	/*
	 * These Netmos parts are multiport serial devices with optional
	 * parallel ports.  Even when parallel ports are present, they
	 * are identified as class SERIAL, which means the serial driver
	 * will claim them.  To prevent this, mark them as class OTHER.
	 * These combo devices should be claimed by parport_serial.
	 *
	 * The subdevice ID is of the form 0x00PS, where <P> is the number
	 * of parallel ports and <S> is the number of serial ports.
	 */
	switch (dev->device) {
	case PCI_DEVICE_ID_NETMOS_9835:
		/* Well, this rule doesn't hold for the following 9835 device */
		if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
				dev->subsystem_device == 0x0299)
			return;
		/* else: fall through */
	case PCI_DEVICE_ID_NETMOS_9735:
	case PCI_DEVICE_ID_NETMOS_9745:
	case PCI_DEVICE_ID_NETMOS_9845:
	case PCI_DEVICE_ID_NETMOS_9855:
		if (num_parallel) {
			pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
				dev->device, num_parallel, num_serial);
			dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
			    (dev->class & 0xff);
		}
	}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
			 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);

static void quirk_e100_interrupt(struct pci_dev *dev)
{
	u16 command, pmcsr;
	u8 __iomem *csr;
	u8 cmd_hi;

	switch (dev->device) {
	/* PCI IDs taken from drivers/net/e100.c */
	case 0x1029:
	case 0x1030 ... 0x1034:
	case 0x1038 ... 0x103E:
	case 0x1050 ... 0x1057:
	case 0x1059:
	case 0x1064 ... 0x106B:
	case 0x1091 ... 0x1095:
	case 0x1209:
	case 0x1229:
	case 0x2449:
	case 0x2459:
	case 0x245D:
	case 0x27DC:
		break;
	default:
		return;
	}

	/*
	 * Some firmware hands off the e100 with interrupts enabled,
	 * which can cause a flood of interrupts if packets are
	 * received before the driver attaches to the device.  So
	 * disable all e100 interrupts here.  The driver will
	 * re-enable them when it's ready.
	 */
	pci_read_config_word(dev, PCI_COMMAND, &command);

	if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
		return;

	/*
	 * Check that the device is in the D0 power state. If it's not,
	 * there is no point to look any further.
	 */
	if (dev->pm_cap) {
		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
			return;
	}

	/* Convert from PCI bus to resource space.  */
	csr = ioremap(pci_resource_start(dev, 0), 8);
	if (!csr) {
		pci_warn(dev, "Can't map e100 registers\n");
		return;
	}

	cmd_hi = readb(csr + 3);
	if (cmd_hi == 0) {
		pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
		writeb(1, csr + 3);
	}

	iounmap(csr);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);

/*
 * The 82575 and 82598 may experience data corruption issues when transitioning
 * out of L0S.  To prevent this we need to disable L0S on the PCIe link.
 */
static void quirk_disable_aspm_l0s(struct pci_dev *dev)
{
	pci_info(dev, "Disabling L0s\n");
	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);

/*
 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
 * Link bit cleared after starting the link retrain process to allow this
 * process to finish.
 *
 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130.  See also the
 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
 */
static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
{
	dev->clear_retrain_link = 1;
	pci_info(dev, "Enable PCIe Retrain Link quirk\n");
}
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);

static void fixup_rev1_53c810(struct pci_dev *dev)
{
	u32 class = dev->class;

	/*
	 * rev 1 ncr53c810 chips don't set the class at all which means
	 * they don't get their resources remapped. Fix that here.
	 */
	if (class)
		return;

	dev->class = PCI_CLASS_STORAGE_SCSI << 8;
	pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
		 class, dev->class);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);

/* Enable 1k I/O space granularity on the Intel P64H2 */
static void quirk_p64h2_1k_io(struct pci_dev *dev)
{
	u16 en1k;

	pci_read_config_word(dev, 0x40, &en1k);

	if (en1k & 0x200) {
		pci_info(dev, "Enable I/O Space to 1KB granularity\n");
		dev->io_window_1k = 1;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);

/*
 * Under some circumstances, AER is not linked with extended capabilities.
 * Force it to be linked by setting the corresponding control bit in the
 * config space.
 */
static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
{
	uint8_t b;

	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
		if (!(b & 0x20)) {
			pci_write_config_byte(dev, 0xf41, b | 0x20);
			pci_info(dev, "Linking AER extended capability\n");
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_pcie_aer_ext_cap);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_pcie_aer_ext_cap);

static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
{
	/*
	 * Disable PCI Bus Parking and PCI Master read caching on CX700
	 * which causes unspecified timing errors with a VT6212L on the PCI
	 * bus leading to USB2.0 packet loss.
	 *
	 * This quirk is only enabled if a second (on the external PCI bus)
	 * VT6212L is found -- the CX700 core itself also contains a USB
	 * host controller with the same PCI ID as the VT6212L.
	 */

	/* Count VT6212L instances */
	struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
		PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
	uint8_t b;

	/*
	 * p should contain the first (internal) VT6212L -- see if we have
	 * an external one by searching again.
	 */
	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
	if (!p)
		return;
	pci_dev_put(p);

	if (pci_read_config_byte(dev, 0x76, &b) == 0) {
		if (b & 0x40) {
			/* Turn off PCI Bus Parking */
			pci_write_config_byte(dev, 0x76, b ^ 0x40);

			pci_info(dev, "Disabling VIA CX700 PCI parking\n");
		}
	}

	if (pci_read_config_byte(dev, 0x72, &b) == 0) {
		if (b != 0) {
			/* Turn off PCI Master read caching */
			pci_write_config_byte(dev, 0x72, 0x0);

			/* Set PCI Master Bus time-out to "1x16 PCLK" */
			pci_write_config_byte(dev, 0x75, 0x1);

			/* Disable "Read FIFO Timer" */
			pci_write_config_byte(dev, 0x77, 0x0);

			pci_info(dev, "Disabling VIA CX700 PCI caching\n");
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);

static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
{
	u32 rev;

	pci_read_config_dword(dev, 0xf4, &rev);

	/* Only CAP the MRRS if the device is a 5719 A0 */
	if (rev == 0x05719000) {
		int readrq = pcie_get_readrq(dev);
		if (readrq > 2048)
			pcie_set_readrq(dev, 2048);
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
			 PCI_DEVICE_ID_TIGON3_5719,
			 quirk_brcm_5719_limit_mrrs);

#ifdef CONFIG_PCIE_IPROC_PLATFORM
static void quirk_paxc_bridge(struct pci_dev *pdev)
{
	/*
	 * The PCI config space is shared with the PAXC root port and the first
	 * Ethernet device.  So, we need to workaround this by telling the PCI
	 * code that the bridge is not an Ethernet device.
	 */
	if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
		pdev->class = PCI_CLASS_BRIDGE_PCI << 8;

	/*
	 * MPSS is not being set properly (as it is currently 0).  This is
	 * because that area of the PCI config space is hard coded to zero, and
	 * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)
	 * so that the MPS can be set to the real max value.
	 */
	pdev->pcie_mpss = 2;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
#endif

/*
 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
 * hide device 6 which configures the overflow device access containing the
 * DRBs - this is where we expose device 6.
 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
 */
static void quirk_unhide_mch_dev6(struct pci_dev *dev)
{
	u8 reg;

	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
		pci_info(dev, "Enabling MCH 'Overflow' Device\n");
		pci_write_config_byte(dev, 0xF4, reg | 0x02);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
			quirk_unhide_mch_dev6);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
			quirk_unhide_mch_dev6);

#ifdef CONFIG_PCI_MSI
/*
 * Some chipsets do not support MSI. We cannot easily rely on setting
 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
 * other buses controlled by the chipset even if Linux is not aware of it.
 * Instead of setting the flag on all buses in the machine, simply disable
 * MSI globally.
 */
static void quirk_disable_all_msi(struct pci_dev *dev)
{
	pci_no_msi();
	pci_warn(dev, "MSI quirk detected; MSI disabled\n");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);

/* Disable MSI on chipsets that are known to not support it */
static void quirk_disable_msi(struct pci_dev *dev)
{
	if (dev->subordinate) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);

/*
 * The APC bridge device in AMD 780 family northbridges has some random
 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
 * we use the possible vendor/device IDs of the host bridge for the
 * declared quirk, and search for the APC bridge by slot number.
 */
static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
{
	struct pci_dev *apc_bridge;

	apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
	if (apc_bridge) {
		if (apc_bridge->device == 0x9602)
			quirk_disable_msi(apc_bridge);
		pci_dev_put(apc_bridge);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);

/*
 * Go through the list of HyperTransport capabilities and return 1 if a HT
 * MSI capability is found and enabled.
 */
static int msi_ht_cap_enabled(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Found %s HT MSI Mapping\n",
				flags & HT_MSI_FLAGS_ENABLE ?
				"enabled" : "disabled");
			return (flags & HT_MSI_FLAGS_ENABLE) != 0;
		}

		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
	return 0;
}

/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
static void quirk_msi_ht_cap(struct pci_dev *dev)
{
	if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
			quirk_msi_ht_cap);

/*
 * The nVidia CK804 chipset may have 2 HT MSI mappings.  MSI is supported
 * if the MSI capability is set in any of these mappings.
 */
static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
{
	struct pci_dev *pdev;

	if (!dev->subordinate)
		return;

	/*
	 * Check HT MSI cap on this chipset and the root one.  A single one
	 * having MSI is enough to be sure that MSI is supported.
	 */
	pdev = pci_get_slot(dev->bus, 0);
	if (!pdev)
		return;
	if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
	pci_dev_put(pdev);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_msi_ht_cap);

/* Force enable MSI mapping capability on HT bridges */
static void ht_enable_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Enabling HT MSI Mapping\n");

			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
					      flags | HT_MSI_FLAGS_ENABLE);
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
			 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
			 ht_enable_msi_mapping);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
			 ht_enable_msi_mapping);

/*
 * The P5N32-SLI motherboards from Asus have a problem with MSI
 * for the MCP55 NIC. It is not yet determined whether the MSI problem
 * also affects other devices. As for now, turn off MSI for this device.
 */
static void nvenet_msi_disable(struct pci_dev *dev)
{
	const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);

	if (board_name &&
	    (strstr(board_name, "P5N32-SLI PREMIUM") ||
	     strstr(board_name, "P5N32-E SLI"))) {
		pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
		dev->no_msi = 1;
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_NVENET_15,
			nvenet_msi_disable);

/*
 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
 * config register.  This register controls the routing of legacy
 * interrupts from devices that route through the MCP55.  If this register
 * is misprogrammed, interrupts are only sent to the BSP, unlike
 * conventional systems where the IRQ is broadcast to all online CPUs.  Not
 * having this register set properly prevents kdump from booting up
 * properly, so let's make sure that we have it set correctly.
 * Note that this is an undocumented register.
 */
static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
{
	u32 cfg;

	if (!pci_find_capability(dev, PCI_CAP_ID_HT))
		return;

	pci_read_config_dword(dev, 0x74, &cfg);

	if (cfg & ((1 << 2) | (1 << 15))) {
		printk(KERN_INFO "Rewriting IRQ routing register on MCP55\n");
		cfg &= ~((1 << 2) | (1 << 15));
		pci_write_config_dword(dev, 0x74, cfg);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
			nvbridge_check_legacy_irq_routing);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
			nvbridge_check_legacy_irq_routing);

static int ht_check_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;
	int found = 0;

	/* Check if there is HT MSI cap or enabled on this device */
	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (found < 1)
			found = 1;
		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			if (flags & HT_MSI_FLAGS_ENABLE) {
				if (found < 2) {
					found = 2;
					break;
				}
			}
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}

	return found;
}

static int host_bridge_with_leaf(struct pci_dev *host_bridge)
{
	struct pci_dev *dev;
	int pos;
	int i, dev_no;
	int found = 0;

	dev_no = host_bridge->devfn >> 3;
	for (i = dev_no + 1; i < 0x20; i++) {
		dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
		if (!dev)
			continue;

		/* found next host bridge? */
		pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
		if (pos != 0) {
			pci_dev_put(dev);
			break;
		}

		if (ht_check_msi_mapping(dev)) {
			found = 1;
			pci_dev_put(dev);
			break;
		}
		pci_dev_put(dev);
	}

	return found;
}

#define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
#define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */

static int is_end_of_ht_chain(struct pci_dev *dev)
{
	int pos, ctrl_off;
	int end = 0;
	u16 flags, ctrl;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);

	if (!pos)
		goto out;

	pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);

	ctrl_off = ((flags >> 10) & 1) ?
			PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
	pci_read_config_word(dev, pos + ctrl_off, &ctrl);

	if (ctrl & (1 << 6))
		end = 1;

out:
	return end;
}

static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
	struct pci_dev *host_bridge;
	int pos;
	int i, dev_no;
	int found = 0;

	dev_no = dev->devfn >> 3;
	for (i = dev_no; i >= 0; i--) {
		host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
		if (!host_bridge)
			continue;

		pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
		if (pos != 0) {
			found = 1;
			break;
		}
		pci_dev_put(host_bridge);
	}

	if (!found)
		return;

	/* don't enable end_device/host_bridge with leaf directly here */
	if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
	    host_bridge_with_leaf(host_bridge))
		goto out;

	/* root did that ! */
	if (msi_ht_cap_enabled(host_bridge))
		goto out;

	ht_enable_msi_mapping(dev);

out:
	pci_dev_put(host_bridge);
}

static void ht_disable_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Disabling HT MSI Mapping\n");

			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
					      flags & ~HT_MSI_FLAGS_ENABLE);
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
}

static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
{
	struct pci_dev *host_bridge;
	int pos;
	int found;

	if (!pci_msi_enabled())
		return;

	/* check if there is HT MSI cap or enabled on this device */
	found = ht_check_msi_mapping(dev);

	/* no HT MSI CAP */
	if (found == 0)
		return;

	/*
	 * HT MSI mapping should be disabled on devices that are below
	 * a non-Hypertransport host bridge. Locate the host bridge...
	 */
	host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
						  PCI_DEVFN(0, 0));
	if (host_bridge == NULL) {
		pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
		return;
	}

	pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
	if (pos != 0) {
		/* Host bridge is to HT */
		if (found == 1) {
			/* it is not enabled, try to enable it */
			if (all)
				ht_enable_msi_mapping(dev);
			else
				nv_ht_enable_msi_mapping(dev);
		}
		goto out;
	}

	/* HT MSI is not enabled */
	if (found == 1)
		goto out;

	/* Host bridge is not to HT, disable HT MSI mapping on this device */
	ht_disable_msi_mapping(dev);

out:
	pci_dev_put(host_bridge);
}

static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
{
	return __nv_msi_ht_cap_quirk(dev, 1);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);

static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
{
	return __nv_msi_ht_cap_quirk(dev, 0);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);

static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
}

static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
{
	struct pci_dev *p;

	/*
	 * SB700 MSI issue will be fixed at HW level from revision A21;
	 * we need check PCI REVISION ID of SMBus controller to get SB700
	 * revision.
	 */
	p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
			   NULL);
	if (!p)
		return;

	if ((p->revision < 0x3B) && (p->revision >= 0x30))
		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
	pci_dev_put(p);
}

static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
{
	/* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
	if (dev->revision < 0x18) {
		pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5780,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5780S,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5714,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5714S,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5715,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5715S,
			quirk_msi_intx_disable_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
			quirk_msi_intx_disable_ati_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
			quirk_msi_intx_disable_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
			quirk_msi_intx_disable_qca_bug);
#endif /* CONFIG_PCI_MSI */

/*
 * Allow manual resource allocation for PCI hotplug bridges via
 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
 * allocate resources when hotplug device is inserted and PCI bus is
 * rescanned.
 */
static void quirk_hotplug_bridge(struct pci_dev *dev)
{
	dev->is_hotplug_bridge = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);

/*
 * This is a quirk for the Ricoh MMC controller found as a part of some
 * multifunction chips.
 *
 * This is very similar and based on the ricoh_mmc driver written by
 * Philip Langdale. Thank you for these magic sequences.
 *
 * These chips implement the four main memory card controllers (SD, MMC,
 * MS, xD) and one or both of CardBus or FireWire.
 *
 * It happens that they implement SD and MMC support as separate
 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
 * cards but the chip detects MMC cards in hardware and directs them to the
 * MMC controller - so the SDHCI driver never sees them.
 *
 * To get around this, we must disable the useless MMC controller.  At that
 * point, the SDHCI controller will start seeing them.  It seems to be the
 * case that the relevant PCI registers to deactivate the MMC controller
 * live on PCI function 0, which might be the CardBus controller or the
 * FireWire controller, depending on the particular chip in question
 *
 * This has to be done early, because as soon as we disable the MMC controller
 * other PCI functions shift up one level, e.g. function #2 becomes function
 * #1, and this will confuse the PCI core.
 */
#ifdef CONFIG_MMC_RICOH_MMC
-static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
-{
-       u8 write_enable;
-       u8 write_target;
-       u8 disable;
-
-       /*
-        * Disable via CardBus interface
-        *
-        * This must be done via function #0
-        */
-       if (PCI_FUNC(dev->devfn))
-               return;
-
-       pci_read_config_byte(dev, 0xB7, &disable);
-       if (disable & 0x02)
-               return;
-
-       pci_read_config_byte(dev, 0x8E, &write_enable);
-       pci_write_config_byte(dev, 0x8E, 0xAA);
-       pci_read_config_byte(dev, 0x8D, &write_target);
-       pci_write_config_byte(dev, 0x8D, 0xB7);
-       pci_write_config_byte(dev, 0xB7, disable | 0x02);
-       pci_write_config_byte(dev, 0x8E, write_enable);
-       pci_write_config_byte(dev, 0x8D, write_target);
-
-       pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
-       pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
-}
-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
-
 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
 {
        u8 write_enable;

	/*
	 * Disable via FireWire interface
	 *
	 * This must be done via function #0
	 */
	if (PCI_FUNC(dev->devfn))
		return;
	/*
	 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
	 * certain types of SD/MMC cards. Lowering the SD base clock
	 * frequency from 200Mhz to 50Mhz fixes this issue.
	 *
	 * 0x150 - SD2.0 mode enable for changing base clock
	 *	   frequency to 50Mhz
	 * 0xe1  - Base clock frequency
	 * 0x32  - 50Mhz new clock frequency
	 * 0xf9  - Key register for 0x150
	 * 0xfc  - key register for 0xe1
	 */
	if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
	    dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
		pci_write_config_byte(dev, 0xf9, 0xfc);
		pci_write_config_byte(dev, 0x150, 0x10);
		pci_write_config_byte(dev, 0xf9, 0x00);
		pci_write_config_byte(dev, 0xfc, 0x01);
		pci_write_config_byte(dev, 0xe1, 0x32);
		pci_write_config_byte(dev, 0xfc, 0x00);

		pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
	}

	pci_read_config_byte(dev, 0xCB, &disable);

	if (disable & 0x02)
		return;

	pci_read_config_byte(dev, 0xCA, &write_enable);
	pci_write_config_byte(dev, 0xCA, 0x57);
	pci_write_config_byte(dev, 0xCB, disable | 0x02);
	pci_write_config_byte(dev, 0xCA, write_enable);

	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
	pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");

}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
#endif /*CONFIG_MMC_RICOH_MMC*/

#ifdef CONFIG_DMAR_TABLE
#define VTUNCERRMSK_REG	0x1ac
#define VTD_MSK_SPEC_ERRORS	(1 << 31)
/*
 * This is a quirk for masking VT-d spec-defined errors to platform error
 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
 * on the RAS config settings of the platform) when a VT-d fault happens.
 * The resulting SMI caused the system to hang.
 *
 * VT-d spec-related errors are already handled by the VT-d OS code, so no
 * need to report the same error through other channels.
 */
static void vtd_mask_spec_errors(struct pci_dev *dev)
{
	u32 word;

	pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
	pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
#endif

static void fixup_ti816x_class(struct pci_dev *dev)
{
	u32 class = dev->class;

	/* TI 816x devices do not have class code set when in PCIe boot mode */
	dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
	pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
		 class, dev->class);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
			      PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);

/*
 * Some PCIe devices do not work reliably with the claimed maximum
 * payload size supported.
 */
static void fixup_mpss_256(struct pci_dev *dev)
{
	dev->pcie_mpss = 1; /* 256 bytes */
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);

/*
 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
 * Since there is no way of knowing what the PCIe MPS on each fabric will be
 * until all of the devices are discovered and buses walked, read completion
 * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
 * it is possible to hotplug a device with MPS of 256B.
 */
static void quirk_intel_mc_errata(struct pci_dev *dev)
{
	int err;
	u16 rcc;

	if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
	    pcie_bus_config == PCIE_BUS_DEFAULT)
		return;

	/*
	 * Intel erratum specifies bits to change but does not say what
	 * they are.  Keeping them magical until such time as the registers
	 * and values can be explained.
	 */
	err = pci_read_config_word(dev, 0x48, &rcc);
	if (err) {
		pci_err(dev, "Error attempting to read the read completion coalescing register\n");
		return;
	}

	if (!(rcc & (1 << 10)))
		return;

	rcc &= ~(1 << 10);

	err = pci_write_config_word(dev, 0x48, rcc);
	if (err) {
		pci_err(dev, "Error attempting to write the read completion coalescing register\n");
		return;
	}

	pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
}
/* Intel 5000 series memory controllers and ports 2-7 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
/* Intel 5100 series memory controllers and ports 2-7 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);

/*
 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
 * To work around this, query the size it should be configured to by the
 * device and modify the resource end to correspond to this new size.
 */
static void quirk_intel_ntb(struct pci_dev *dev)
{
	int rc;
	u8 val;

	rc = pci_read_config_byte(dev, 0x00D0, &val);
	if (rc)
		return;

	dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;

	rc = pci_read_config_byte(dev, 0x00D1, &val);
	if (rc)
		return;

	dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);

/*
 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
 * though no one is handling them (e.g., if the i915 driver is never
 * loaded).  Additionally the interrupt destination is not set up properly
 * and the interrupt ends up -somewhere-.
 *
 * These spurious interrupts are "sticky" and the kernel disables the
 * (shared) interrupt line after 100,000+ generated interrupts.
 *
 * Fix it by disabling the still enabled interrupts.  This resolves crashes
 * often seen on monitor unplug.
 */
#define I915_DEIER_REG 0x4400c
static void disable_igfx_irq(struct pci_dev *dev)
{
	void __iomem *regs = pci_iomap(dev, 0, 0);
	if (regs == NULL) {
		pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
		return;
	}

	/* Check if any interrupt line is still enabled */
	if (readl(regs + I915_DEIER_REG) != 0) {
		pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");

		writel(0, regs + I915_DEIER_REG);
	}

	pci_iounmap(dev, regs);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);

/*
 * PCI devices which are on Intel chips can skip the 10ms delay
 * before entering D3 mode.
 */
static void quirk_remove_d3_delay(struct pci_dev *dev)
{
	dev->d3_delay = 0;
}
/* C600 Series devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
/* Intel Cherrytrail devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);

/*
 * Some devices may pass our check in pci_intx_mask_supported() if
 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
 * support this feature.
 */
static void quirk_broken_intx_masking(struct pci_dev *dev)
{
	dev->broken_intx_masking = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
			quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
			quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
			quirk_broken_intx_masking);

/*
 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
 *
 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
			quirk_broken_intx_masking);

/*
 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
 * DisINTx can be set but the interrupt status bit is non-functional.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);

static u16 mellanox_broken_intx_devs[] = {
	PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
	PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
	PCI_DEVICE_ID_MELLANOX_HERMON_EN,
	PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX3,
	PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
};

#define CONNECTX_4_CURR_MAX_MINOR 99
#define CONNECTX_4_INTX_SUPPORT_MINOR 14

/*
 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
 * If so, don't mark it as broken.
 * FW minor > 99 means older FW version format and no INTx masking support.
 * FW minor < 14 means new FW version format and no INTx masking support.
 */
static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
{
	__be32 __iomem *fw_ver;
	u16 fw_major;
	u16 fw_minor;
	u16 fw_subminor;
	u32 fw_maj_min;
	u32 fw_sub_min;
	int i;

	for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
		if (pdev->device == mellanox_broken_intx_devs[i]) {
			pdev->broken_intx_masking = 1;
			return;
		}
	}

	/*
	 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
	 * support so shouldn't be checked further
	 */
	if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
		return;

	if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
	    pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
		return;

	/* For ConnectX-4 and ConnectX-4LX, need to check FW support */
	if (pci_enable_device_mem(pdev)) {
		pci_warn(pdev, "Can't enable device memory\n");
		return;
	}

	fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
	if (!fw_ver) {
		pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
		goto out;
	}

	/* Reading from resource space should be 32b aligned */
	fw_maj_min = ioread32be(fw_ver);
	fw_sub_min = ioread32be(fw_ver + 1);
	fw_major = fw_maj_min & 0xffff;
	fw_minor = fw_maj_min >> 16;
	fw_subminor = fw_sub_min & 0xffff;
	if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
	    fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
		pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
			 fw_major, fw_minor, fw_subminor, pdev->device ==
			 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
		pdev->broken_intx_masking = 1;
	}

	iounmap(fw_ver);

out:
	pci_disable_device(pdev);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
			mellanox_check_broken_intx_masking);

static void quirk_no_bus_reset(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
}

/*
 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
 * The device will throw a Link Down error on AER-capable systems and
 * regardless of AER, config space of the device is never accessible again
 * and typically causes the system to hang or reset when access is attempted.
 * http://www.spinics.net/lists/linux-pci/msg34797.html
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);

/*
 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
 * reset when used with certain child devices.  After the reset, config
 * accesses to the child may fail.
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);

static void quirk_no_pm_reset(struct pci_dev *dev)
{
	/*
	 * We can't do a bus reset on root bus devices, but an ineffective
	 * PM reset may be better than nothing.
	 */
	if (!pci_is_root_bus(dev->bus))
		dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
}

/*
 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
 * causes a reset (i.e., they advertise NoSoftRst-).  This transition seems
 * to have no effect on the device: it retains the framebuffer contents and
 * monitor sync.  Advertising this support makes other layers, like VFIO,
 * assume pci_reset_function() is viable for this device.  Mark it as
 * unavailable to skip it when testing reset methods.
 */
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
			       PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);

/*
 * Thunderbolt controllers with broken MSI hotplug signaling:
 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
 */
static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
{
	if (pdev->is_hotplug_bridge &&
	    (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
	     pdev->revision <= 1))
		pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
			quirk_thunderbolt_hotplug_msi);

#ifdef CONFIG_ACPI
/*
 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
 *
 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
 * shutdown before suspend. Otherwise the native host interface (NHI) will not
 * be present after resume if a device was plugged in before suspend.
 *
 * The Thunderbolt controller consists of a PCIe switch with downstream
 * bridges leading to the NHI and to the tunnel PCI bridges.
 *
 * This quirk cuts power to the whole chip. Therefore we have to apply it
 * during suspend_noirq of the upstream bridge.
 *
 * Power is automagically restored before resume. No action is needed.
 */
static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
{
	acpi_handle bridge, SXIO, SXFP, SXLV;

	if (!x86_apple_machine)
		return;
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
		return;
	bridge = ACPI_HANDLE(&dev->dev);
	if (!bridge)
		return;

	/*
	 * SXIO and SXLV are present only on machines requiring this quirk.
	 * Thunderbolt bridges in external devices might have the same
	 * device ID as those on the host, but they will not have the
	 * associated ACPI methods. This implicitly checks that we are at
	 * the right bridge.
	 */
	if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
		return;
	pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");

	/* magic sequence */
	acpi_execute_simple_method(SXIO, NULL, 1);
	acpi_execute_simple_method(SXFP, NULL, 0);
	msleep(300);
	acpi_execute_simple_method(SXLV, NULL, 0);
	acpi_execute_simple_method(SXIO, NULL, 0);
	acpi_execute_simple_method(SXLV, NULL, 0);
}
DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			       quirk_apple_poweroff_thunderbolt);

/*
 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
 *
 * During suspend the Thunderbolt controller is reset and all PCI
 * tunnels are lost. The NHI driver will try to reestablish all tunnels
 * during resume. We have to manually wait for the NHI since there is
 * no parent child relationship between the NHI and the tunneled
 * bridges.
 */
static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
{
	struct pci_dev *sibling = NULL;
	struct pci_dev *nhi = NULL;

	if (!x86_apple_machine)
		return;
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
		return;

	/*
	 * Find the NHI and confirm that we are a bridge on the Thunderbolt
	 * host controller and not on a Thunderbolt endpoint.
	 */
	sibling = pci_get_slot(dev->bus, 0x0);
	if (sibling == dev)
		goto out; /* we are the downstream bridge to the NHI */
	if (!sibling || !sibling->subordinate)
		goto out;
	nhi = pci_get_slot(sibling->subordinate, 0x0);
	if (!nhi)
		goto out;
	if (nhi->vendor != PCI_VENDOR_ID_INTEL
		    || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
			nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
		    || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
		goto out;
	pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
	device_pm_wait_for_dev(&dev->dev, &nhi->dev);
out:
	pci_dev_put(nhi);
	pci_dev_put(sibling);
}
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
			       quirk_apple_wait_for_thunderbolt);
#endif

/*
 * Following are device-specific reset methods which can be used to
 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
 * not available.
 */
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
{
	/*
	 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
	 *
	 * The 82599 supports FLR on VFs, but FLR support is reported only
	 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
	 * Thus we must call pcie_flr() directly without first checking if it is
	 * supported.
	 */
	if (!probe)
		pcie_flr(dev);
	return 0;
}

#define SOUTH_CHICKEN2		0xc2004
#define PCH_PP_STATUS		0xc7200
#define PCH_PP_CONTROL		0xc7204
#define MSG_CTL			0x45010
#define NSDE_PWR_STATE		0xd0100
#define IGD_OPERATION_TIMEOUT	10000     /* set timeout 10 seconds */

static int reset_ivb_igd(struct pci_dev *dev, int probe)
{
	void __iomem *mmio_base;
	unsigned long timeout;
	u32 val;

	if (probe)
		return 0;

	mmio_base = pci_iomap(dev, 0, 0);
	if (!mmio_base)
		return -ENOMEM;

	iowrite32(0x00000002, mmio_base + MSG_CTL);

	/*
	 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
	 * driver loaded sets the right bits. However, this's a reset and
	 * the bits have been set by i915 previously, so we clobber
	 * SOUTH_CHICKEN2 register directly here.
	 */
	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);

	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
	iowrite32(val, mmio_base + PCH_PP_CONTROL);

	timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
	do {
		val = ioread32(mmio_base + PCH_PP_STATUS);
		if ((val & 0xb0000000) == 0)
			goto reset_complete;
		msleep(10);
	} while (time_before(jiffies, timeout));
	pci_warn(dev, "timeout during reset\n");

reset_complete:
	iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);

	pci_iounmap(dev, mmio_base);
	return 0;
}

/* Device-specific reset method for Chelsio T4-based adapters */
static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
{
	u16 old_command;
	u16 msix_flags;

	/*
	 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
	 * that we have no device-specific reset method.
	 */
	if ((dev->device & 0xf000) != 0x4000)
		return -ENOTTY;

	/*
	 * If this is the "probe" phase, return 0 indicating that we can
	 * reset this device.
	 */
	if (probe)
		return 0;

	/*
	 * T4 can wedge if there are DMAs in flight within the chip and Bus
	 * Master has been disabled.  We need to have it on till the Function
	 * Level Reset completes.  (BUS_MASTER is disabled in
	 * pci_reset_function()).
	 */
	pci_read_config_word(dev, PCI_COMMAND, &old_command);
	pci_write_config_word(dev, PCI_COMMAND,
			      old_command | PCI_COMMAND_MASTER);

	/*
	 * Perform the actual device function reset, saving and restoring
	 * configuration information around the reset.
	 */
	pci_save_state(dev);

	/*
	 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
	 * are disabled when an MSI-X interrupt message needs to be delivered.
	 * So we briefly re-enable MSI-X interrupts for the duration of the
	 * FLR.  The pci_restore_state() below will restore the original
	 * MSI-X state.
	 */
	pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
	if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
		pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
				      msix_flags |
				      PCI_MSIX_FLAGS_ENABLE |
				      PCI_MSIX_FLAGS_MASKALL);

	pcie_flr(dev);

	/*
	 * Restore the configuration information (BAR values, etc.) including
	 * the original PCI Configuration Space Command word, and return
	 * success.
	 */
	pci_restore_state(dev);
	pci_write_config_word(dev, PCI_COMMAND, old_command);
	return 0;
}

#define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
#define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166

/*
 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
 * FLR where config space reads from the device return -1.  We seem to be
 * able to avoid this condition if we disable the NVMe controller prior to
 * FLR.  This quirk is generic for any NVMe class device requiring similar
 * assistance to quiesce the device prior to FLR.
 *
 * NVMe specification: https://nvmexpress.org/resources/specifications/
 * Revision 1.0e:
 *    Chapter 2: Required and optional PCI config registers
 *    Chapter 3: NVMe control registers
 *    Chapter 7.3: Reset behavior
 */
static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
{
	void __iomem *bar;
	u16 cmd;
	u32 cfg;

	if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
	    !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
		return -ENOTTY;

	if (probe)
		return 0;

	bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
	if (!bar)
		return -ENOTTY;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);

	cfg = readl(bar + NVME_REG_CC);

	/* Disable controller if enabled */
	if (cfg & NVME_CC_ENABLE) {
		u32 cap = readl(bar + NVME_REG_CAP);
		unsigned long timeout;

		/*
		 * Per nvme_disable_ctrl() skip shutdown notification as it
		 * could complete commands to the admin queue.  We only intend
		 * to quiesce the device before reset.
		 */
		cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);

		writel(cfg, bar + NVME_REG_CC);

		/*
		 * Some controllers require an additional delay here, see
		 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY.  None of those are yet
		 * supported by this quirk.
		 */

		/* Cap register provides max timeout in 500ms increments */
		timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;

		for (;;) {
			u32 status = readl(bar + NVME_REG_CSTS);

			/* Ready status becomes zero on disable complete */
			if (!(status & NVME_CSTS_RDY))
				break;

			msleep(100);

			if (time_after(jiffies, timeout)) {
				pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
				break;
			}
		}
	}

	pci_iounmap(dev, bar);

	pcie_flr(dev);

	return 0;
}

/*
 * Intel DC P3700 NVMe controller will timeout waiting for ready status
 * to change after NVMe enable if the driver starts interacting with the
 * device too soon after FLR.  A 250ms delay after FLR has heuristically
 * proven to produce reliably working results for device assignment cases.
 */
static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
{
	if (!pcie_has_flr(dev))
		return -ENOTTY;

	if (probe)
		return 0;

	pcie_flr(dev);

	msleep(250);

	return 0;
}

static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
		 reset_intel_82599_sfp_virtfn },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
		reset_ivb_igd },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
		reset_ivb_igd },
	{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
	{ PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
		reset_chelsio_generic_dev },
	{ 0 }
};

/*
 * These device-specific reset methods are here rather than in a driver
 * because when a host assigns a device to a guest VM, the host may need
 * to reset the device but probably doesn't have a driver for it.
 */
int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	const struct pci_dev_reset_methods *i;

	for (i = pci_dev_reset_methods; i->reset; i++) {
		if ((i->vendor == dev->vendor ||
		     i->vendor == (u16)PCI_ANY_ID) &&
		    (i->device == dev->device ||
		     i->device == (u16)PCI_ANY_ID))
			return i->reset(dev, probe);
	}

	return -ENOTTY;
}

static void quirk_dma_func0_alias(struct pci_dev *dev)
{
	if (PCI_FUNC(dev->devfn) != 0)
		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
}

/*
 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
 *
 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);

static void quirk_dma_func1_alias(struct pci_dev *dev)
{
	if (PCI_FUNC(dev->devfn) != 1)
		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
}

/*
 * Marvell 88SE9123 uses function 1 as the requester ID for DMA.  In some
 * SKUs function 1 is present and is a legacy IDE controller, in other
 * SKUs this function is not present, making this a ghost requester.
 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
			 quirk_dma_func1_alias);
/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
			 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
			 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
			 quirk_dma_func1_alias);

/*
 * Some devices DMA with the wrong devfn, not just the wrong function.
 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
 * the alias is "fixed" and independent of the device devfn.
 *
 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
 * processor.  To software, this appears as a PCIe-to-PCI/X bridge with a
 * single device on the secondary bus.  In reality, the single exposed
 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
 * that provides a bridge to the internal bus of the I/O processor.  The
 * controller supports private devices, which can be hidden from PCI config
 * space.  In the case of the Adaptec 3405, a private device at 01.0
 * appears to be the DMA engine, which therefore needs to become a DMA
 * alias for the device.
 */
static const struct pci_device_id fixed_dma_alias_tbl[] = {
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
			 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
	  .driver_data = PCI_DEVFN(1, 0) },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
			 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
	  .driver_data = PCI_DEVFN(1, 0) },
	{ 0 }
};

static void quirk_fixed_dma_alias(struct pci_dev *dev)
{
	const struct pci_device_id *id;

	id = pci_match_id(fixed_dma_alias_tbl, dev);
	if (id)
		pci_add_dma_alias(dev, id->driver_data);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);

/*
 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
 * using the wrong DMA alias for the device.  Some of these devices can be
 * used as either forward or reverse bridges, so we need to test whether the
 * device is operating in the correct mode.  We could probably apply this
 * quirk to PCI_ANY_ID, but for now we'll just use known offenders.  The test
 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
 */
static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
{
	if (!pci_is_root_bus(pdev->bus) &&
	    pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
	    !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
	    pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
		pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
}
/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
			 quirk_use_pcie_bridge_dma_alias);
/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
/* ITE 8893 has the same problem as the 8892 */
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);

/*
 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
 * be added as aliases to the DMA device in order to allow buffer access
 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
 * programmed in the EEPROM.
 */
static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
{
	pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
	pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
	pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);

/*
 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
 * associated not at the root bus, but at a bridge below. This quirk avoids
 * generating invalid DMA aliases.
 */
static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
				quirk_bridge_cavm_thrx2_pcie_root);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
				quirk_bridge_cavm_thrx2_pcie_root);

/*
 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
 * class code.  Fix it.
 */
static void quirk_tw686x_class(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	/* Use "Multimedia controller" class */
	pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
	pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
		 class, pdev->class);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);

/*
 * Some devices have problems with Transaction Layer Packets with the Relaxed
 * Ordering Attribute set.  Such devices should mark themselves and other
 * device drivers should check before sending TLPs with RO set.
 */
static void quirk_relaxedordering_disable(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
	pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
}

/*
 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
 * Complex have a Flow Control Credit issue which can cause performance
 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
 */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);

/*
 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
 * where Upstream Transaction Layer Packets with the Relaxed Ordering
 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
 * set.  This is a violation of the PCIe 3.0 Transaction Ordering Rules
 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
 * November 10, 2010).  As a result, on this platform we can't use Relaxed
 * Ordering for Upstream TLPs.
 */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);

/*
 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
 * values for the Attribute as were supplied in the header of the
 * corresponding Request, except as explicitly allowed when IDO is used."
 *
 * If a non-compliant device generates a completion with a different
 * attribute than the request, the receiver may accept it (which itself
 * seems non-compliant based on sec 2.3.2), or it may handle it as a
 * Malformed TLP or an Unexpected Completion, which will probably lead to a
 * device access timeout.
 *
 * If the non-compliant device generates completions with zero attributes
 * (instead of copying the attributes from the request), we can work around
 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
 * upstream devices so they always generate requests with zero attributes.
 *
 * This affects other devices under the same Root Port, but since these
 * attributes are performance hints, there should be no functional problem.
 *
 * Note that Configuration Space accesses are never supposed to have TLP
 * Attributes, so we're safe waiting till after any Configuration Space
 * accesses to do the Root Port fixup.
 */
static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
{
	struct pci_dev *root_port = pci_find_pcie_root_port(pdev);

	if (!root_port) {
		pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
		return;
	}

	pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
		 dev_name(&pdev->dev));
	pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
					   PCI_EXP_DEVCTL_RELAX_EN |
					   PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
}

/*
 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
 * Completion it generates.
 */
static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
{
	/*
	 * This mask/compare operation selects for Physical Function 4 on a
	 * T5.  We only need to fix up the Root Port once for any of the
	 * PFs.  PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
	 * 0x54xx so we use that one.
	 */
	if ((pdev->device & 0xff00) == 0x5400)
		quirk_disable_root_port_attributes(pdev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
			 quirk_chelsio_T5_disable_root_port_attributes);

/*
 * AMD has indicated that the devices below do not support peer-to-peer
 * in any system where they are found in the southbridge with an AMD
 * IOMMU in the system.  Multifunction devices that do not support
 * peer-to-peer between functions can claim to support a subset of ACS.
 * Such devices effectively enable request redirect (RR) and completion
 * redirect (CR) since all transactions are redirected to the upstream
 * root complex.
 *
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
 *
 * 1002:4385 SBx00 SMBus Controller
 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
 * 1002:4383 SBx00 Azalia (Intel HDA)
 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
 * 1002:4384 SBx00 PCI to PCI Bridge
 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
 *
 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
 *
 * 1022:780f [AMD] FCH PCI Bridge
 * 1022:7809 [AMD] FCH USB OHCI Controller
 */
static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
{
#ifdef CONFIG_ACPI
	struct acpi_table_header *header = NULL;
	acpi_status status;

	/* Targeting multifunction devices on the SB (appears on root bus) */
	if (!dev->multifunction || !pci_is_root_bus(dev->bus))
		return -ENODEV;

	/* The IVRS table describes the AMD IOMMU */
	status = acpi_get_table("IVRS", 0, &header);
	if (ACPI_FAILURE(status))
		return -ENODEV;

	/* Filter out flags not applicable to multifunction */
	acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);

	return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
#else
	return -ENODEV;
#endif
}

static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
{
	/*
	 * Effectively selects all downstream ports for whole ThunderX 1
	 * family by 0xf800 mask (which represents 8 SoCs), while the lower
	 * bits of device ID are used to indicate which subdevice is used
	 * within the SoC.
	 */
	return (pci_is_pcie(dev) &&
		(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
		((dev->device & 0xf800) == 0xa000));
}

static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * Cavium root ports don't advertise an ACS capability.  However,
	 * the RTL internally implements similar protection as if ACS had
	 * Request Redirection, Completion Redirection, Source Validation,
	 * and Upstream Forwarding features enabled.  Assert that the
	 * hardware implements and enables equivalent ACS functionality for
	 * these flags.
	 */
	acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);

	if (!pci_quirk_cavium_acs_match(dev))
		return -ENOTTY;

	return acs_flags ? 0 : 1;
}

static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
	 * transactions with others, allowing masking out these bits as if they
	 * were unimplemented in the ACS capability.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

/*
 * Many Intel PCH root ports do provide ACS-like features to disable peer
 * transactions and validate bus numbers in requests, but do not provide an
 * actual PCIe ACS capability.  This is the list of device IDs known to fall
 * into that category as provided by Intel in Red Hat bugzilla 1037684.
 */
static const u16 pci_quirk_intel_pch_acs_ids[] = {
	/* Ibexpeak PCH */
	0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
	0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
	/* Cougarpoint PCH */
	0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
	0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
	/* Pantherpoint PCH */
	0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
	0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
	/* Lynxpoint-H PCH */
	0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
	0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
	/* Lynxpoint-LP PCH */
	0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
	0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
	/* Wildcat PCH */
	0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
	0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
	/* Patsburg (X79) PCH */
	0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
	/* Wellsburg (X99) PCH */
	0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
	0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
	/* Lynx Point (9 series) PCH */
	0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
};

static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
{
	int i;

	/* Filter out a few obvious non-matches first */
	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return false;

	for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
		if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
			return true;

	return false;
}

#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)

static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
{
	u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
		    INTEL_PCH_ACS_FLAGS : 0;

	if (!pci_quirk_intel_pch_acs_match(dev))
		return -ENOTTY;

	return acs_flags & ~flags ? 0 : 1;
}

/*
 * These QCOM root ports do provide ACS-like features to disable peer
 * transactions and validate bus numbers in requests, but do not provide an
 * actual PCIe ACS capability.  Hardware supports source validation but it
 * will report the issue as Completer Abort instead of ACS Violation.
 * Hardware doesn't support peer-to-peer and each root port is a root
 * complex with unique segment numbers.  It is not possible for one root
 * port to pass traffic to another root port.  All PCIe transactions are
 * terminated inside the root port.
 */
static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
{
	u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
	int ret = acs_flags & ~flags ? 0 : 1;

	pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);

	return ret;
}

/*
 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
 * 7.16 ACS Extended Capability).  The bit definitions are correct, but the
 * control register is at offset 8 instead of 6 and we should probably use
 * dword accesses to them.  This applies to the following PCI Device IDs, as
 * found in volume 1 of the datasheet[2]:
 *
 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
 *
 * N.B. This doesn't fix what lspci shows.
 *
 * The 100 series chipset specification update includes this as errata #23[3].
 *
 * The 200 series chipset (Union Point) has the same bug according to the
 * specification update (Intel 200 Series Chipset Family Platform Controller
 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
 * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
 * chipset include:
 *
 * 0xa290-0xa29f PCI Express Root port #{0-16}
 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
 *
 * Mobile chipsets are also affected, 7th & 8th Generation
 * Specification update confirms ACS errata 22, status no fix: (7th Generation
 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
 * Processor Family I/O for U Quad Core Platforms Specification Update,
 * August 2017, Revision 002, Document#: 334660-002)[6]
 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
 *
 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
 *
 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
 */
static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
{
	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return false;

	switch (dev->device) {
	case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
	case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
	case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
		return true;
	}

	return false;
}

#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)

static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	/* see pci_acs_flags_enabled() */
	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	acs_flags &= (cap | PCI_ACS_EC);

	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	return acs_flags & ~ctrl ? 0 : 1;
}

static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * SV, TB, and UF are not relevant to multifunction endpoints.
	 *
	 * Multifunction devices are only required to implement RR, CR, and DT
	 * in their ACS capability if they support peer-to-peer transactions.
	 * Devices matching this quirk have been verified by the vendor to not
	 * perform peer-to-peer with other functions, allowing us to mask out
	 * these bits as if they were unimplemented in the ACS capability.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);

	return acs_flags ? 0 : 1;
}

static const struct pci_dev_acs_enabled {
	u16 vendor;
	u16 device;
	int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
} pci_dev_acs_enabled[] = {
	{ PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
	/* 82580 */
	{ PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
	/* 82576 */
	{ PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
	/* 82575 */
	{ PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
	/* I350 */
	{ PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
	/* 82571 (Quads omitted due to non-ACS switch) */
	{ PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
	/* I219 */
	{ PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
	/* QCOM QDF2xxx root ports */
	{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
	{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
	/* Intel PCH root ports */
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
	{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
	/* Cavium ThunderX */
	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
	/* APM X-Gene */
	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
	/* Ampere Computing */
	{ PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
	{ 0 }
};

int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
{
	const struct pci_dev_acs_enabled *i;
	int ret;

	/*
	 * Allow devices that do not expose standard PCIe ACS capabilities
	 * or control to indicate their support here.  Multi-function express
	 * devices which do not allow internal peer-to-peer between functions,
	 * but do not implement PCIe ACS may wish to return true here.
	 */
	for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
		if ((i->vendor == dev->vendor ||
		     i->vendor == (u16)PCI_ANY_ID) &&
		    (i->device == dev->device ||
		     i->device == (u16)PCI_ANY_ID)) {
			ret = i->acs_enabled(dev, acs_flags);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

/* Config space offset of Root Complex Base Address register */
#define INTEL_LPC_RCBA_REG 0xf0
/* 31:14 RCBA address */
#define INTEL_LPC_RCBA_MASK 0xffffc000
/* RCBA Enable */
#define INTEL_LPC_RCBA_ENABLE (1 << 0)

/* Backbone Scratch Pad Register */
#define INTEL_BSPR_REG 0x1104
/* Backbone Peer Non-Posted Disable */
#define INTEL_BSPR_REG_BPNPD (1 << 8)
/* Backbone Peer Posted Disable */
#define INTEL_BSPR_REG_BPPD  (1 << 9)

/* Upstream Peer Decode Configuration Register */
#define INTEL_UPDCR_REG 0x1114
/* 5:0 Peer Decode Enable bits */
#define INTEL_UPDCR_REG_MASK 0x3f

static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
{
	u32 rcba, bspr, updcr;
	void __iomem *rcba_mem;

	/*
	 * Read the RCBA register from the LPC (D31:F0).  PCH root ports
	 * are D28:F* and therefore get probed before LPC, thus we can't
	 * use pci_get_slot()/pci_read_config_dword() here.
	 */
	pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
				  INTEL_LPC_RCBA_REG, &rcba);
	if (!(rcba & INTEL_LPC_RCBA_ENABLE))
		return -EINVAL;

	rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
				   PAGE_ALIGN(INTEL_UPDCR_REG));
	if (!rcba_mem)
		return -ENOMEM;

	/*
	 * The BSPR can disallow peer cycles, but it's set by soft strap and
	 * therefore read-only.  If both posted and non-posted peer cycles are
	 * disallowed, we're ok.  If either are allowed, then we need to use
	 * the UPDCR to disable peer decodes for each port.  This provides the
	 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
	 */
	bspr = readl(rcba_mem + INTEL_BSPR_REG);
	bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
	if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
		updcr = readl(rcba_mem + INTEL_UPDCR_REG);
		if (updcr & INTEL_UPDCR_REG_MASK) {
			pci_info(dev, "Disabling UPDCR peer decodes\n");
			updcr &= ~INTEL_UPDCR_REG_MASK;
			writel(updcr, rcba_mem + INTEL_UPDCR_REG);
		}
	}

	iounmap(rcba_mem);
	return 0;
}

/* Miscellaneous Port Configuration register */
#define INTEL_MPC_REG 0xd8
/* MPC: Invalid Receive Bus Number Check Enable */
#define INTEL_MPC_REG_IRBNCE (1 << 26)

static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
{
	u32 mpc;

	/*
	 * When enabled, the IRBNCE bit of the MPC register enables the
	 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
	 * ensures that requester IDs fall within the bus number range
	 * of the bridge.  Enable if not already.
	 */
	pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
	if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
		pci_info(dev, "Enabling MPC IRBNCE\n");
		mpc |= INTEL_MPC_REG_IRBNCE;
		pci_write_config_word(dev, INTEL_MPC_REG, mpc);
	}
}

static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
{
	if (!pci_quirk_intel_pch_acs_match(dev))
		return -ENOTTY;

	if (pci_quirk_enable_intel_lpc_acs(dev)) {
		pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
		return 0;
	}

	pci_quirk_enable_intel_rp_mpc_acs(dev);

	dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;

	pci_info(dev, "Intel PCH root port ACS workaround enabled\n");

	return 0;
}

static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	ctrl |= (cap & PCI_ACS_SV);
	ctrl |= (cap & PCI_ACS_RR);
	ctrl |= (cap & PCI_ACS_CR);
	ctrl |= (cap & PCI_ACS_UF);

	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);

	pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");

	return 0;
}

static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);

	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);

	pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");

	return 0;
}

static const struct pci_dev_acs_ops {
	u16 vendor;
	u16 device;
	int (*enable_acs)(struct pci_dev *dev);
	int (*disable_acs_redir)(struct pci_dev *dev);
} pci_dev_acs_ops[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	    .enable_acs = pci_quirk_enable_intel_pch_acs,
	},
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	    .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
	    .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
	},
};

int pci_dev_specific_enable_acs(struct pci_dev *dev)
{
	const struct pci_dev_acs_ops *p;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
		p = &pci_dev_acs_ops[i];
		if ((p->vendor == dev->vendor ||
		     p->vendor == (u16)PCI_ANY_ID) &&
		    (p->device == dev->device ||
		     p->device == (u16)PCI_ANY_ID) &&
		    p->enable_acs) {
			ret = p->enable_acs(dev);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
{
	const struct pci_dev_acs_ops *p;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
		p = &pci_dev_acs_ops[i];
		if ((p->vendor == dev->vendor ||
		     p->vendor == (u16)PCI_ANY_ID) &&
		    (p->device == dev->device ||
		     p->device == (u16)PCI_ANY_ID) &&
		    p->disable_acs_redir) {
			ret = p->disable_acs_redir(dev);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

/*
 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
 * QuickAssist Technology (QAT) is prematurely terminated in hardware.  The
 * Next Capability pointer in the MSI Capability Structure should point to
 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
 * the list.
 */
static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
{
	int pos, i = 0;
	u8 next_cap;
	u16 reg16, *cap;
	struct pci_cap_saved_state *state;

	/* Bail if the hardware bug is fixed */
	if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
		return;

	/* Bail if MSI Capability Structure is not found for some reason */
	pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
	if (!pos)
		return;

	/*
	 * Bail if Next Capability pointer in the MSI Capability Structure
	 * is not the expected incorrect 0x00.
	 */
	pci_read_config_byte(pdev, pos + 1, &next_cap);
	if (next_cap)
		return;

	/*
	 * PCIe Capability Structure is expected to be at 0x50 and should
	 * terminate the list (Next Capability pointer is 0x00).  Verify
	 * Capability Id and Next Capability pointer is as expected.
	 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
	 * to correctly set kernel data structures which have already been
	 * set incorrectly due to the hardware bug.
	 */
	pos = 0x50;
	pci_read_config_word(pdev, pos, &reg16);
	if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
		u32 status;
#ifndef PCI_EXP_SAVE_REGS
#define PCI_EXP_SAVE_REGS     7
#endif
		int size = PCI_EXP_SAVE_REGS * sizeof(u16);

		pdev->pcie_cap = pos;
		pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
		pdev->pcie_flags_reg = reg16;
		pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
		pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;

		pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
		if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
		    PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
			pdev->cfg_size = PCI_CFG_SPACE_SIZE;

		if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
			return;

		/* Save PCIe cap */
		state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
		if (!state)
			return;

		state->cap.cap_nr = PCI_CAP_ID_EXP;
		state->cap.cap_extended = 0;
		state->cap.size = size;
		cap = (u16 *)&state->cap.data[0];
		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_RTCTL,  &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
		hlist_add_head(&state->next, &pdev->saved_cap_space);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);

/* FLR may cause some 82579 devices to hang */
static void quirk_intel_no_flr(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);

static void quirk_no_ext_tags(struct pci_dev *pdev)
{
	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);

	if (!bridge)
		return;

	bridge->no_ext_tags = 1;
	pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");

	pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);

#ifdef CONFIG_PCI_ATS
/*
 * Some devices have a broken ATS implementation causing IOMMU stalls.
 * Don't use ATS for those devices.
 */
static void quirk_no_ats(struct pci_dev *pdev)
{
	pci_info(pdev, "disabling ATS (broken on this device)\n");
	pdev->ats_cap = 0;
}

/* AMD Stoney platform GPU */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
#endif /* CONFIG_PCI_ATS */

/* Freescale PCIe doesn't support MSI in RC mode */
static void quirk_fsl_no_msi(struct pci_dev *pdev)
{
	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
		pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);

/*
 * GPUs with integrated HDA controller for streaming audio to attached displays
 * need a device link from the HDA controller (consumer) to the GPU (supplier)
 * so that the GPU is powered up whenever the HDA controller is accessed.
 * The GPU and HDA controller are functions 0 and 1 of the same PCI device.
 * The device link stays in place until shutdown (or removal of the PCI device
 * if it's hotplugged).  Runtime PM is allowed by default on the HDA controller
 * to prevent it from permanently keeping the GPU awake.
 */
static void quirk_gpu_hda(struct pci_dev *hda)
{
	struct pci_dev *gpu;

	if (PCI_FUNC(hda->devfn) != 1)
		return;

	gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus),
					  hda->bus->number,
					  PCI_DEVFN(PCI_SLOT(hda->devfn), 0));
	if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) {
		pci_dev_put(gpu);
		return;
	}

	if (!device_link_add(&hda->dev, &gpu->dev,
			     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
		pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu));

	pm_runtime_allow(&hda->dev);
	pci_dev_put(gpu);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);

/*
 * Some IDT switches incorrectly flag an ACS Source Validation error on
 * completions for config read requests even though PCIe r4.0, sec
 * 6.12.1.1, says that completions are never affected by ACS Source
 * Validation.  Here's the text of IDT 89H32H8G3-YC, erratum #36:
 *
 *   Item #36 - Downstream port applies ACS Source Validation to Completions
 *   Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
 *   completions are never affected by ACS Source Validation.  However,
 *   completions received by a downstream port of the PCIe switch from a
 *   device that has not yet captured a PCIe bus number are incorrectly
 *   dropped by ACS Source Validation by the switch downstream port.
 *
 * The workaround suggested by IDT is to issue a config write to the
 * downstream device before issuing the first config read.  This allows the
 * downstream device to capture its bus and device numbers (see PCIe r4.0,
 * sec 2.2.9), thus avoiding the ACS error on the completion.
 *
 * However, we don't know when the device is ready to accept the config
 * write, so we do config reads until we receive a non-Config Request Retry
 * Status, then do the config write.
 *
 * To avoid hitting the erratum when doing the config reads, we disable ACS
 * SV around this process.
 */
int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
{
	int pos;
	u16 ctrl = 0;
	bool found;
	struct pci_dev *bridge = bus->self;

	pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);

	/* Disable ACS SV before initial config reads */
	if (pos) {
		pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
		if (ctrl & PCI_ACS_SV)
			pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
					      ctrl & ~PCI_ACS_SV);
	}

	found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);

	/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
	if (found)
		pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);

	/* Re-enable ACS_SV if it was previously enabled */
	if (ctrl & PCI_ACS_SV)
		pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);

	return found;
}

/*
 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
 * NT endpoints via the internal switch fabric. These IDs replace the
 * originating requestor ID TLPs which access host memory on peer NTB
 * ports. Therefore, all proxy IDs must be aliased to the NTB device
 * to permit access when the IOMMU is turned on.
 */
static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
{
	void __iomem *mmio;
	struct ntb_info_regs __iomem *mmio_ntb;
	struct ntb_ctrl_regs __iomem *mmio_ctrl;
	struct sys_info_regs __iomem *mmio_sys_info;
	u64 partition_map;
	u8 partition;
	int pp;

	if (pci_enable_device(pdev)) {
		pci_err(pdev, "Cannot enable Switchtec device\n");
		return;
	}

	mmio = pci_iomap(pdev, 0, 0);
	if (mmio == NULL) {
		pci_disable_device(pdev);
		pci_err(pdev, "Cannot iomap Switchtec device\n");
		return;
	}

	pci_info(pdev, "Setting Switchtec proxy ID aliases\n");

	mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
	mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
	mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;

	partition = ioread8(&mmio_ntb->partition_id);

	partition_map = ioread32(&mmio_ntb->ep_map);
	partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
	partition_map &= ~(1ULL << partition);

	for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
		struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
		u32 table_sz = 0;
		int te;

		if (!(partition_map & (1ULL << pp)))
			continue;

		pci_dbg(pdev, "Processing partition %d\n", pp);

		mmio_peer_ctrl = &mmio_ctrl[pp];

		table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
		if (!table_sz) {
			pci_warn(pdev, "Partition %d table_sz 0\n", pp);
			continue;
		}

		if (table_sz > 512) {
			pci_warn(pdev,
				 "Invalid Switchtec partition %d table_sz %d\n",
				 pp, table_sz);
			continue;
		}

		for (te = 0; te < table_sz; te++) {
			u32 rid_entry;
			u8 devfn;

			rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
			devfn = (rid_entry >> 1) & 0xFF;
			pci_dbg(pdev,
				"Aliasing Partition %d Proxy ID %02x.%d\n",
				pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
			pci_add_dma_alias(pdev, devfn);
		}
	}

	pci_iounmap(pdev, mmio);
	pci_disable_device(pdev);
}
#define SWITCHTEC_QUIRK(vid) \
	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
				quirk_switchtec_ntb_dma_alias)

SWITCHTEC_QUIRK(0x8531);  /* PFX 24xG3 */
SWITCHTEC_QUIRK(0x8532);  /* PFX 32xG3 */
SWITCHTEC_QUIRK(0x8533);  /* PFX 48xG3 */
SWITCHTEC_QUIRK(0x8534);  /* PFX 64xG3 */
SWITCHTEC_QUIRK(0x8535);  /* PFX 80xG3 */
SWITCHTEC_QUIRK(0x8536);  /* PFX 96xG3 */
SWITCHTEC_QUIRK(0x8541);  /* PSX 24xG3 */
SWITCHTEC_QUIRK(0x8542);  /* PSX 32xG3 */
SWITCHTEC_QUIRK(0x8543);  /* PSX 48xG3 */
SWITCHTEC_QUIRK(0x8544);  /* PSX 64xG3 */
SWITCHTEC_QUIRK(0x8545);  /* PSX 80xG3 */
SWITCHTEC_QUIRK(0x8546);  /* PSX 96xG3 */
SWITCHTEC_QUIRK(0x8551);  /* PAX 24XG3 */
SWITCHTEC_QUIRK(0x8552);  /* PAX 32XG3 */
SWITCHTEC_QUIRK(0x8553);  /* PAX 48XG3 */
SWITCHTEC_QUIRK(0x8554);  /* PAX 64XG3 */
SWITCHTEC_QUIRK(0x8555);  /* PAX 80XG3 */
SWITCHTEC_QUIRK(0x8556);  /* PAX 96XG3 */
SWITCHTEC_QUIRK(0x8561);  /* PFXL 24XG3 */
SWITCHTEC_QUIRK(0x8562);  /* PFXL 32XG3 */
SWITCHTEC_QUIRK(0x8563);  /* PFXL 48XG3 */
SWITCHTEC_QUIRK(0x8564);  /* PFXL 64XG3 */
SWITCHTEC_QUIRK(0x8565);  /* PFXL 80XG3 */
SWITCHTEC_QUIRK(0x8566);  /* PFXL 96XG3 */
SWITCHTEC_QUIRK(0x8571);  /* PFXI 24XG3 */
SWITCHTEC_QUIRK(0x8572);  /* PFXI 32XG3 */
SWITCHTEC_QUIRK(0x8573);  /* PFXI 48XG3 */
SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */

/*
 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
 * not always reset the secondary Nvidia GPU between reboots if the system
 * is configured to use Hybrid Graphics mode.  This results in the GPU
 * being left in whatever state it was in during the *previous* boot, which
 * causes spurious interrupts from the GPU, which in turn causes us to
 * disable the wrong IRQ and end up breaking the touchpad.  Unsurprisingly,
 * this also completely breaks nouveau.
 *
 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
 * clean state and fixes all these issues.
 *
 * When the machine is configured in Dedicated display mode, the issue
 * doesn't occur.  Fortunately the GPU advertises NoReset+ when in this
 * mode, so we can detect that and avoid resetting it.
 */
static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
{
	void __iomem *map;
	int ret;

	if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
	    pdev->subsystem_device != 0x222e ||
	    !pdev->reset_fn)
		return;

	if (pci_enable_device_mem(pdev))
		return;

	/*
	 * Based on nvkm_device_ctor() in
	 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
	 */
	map = pci_iomap(pdev, 0, 0x23000);
	if (!map) {
		pci_err(pdev, "Can't map MMIO space\n");
		goto out_disable;
	}

	/*
	 * Make sure the GPU looks like it's been POSTed before resetting
	 * it.
	 */
	if (ioread32(map + 0x2240c) & 0x2) {
		pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
		ret = pci_reset_bus(pdev);
		if (ret < 0)
			pci_err(pdev, "Failed to reset GPU: %d\n", ret);
	}

	iounmap(map);
out_disable:
	pci_disable_device(pdev);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
			      PCI_CLASS_DISPLAY_VGA, 8,
			      quirk_reset_lenovo_thinkpad_p50_nvgpu);

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

[-- Attachment #1: Type: text/plain, Size: 6844 bytes --]

Here's the resulting output of the failed compilation of 5.4rc1 with
the patch applied to quirks.c:
 CC      drivers/pci/quirks.o
drivers/pci/quirks.c:3039:1: error: expected identifier or ‘(’ before ‘-’ token
 3039 | -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
      | ^
drivers/pci/quirks.c:3068:1: error: expected identifier or ‘(’ before ‘-’ token
 3068 | -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
      | ^
drivers/pci/quirks.c:3069:1: error: expected identifier or ‘(’ before ‘-’ token
 3069 | -DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
      | ^
drivers/pci/quirks.c:3070:1: error: expected identifier or ‘(’ before ‘-’ token
 3070 | -
      | ^
In file included from ./include/linux/export.h:44,
                 from ./include/linux/linkage.h:7,
                 from ./include/linux/kernel.h:8,
                 from drivers/pci/quirks.c:16:
drivers/pci/quirks.c:3120:74: error: ‘ricoh_mmc_fixup_r5c832’
undeclared here (not in a function)
 3120 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
      |
          ^~~~~~~~~~~~~~~~~~~~~~
./include/linux/compiler.h:302:53: note: in definition of macro ‘__ADDRESSABLE’
  302 |   __PASTE(__addressable_##sym, __LINE__) = (void *)&sym;
      |                                                     ^~~
./include/linux/pci.h:1911:2: note: in expansion of macro
‘__DECLARE_PCI_FIXUP_SECTION’
 1911 |  __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
      |  ^~~~~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/pci.h:1956:2: note: in expansion of macro
‘DECLARE_PCI_FIXUP_SECTION’
 1956 |  DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,   \
      |  ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pci/quirks.c:3120:1: note: in expansion of macro
‘DECLARE_PCI_FIXUP_EARLY’
 3120 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
      | ^~~~~~~~~~~~~~~~~~~~~~~
make[5]: *** [scripts/Makefile.build:266: drivers/pci/quirks.o] Error 1
make[4]: *** [scripts/Makefile.build:509: drivers/pci] Error 2
make[3]: *** [Makefile:1649: drivers] Error 2
make[2]: *** [debian/rules:6: build] Error 2
dpkg-buildpackage: error: debian/rules build subprocess returned exit status 2
make[1]: *** [scripts/Makefile.package:77: deb-pkg] Error 2
make: *** [Makefile:1427: deb-pkg] Error 2
root@michael-desktop:/home/michael/Debian/linux-5.4-rc4#

Please also find attached the patched quirks.c file
Cheers.
Michael

On 25/10/2019, Michael . <keltoiboy@gmail.com> wrote:
> I just tried to do a kernel compile on Debian Sid running kernel 5.2.
> Downloaded 4.19.80 modded the quirks file, please find modded file
> attached, and started the compile.
> About an hour into it it fails with:
>   CC      drivers/pci/quirks.o
> drivers/pci/quirks.c:2945:1: error: expected identifier or ‘(’ before ‘-’
> token
>  2945 | -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
>       | ^
> drivers/pci/quirks.c:2974:1: error: expected identifier or ‘(’ before ‘-’
> token
>  2974 | -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
> PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
>       | ^
> drivers/pci/quirks.c:2975:1: error: expected identifier or ‘(’ before ‘-’
> token
>  2975 | -DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH,
> PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
>       | ^
> drivers/pci/quirks.c:2976:1: error: expected identifier or ‘(’ before ‘-’
> token
>  2976 | -
>       | ^
> In file included from ./include/linux/export.h:45,
>                  from ./include/linux/linkage.h:7,
>                  from ./include/linux/kernel.h:7,
>                  from drivers/pci/quirks.c:16:
> drivers/pci/quirks.c:3026:74: error: ‘ricoh_mmc_fixup_r5c832’
> undeclared here (not in a function)
>  3026 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
> PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
>       |
>           ^~~~~~~~~~~~~~~~~~~~~~
> ./include/linux/compiler.h:296:53: note: in definition of macro
> ‘__ADDRESSABLE’
>   296 |   __PASTE(__addressable_##sym, __LINE__) = (void *)&sym;
>       |                                                     ^~~
> ./include/linux/pci.h:1847:2: note: in expansion of macro
> ‘__DECLARE_PCI_FIXUP_SECTION’
>  1847 |  __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
>       |  ^~~~~~~~~~~~~~~~~~~~~~~~~~~
> ./include/linux/pci.h:1892:2: note: in expansion of macro
> ‘DECLARE_PCI_FIXUP_SECTION’
>  1892 |  DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,   \
>       |  ^~~~~~~~~~~~~~~~~~~~~~~~~
> drivers/pci/quirks.c:3026:1: note: in expansion of macro
> ‘DECLARE_PCI_FIXUP_EARLY’
>  3026 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH,
> PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
>       | ^~~~~~~~~~~~~~~~~~~~~~~
> make[5]: *** [scripts/Makefile.build:304: drivers/pci/quirks.o] Error 1
> make[4]: *** [scripts/Makefile.build:544: drivers/pci] Error 2
> make[3]: *** [Makefile:1046: drivers] Error 2
> make[2]: *** [debian/rules:4: build] Error 2
> dpkg-buildpackage: error: debian/rules build subprocess returned exit status
> 2
> make[1]: *** [scripts/package/Makefile:75: deb-pkg] Error 2
> make: *** [Makefile:1359: deb-pkg] Error 2
> root@michael-desktop:/home/michael/Debian/linux-4.19.80#
>
> I will try later with the latest 5.4-rc to see if the diff is
> incompatible with 4.19.
> Cheers.
> Michael
>
> On 22/10/2019, Michael . <keltoiboy@gmail.com> wrote:
>> Thanks Domunik I'll get onto this and report back the results.
>>
>> On 22/10/2019, Dominik Brodowski <linux@dominikbrodowski.net> wrote:
>>> On Tue, Oct 22, 2019 at 05:17:12AM +1100, Michael . wrote:
>>>> Thank you Dominik for looking at this for us and passing it on.
>>>>
>>>> Good morning Bjorn, thank you also for looking into this for us and
>>>> thank you for CCing us into this as non of us are on the mailing list.
>>>> One question how do we apply this patch or is this for Dominik to try?
>>>
>>> That's for you and/or other users of this hardware; I cannot test this
>>> myself, sorry. As to how to apply the patch: you'd need to apply the
>>> patch
>>> for the linux kernel sources, and then build a custom kernel. Some hints
>>> on
>>> that (details depend on the distribtion):
>>>
>>> 	https://wiki.ubuntu.com/Kernel/BuildYourOwnKernel
>>> 	https://wiki.ubuntu.com/KernelTeam/GitKernelBuild
>>> 	https://wiki.archlinux.org/index.php/Kernels/Arch_Build_System
>>> 	https://kernelnewbies.org/KernelBuild
>>>
>>> Best,
>>> 	Dominik
>>>
>>
>

[-- Attachment #2: quirks.c --]
[-- Type: text/x-csrc, Size: 193892 bytes --]

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains work-arounds for many known PCI hardware bugs.
 * Devices present only on certain architectures (host bridges et cetera)
 * should be handled in arch-specific code.
 *
 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
 *
 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
 *
 * Init/reset quirks for USB host controllers should be in the USB quirks
 * file, where their drivers can use them.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/switchtec.h>
#include <asm/dma.h>	/* isa_dma_bridge_buggy */
#include "pci.h"

static ktime_t fixup_debug_start(struct pci_dev *dev,
				 void (*fn)(struct pci_dev *dev))
{
	if (initcall_debug)
		pci_info(dev, "calling  %pS @ %i\n", fn, task_pid_nr(current));

	return ktime_get();
}

static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
			       void (*fn)(struct pci_dev *dev))
{
	ktime_t delta, rettime;
	unsigned long long duration;

	rettime = ktime_get();
	delta = ktime_sub(rettime, calltime);
	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
	if (initcall_debug || duration > 10000)
		pci_info(dev, "%pS took %lld usecs\n", fn, duration);
}

static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
			  struct pci_fixup *end)
{
	ktime_t calltime;

	for (; f < end; f++)
		if ((f->class == (u32) (dev->class >> f->class_shift) ||
		     f->class == (u32) PCI_ANY_ID) &&
		    (f->vendor == dev->vendor ||
		     f->vendor == (u16) PCI_ANY_ID) &&
		    (f->device == dev->device ||
		     f->device == (u16) PCI_ANY_ID)) {
			void (*hook)(struct pci_dev *dev);
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
			hook = offset_to_ptr(&f->hook_offset);
#else
			hook = f->hook;
#endif
			calltime = fixup_debug_start(dev, hook);
			hook(dev);
			fixup_debug_report(dev, calltime, hook);
		}
}

extern struct pci_fixup __start_pci_fixups_early[];
extern struct pci_fixup __end_pci_fixups_early[];
extern struct pci_fixup __start_pci_fixups_header[];
extern struct pci_fixup __end_pci_fixups_header[];
extern struct pci_fixup __start_pci_fixups_final[];
extern struct pci_fixup __end_pci_fixups_final[];
extern struct pci_fixup __start_pci_fixups_enable[];
extern struct pci_fixup __end_pci_fixups_enable[];
extern struct pci_fixup __start_pci_fixups_resume[];
extern struct pci_fixup __end_pci_fixups_resume[];
extern struct pci_fixup __start_pci_fixups_resume_early[];
extern struct pci_fixup __end_pci_fixups_resume_early[];
extern struct pci_fixup __start_pci_fixups_suspend[];
extern struct pci_fixup __end_pci_fixups_suspend[];
extern struct pci_fixup __start_pci_fixups_suspend_late[];
extern struct pci_fixup __end_pci_fixups_suspend_late[];

static bool pci_apply_fixup_final_quirks;

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
{
	struct pci_fixup *start, *end;

	switch (pass) {
	case pci_fixup_early:
		start = __start_pci_fixups_early;
		end = __end_pci_fixups_early;
		break;

	case pci_fixup_header:
		start = __start_pci_fixups_header;
		end = __end_pci_fixups_header;
		break;

	case pci_fixup_final:
		if (!pci_apply_fixup_final_quirks)
			return;
		start = __start_pci_fixups_final;
		end = __end_pci_fixups_final;
		break;

	case pci_fixup_enable:
		start = __start_pci_fixups_enable;
		end = __end_pci_fixups_enable;
		break;

	case pci_fixup_resume:
		start = __start_pci_fixups_resume;
		end = __end_pci_fixups_resume;
		break;

	case pci_fixup_resume_early:
		start = __start_pci_fixups_resume_early;
		end = __end_pci_fixups_resume_early;
		break;

	case pci_fixup_suspend:
		start = __start_pci_fixups_suspend;
		end = __end_pci_fixups_suspend;
		break;

	case pci_fixup_suspend_late:
		start = __start_pci_fixups_suspend_late;
		end = __end_pci_fixups_suspend_late;
		break;

	default:
		/* stupid compiler warning, you would think with an enum... */
		return;
	}
	pci_do_fixups(dev, start, end);
}
EXPORT_SYMBOL(pci_fixup_device);

static int __init pci_apply_final_quirks(void)
{
	struct pci_dev *dev = NULL;
	u8 cls = 0;
	u8 tmp;

	if (pci_cache_line_size)
		pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);

	pci_apply_fixup_final_quirks = true;
	for_each_pci_dev(dev) {
		pci_fixup_device(pci_fixup_final, dev);
		/*
		 * If arch hasn't set it explicitly yet, use the CLS
		 * value shared by all PCI devices.  If there's a
		 * mismatch, fall back to the default value.
		 */
		if (!pci_cache_line_size) {
			pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
			if (!cls)
				cls = tmp;
			if (!tmp || cls == tmp)
				continue;

			pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
			         cls << 2, tmp << 2,
				 pci_dfl_cache_line_size << 2);
			pci_cache_line_size = pci_dfl_cache_line_size;
		}
	}

	if (!pci_cache_line_size) {
		pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
			pci_dfl_cache_line_size << 2);
		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
	}

	return 0;
}
fs_initcall_sync(pci_apply_final_quirks);

/*
 * Decoding should be disabled for a PCI device during BAR sizing to avoid
 * conflict. But doing so may cause problems on host bridge and perhaps other
 * key system devices. For devices that need to have mmio decoding always-on,
 * we need to set the dev->mmio_always_on bit.
 */
static void quirk_mmio_always_on(struct pci_dev *dev)
{
	dev->mmio_always_on = 1;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
				PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);

/*
 * The Mellanox Tavor device gives false positive parity errors.  Mark this
 * device with a broken_parity_status to allow PCI scanning code to "skip"
 * this now blacklisted device.
 */
static void quirk_mellanox_tavor(struct pci_dev *dev)
{
	dev->broken_parity_status = 1;	/* This device gives false positives */
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);

/*
 * Deal with broken BIOSes that neglect to enable passive release,
 * which can cause problems in combination with the 82441FX/PPro MTRRs
 */
static void quirk_passive_release(struct pci_dev *dev)
{
	struct pci_dev *d = NULL;
	unsigned char dlc;

	/*
	 * We have to make sure a particular bit is set in the PIIX3
	 * ISA bridge, so we have to go out and find it.
	 */
	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
		pci_read_config_byte(d, 0x82, &dlc);
		if (!(dlc & 1<<1)) {
			pci_info(d, "PIIX3: Enabling Passive Release\n");
			dlc |= 1<<1;
			pci_write_config_byte(d, 0x82, dlc);
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);

/*
 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
 * workaround but VIA don't answer queries. If you happen to have good
 * contacts at VIA ask them for me please -- Alan
 *
 * This appears to be BIOS not version dependent. So presumably there is a
 * chipset level fix.
 */
static void quirk_isa_dma_hangs(struct pci_dev *dev)
{
	if (!isa_dma_bridge_buggy) {
		isa_dma_bridge_buggy = 1;
		pci_info(dev, "Activating ISA DMA hang workarounds\n");
	}
}
/*
 * It's not totally clear which chipsets are the problematic ones.  We know
 * 82C586 and 82C596 variants are affected.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_0,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C596,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1533,		quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_1,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs);

/*
 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
 * for some HT machines to use C4 w/o hanging.
 */
static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
{
	u32 pmbase;
	u16 pm1a;

	pci_read_config_dword(dev, 0x40, &pmbase);
	pmbase = pmbase & 0xff80;
	pm1a = inw(pmbase);

	if (pm1a & 0x10) {
		pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
		outw(0x10, pmbase);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);

/* Chipsets where PCI->PCI transfers vanish or hang */
static void quirk_nopcipci(struct pci_dev *dev)
{
	if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
		pci_info(dev, "Disabling direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_FAIL;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci);

static void quirk_nopciamd(struct pci_dev *dev)
{
	u8 rev;
	pci_read_config_byte(dev, 0x08, &rev);
	if (rev == 0x13) {
		/* Erratum 24 */
		pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
		pci_pci_problems |= PCIAGP_FAIL;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopciamd);

/* Triton requires workarounds to be used by the drivers */
static void quirk_triton(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_TRITON;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437VX,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439TX,	quirk_triton);

/*
 * VIA Apollo KT133 needs PCI latency patch
 * Made according to a Windows driver-based patch by George E. Breese;
 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
 * which Mr Breese based his work.
 *
 * Updated based on further information from the site and also on
 * information provided by VIA
 */
static void quirk_vialatency(struct pci_dev *dev)
{
	struct pci_dev *p;
	u8 busarb;

	/*
	 * Ok, we have a potential problem chipset here. Now see if we have
	 * a buggy southbridge.
	 */
	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
	if (p != NULL) {

		/*
		 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
		 * thanks Dan Hollis.
		 * Check for buggy part revisions
		 */
		if (p->revision < 0x40 || p->revision > 0x42)
			goto exit;
	} else {
		p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
		if (p == NULL)	/* No problem parts */
			goto exit;

		/* Check for buggy part revisions */
		if (p->revision < 0x10 || p->revision > 0x12)
			goto exit;
	}

	/*
	 * Ok we have the problem. Now set the PCI master grant to occur
	 * every master grant. The apparent bug is that under high PCI load
	 * (quite common in Linux of course) you can get data loss when the
	 * CPU is held off the bus for 3 bus master requests.  This happens
	 * to include the IDE controllers....
	 *
	 * VIA only apply this fix when an SB Live! is present but under
	 * both Linux and Windows this isn't enough, and we have seen
	 * corruption without SB Live! but with things like 3 UDMA IDE
	 * controllers. So we ignore that bit of the VIA recommendation..
	 */
	pci_read_config_byte(dev, 0x76, &busarb);

	/*
	 * Set bit 4 and bit 5 of byte 76 to 0x01
	 * "Master priority rotation on every PCI master grant"
	 */
	busarb &= ~(1<<5);
	busarb |= (1<<4);
	pci_write_config_byte(dev, 0x76, busarb);
	pci_info(dev, "Applying VIA southbridge workaround\n");
exit:
	pci_dev_put(p);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
/* Must restore this on a resume from RAM */
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);

/* VIA Apollo VP3 needs ETBF on BT848/878 */
static void quirk_viaetbf(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_VIAETBF;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_viaetbf);

static void quirk_vsfx(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_VSFX;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx);

/*
 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
 * space. Latency must be set to 0xA and Triton workaround applied too.
 * [Info kindly provided by ALi]
 */
static void quirk_alimagik(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1647,		quirk_alimagik);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagik);

/* Natoma has some interesting boundary conditions with Zoran stuff at least */
static void quirk_natoma(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_NATOMA;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_0,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_1,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_0,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_1,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_2,	quirk_natoma);

/*
 * This chip can cause PCI parity errors if config register 0xA0 is read
 * while DMAs are occurring.
 */
static void quirk_citrine(struct pci_dev *dev)
{
	dev->cfg_size = 0xA0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine);

/*
 * This chip can cause bus lockups if config addresses above 0x600
 * are read or written.
 */
static void quirk_nfp6000(struct pci_dev *dev)
{
	dev->cfg_size = 0x600;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP4000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP5000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000_VF,	quirk_nfp6000);

/*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
static void quirk_extend_bar_to_page(struct pci_dev *dev)
{
	int i;

	for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
		struct resource *r = &dev->resource[i];

		if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
			r->end = PAGE_SIZE - 1;
			r->start = 0;
			r->flags |= IORESOURCE_UNSET;
			pci_info(dev, "expanded BAR %d to page size: %pR\n",
				 i, r);
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);

/*
 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 * If it's needed, re-allocate the region.
 */
static void quirk_s3_64M(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[0];

	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
		r->flags |= IORESOURCE_UNSET;
		r->start = 0;
		r->end = 0x3ffffff;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_868,		quirk_s3_64M);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_968,		quirk_s3_64M);

static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
		     const char *name)
{
	u32 region;
	struct pci_bus_region bus_region;
	struct resource *res = dev->resource + pos;

	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);

	if (!region)
		return;

	res->name = pci_name(dev);
	res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
	res->flags |=
		(IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
	region &= ~(size - 1);

	/* Convert from PCI bus to resource space */
	bus_region.start = region;
	bus_region.end = region + size - 1;
	pcibios_bus_to_resource(dev->bus, res, &bus_region);

	pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
		 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
}

/*
 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
 * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
 * (which conflicts w/ BAR1's memory range).
 *
 * CS553x's ISA PCI BARs may also be read-only (ref:
 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
 */
static void quirk_cs5536_vsa(struct pci_dev *dev)
{
	static char *name = "CS5536 ISA bridge";

	if (pci_resource_len(dev, 0) != 8) {
		quirk_io(dev, 0,   8, name);	/* SMB */
		quirk_io(dev, 1, 256, name);	/* GPIO */
		quirk_io(dev, 2,  64, name);	/* MFGPT */
		pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
			 name);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);

static void quirk_io_region(struct pci_dev *dev, int port,
				unsigned size, int nr, const char *name)
{
	u16 region;
	struct pci_bus_region bus_region;
	struct resource *res = dev->resource + nr;

	pci_read_config_word(dev, port, &region);
	region &= ~(size - 1);

	if (!region)
		return;

	res->name = pci_name(dev);
	res->flags = IORESOURCE_IO;

	/* Convert from PCI bus to resource space */
	bus_region.start = region;
	bus_region.end = region + size - 1;
	pcibios_bus_to_resource(dev->bus, res, &bus_region);

	if (!pci_claim_resource(dev, nr))
		pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
}

/*
 * ATI Northbridge setups MCE the processor if you even read somewhere
 * between 0x3b0->0x3bb or read 0x3d3
 */
static void quirk_ati_exploding_mce(struct pci_dev *dev)
{
	pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
	/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
	request_region(0x3b0, 0x0C, "RadeonIGP");
	request_region(0x3d3, 0x01, "RadeonIGP");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);

/*
 * In the AMD NL platform, this device ([1022:7912]) has a class code of
 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
 * claim it.
 *
 * But the dwc3 driver is a more specific driver for this device, and we'd
 * prefer to use it instead of xhci. To prevent xhci from claiming the
 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
 * defines as "USB device (not host controller)". The dwc3 driver can then
 * claim it based on its Vendor and Device ID.
 */
static void quirk_amd_nl_class(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	/* Use "USB Device (not host controller)" class */
	pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
	pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
		 class, pdev->class);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
		quirk_amd_nl_class);

/*
 * Synopsys USB 3.x host HAPS platform has a class code of
 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it.  However, these
 * devices should use dwc3-haps driver.  Change these devices' class code to
 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
 * them.
 */
static void quirk_synopsys_haps(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	switch (pdev->device) {
	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
		pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
		pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
			 class, pdev->class);
		break;
	}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
			       PCI_CLASS_SERIAL_USB_XHCI, 0,
			       quirk_synopsys_haps);

/*
 * Let's make the southbridge information explicit instead of having to
 * worry about people probing the ACPI areas, for example.. (Yes, it
 * happens, and if you read the wrong ACPI register it will put the machine
 * to sleep with no way of waking it up again. Bummer).
 *
 * ALI M7101: Two IO regions pointed to by words at
 *	0xE0 (64 bytes of ACPI registers)
 *	0xE2 (32 bytes of SMB registers)
 */
static void quirk_ali7101_acpi(struct pci_dev *dev)
{
	quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
	quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi);

static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
{
	u32 devres;
	u32 mask, size, base;

	pci_read_config_dword(dev, port, &devres);
	if ((devres & enable) != enable)
		return;
	mask = (devres >> 16) & 15;
	base = devres & 0xffff;
	size = 16;
	for (;;) {
		unsigned bit = size >> 1;
		if ((bit & mask) == bit)
			break;
		size = bit;
	}
	/*
	 * For now we only print it out. Eventually we'll want to
	 * reserve it (at least if it's in the 0x1000+ range), but
	 * let's get enough confirmation reports first.
	 */
	base &= -size;
	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
}

static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
{
	u32 devres;
	u32 mask, size, base;

	pci_read_config_dword(dev, port, &devres);
	if ((devres & enable) != enable)
		return;
	base = devres & 0xffff0000;
	mask = (devres & 0x3f) << 16;
	size = 128 << 16;
	for (;;) {
		unsigned bit = size >> 1;
		if ((bit & mask) == bit)
			break;
		size = bit;
	}

	/*
	 * For now we only print it out. Eventually we'll want to
	 * reserve it, but let's get enough confirmation reports first.
	 */
	base &= -size;
	pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
}

/*
 * PIIX4 ACPI: Two IO regions pointed to by longwords at
 *	0x40 (64 bytes of ACPI registers)
 *	0x90 (16 bytes of SMB registers)
 * and a few strange programmable PIIX4 device resources.
 */
static void quirk_piix4_acpi(struct pci_dev *dev)
{
	u32 res_a;

	quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");

	/* Device resource A has enables for some of the other ones */
	pci_read_config_dword(dev, 0x5c, &res_a);

	piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
	piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);

	/* Device resource D is just bitfields for static resources */

	/* Device 12 enabled? */
	if (res_a & (1 << 29)) {
		piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
		piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
	}
	/* Device 13 enabled? */
	if (res_a & (1 << 30)) {
		piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
		piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
	}
	piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
	piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_3,	quirk_piix4_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443MX_3,	quirk_piix4_acpi);

#define ICH_PMBASE	0x40
#define ICH_ACPI_CNTL	0x44
#define  ICH4_ACPI_EN	0x10
#define  ICH6_ACPI_EN	0x80
#define ICH4_GPIOBASE	0x58
#define ICH4_GPIO_CNTL	0x5c
#define  ICH4_GPIO_EN	0x10
#define ICH6_GPIOBASE	0x48
#define ICH6_GPIO_CNTL	0x4c
#define  ICH6_GPIO_EN	0x10

/*
 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 *	0x40 (128 bytes of ACPI, GPIO & TCO registers)
 *	0x58 (64 bytes of GPIO I/O space)
 */
static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
{
	u8 enable;

	/*
	 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
	 * with low legacy (and fixed) ports. We don't know the decoding
	 * priority and can't tell whether the legacy device or the one created
	 * here is really at that address.  This happens on boards with broken
	 * BIOSes.
	 */
	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
	if (enable & ICH4_ACPI_EN)
		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
				 "ICH4 ACPI/GPIO/TCO");

	pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
	if (enable & ICH4_GPIO_EN)
		quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
				"ICH4 GPIO");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi);

static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
{
	u8 enable;

	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
	if (enable & ICH6_ACPI_EN)
		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
				 "ICH6 ACPI/GPIO/TCO");

	pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
	if (enable & ICH6_GPIO_EN)
		quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
				"ICH6 GPIO");
}

static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
				    const char *name, int dynsize)
{
	u32 val;
	u32 size, base;

	pci_read_config_dword(dev, reg, &val);

	/* Enabled? */
	if (!(val & 1))
		return;
	base = val & 0xfffc;
	if (dynsize) {
		/*
		 * This is not correct. It is 16, 32 or 64 bytes depending on
		 * register D31:F0:ADh bits 5:4.
		 *
		 * But this gets us at least _part_ of it.
		 */
		size = 16;
	} else {
		size = 128;
	}
	base &= ~(size-1);

	/*
	 * Just print it out for now. We should reserve it after more
	 * debugging.
	 */
	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
}

static void quirk_ich6_lpc(struct pci_dev *dev)
{
	/* Shared ACPI/GPIO decode with all ICH6+ */
	ich6_lpc_acpi_gpio(dev);

	/* ICH6-specific generic IO decode */
	ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
	ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);

static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
				    const char *name)
{
	u32 val;
	u32 mask, base;

	pci_read_config_dword(dev, reg, &val);

	/* Enabled? */
	if (!(val & 1))
		return;

	/* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
	base = val & 0xfffc;
	mask = (val >> 16) & 0xfc;
	mask |= 3;

	/*
	 * Just print it out for now. We should reserve it after more
	 * debugging.
	 */
	pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
}

/* ICH7-10 has the same common LPC generic IO decode registers */
static void quirk_ich7_lpc(struct pci_dev *dev)
{
	/* We share the common ACPI/GPIO decode with ICH6 */
	ich6_lpc_acpi_gpio(dev);

	/* And have 4 ICH7+ generic decodes */
	ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
	ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
	ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
	ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);

/*
 * VIA ACPI: One IO region pointed to by longword at
 *	0x48 or 0x20 (256 bytes of ACPI registers)
 */
static void quirk_vt82c586_acpi(struct pci_dev *dev)
{
	if (dev->revision & 0x10)
		quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
				"vt82c586 ACPI");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_vt82c586_acpi);

/*
 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 *	0x48 (256 bytes of ACPI registers)
 *	0x70 (128 bytes of hardware monitoring register)
 *	0x90 (16 bytes of SMB registers)
 */
static void quirk_vt82c686_acpi(struct pci_dev *dev)
{
	quirk_vt82c586_acpi(dev);

	quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
				 "vt82c686 HW-mon");

	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi);

/*
 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 *	0x88 (128 bytes of power management registers)
 *	0xd0 (16 bytes of SMB registers)
 */
static void quirk_vt8235_acpi(struct pci_dev *dev)
{
	quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
	quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);

/*
 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
 * back-to-back: Disable fast back-to-back on the secondary bus segment
 */
static void quirk_xio2000a(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 command;

	pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
	list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
		pci_read_config_word(pdev, PCI_COMMAND, &command);
		if (command & PCI_COMMAND_FAST_BACK)
			pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
			quirk_xio2000a);

#ifdef CONFIG_X86_IO_APIC

#include <asm/io_apic.h>

/*
 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 * devices to the external APIC.
 *
 * TODO: When we have device-specific interrupt routers, this code will go
 * away from quirks.
 */
static void quirk_via_ioapic(struct pci_dev *dev)
{
	u8 tmp;

	if (nr_ioapics < 1)
		tmp = 0;    /* nothing routed to external APIC */
	else
		tmp = 0x1f; /* all known bits (4-0) routed to external APIC */

	pci_info(dev, "%sbling VIA external APIC routing\n",
	       tmp == 0 ? "Disa" : "Ena");

	/* Offset 0x58: External APIC IRQ output control */
	pci_write_config_byte(dev, 0x58, tmp);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);

/*
 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
 * This leads to doubled level interrupt rates.
 * Set this bit to get rid of cycle wastage.
 * Otherwise uncritical.
 */
static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
{
	u8 misc_control2;
#define BYPASS_APIC_DEASSERT 8

	pci_read_config_byte(dev, 0x5B, &misc_control2);
	if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
		pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
		pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

/*
 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
 * We check all revs >= B0 (yet not in the pre production!) as the bug
 * is currently marked NoFix
 *
 * We have multiple reports of hangs with this chipset that went away with
 * noapic specified. For the moment we assume it's the erratum. We may be wrong
 * of course. However the advice is demonstrably good even if so.
 */
static void quirk_amd_ioapic(struct pci_dev *dev)
{
	if (dev->revision >= 0x02) {
		pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
		pci_warn(dev, "        : booting with the \"noapic\" option\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);
#endif /* CONFIG_X86_IO_APIC */

#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)

static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
{
	/* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
	if (dev->subsystem_device == 0xa118)
		dev->sriov->link = dev->devfn;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
#endif

/*
 * Some settings of MMRBC can lead to data corruption so block changes.
 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
 */
static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
{
	if (dev->subordinate && dev->revision <= 0x12) {
		pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
			 dev->revision);
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);

/*
 * FIXME: it is questionable that quirk_via_acpi() is needed.  It shows up
 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
 * at all.  Therefore it seems like setting the pci_dev's IRQ to the value
 * of the ACPI SCI interrupt is only done for convenience.
 *	-jgarzik
 */
static void quirk_via_acpi(struct pci_dev *d)
{
	u8 irq;

	/* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
	pci_read_config_byte(d, 0x42, &irq);
	irq &= 0xf;
	if (irq && (irq != 2))
		d->irq = irq;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi);

/* VIA bridges which have VLink */
static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;

static void quirk_via_bridge(struct pci_dev *dev)
{
	/* See what bridge we have and find the device ranges */
	switch (dev->device) {
	case PCI_DEVICE_ID_VIA_82C686:
		/*
		 * The VT82C686 is special; it attaches to PCI and can have
		 * any device number. All its subdevices are functions of
		 * that single device.
		 */
		via_vlink_dev_lo = PCI_SLOT(dev->devfn);
		via_vlink_dev_hi = PCI_SLOT(dev->devfn);
		break;
	case PCI_DEVICE_ID_VIA_8237:
	case PCI_DEVICE_ID_VIA_8237A:
		via_vlink_dev_lo = 15;
		break;
	case PCI_DEVICE_ID_VIA_8235:
		via_vlink_dev_lo = 16;
		break;
	case PCI_DEVICE_ID_VIA_8231:
	case PCI_DEVICE_ID_VIA_8233_0:
	case PCI_DEVICE_ID_VIA_8233A:
	case PCI_DEVICE_ID_VIA_8233C_0:
		via_vlink_dev_lo = 17;
		break;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8231,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233_0,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233A,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233C_0,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237A,	quirk_via_bridge);

/*
 * quirk_via_vlink		-	VIA VLink IRQ number update
 * @dev: PCI device
 *
 * If the device we are dealing with is on a PIC IRQ we need to ensure that
 * the IRQ line register which usually is not relevant for PCI cards, is
 * actually written so that interrupts get sent to the right place.
 *
 * We only do this on systems where a VIA south bridge was detected, and
 * only for VIA devices on the motherboard (see quirk_via_bridge above).
 */
static void quirk_via_vlink(struct pci_dev *dev)
{
	u8 irq, new_irq;

	/* Check if we have VLink at all */
	if (via_vlink_dev_lo == -1)
		return;

	new_irq = dev->irq;

	/* Don't quirk interrupts outside the legacy IRQ range */
	if (!new_irq || new_irq > 15)
		return;

	/* Internal device ? */
	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
	    PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
		return;

	/*
	 * This is an internal VLink device on a PIC interrupt. The BIOS
	 * ought to have set this but may not have, so we redo it.
	 */
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	if (new_irq != irq) {
		pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
			irq, new_irq);
		udelay(15);	/* unknown if delay really needed */
		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);

/*
 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
 * of VT82C597 for backward compatibility.  We need to switch it off to be
 * able to recognize the real type of the chip.
 */
static void quirk_vt82c598_id(struct pci_dev *dev)
{
	pci_write_config_byte(dev, 0xfc, 0);
	pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_vt82c598_id);

/*
 * CardBus controllers have a legacy base address that enables them to
 * respond as i82365 pcmcia controllers.  We don't want them to do this
 * even if the Linux CardBus driver is not loaded, because the Linux i82365
 * driver does not (and should not) handle CardBus.
 */
static void quirk_cardbus_legacy(struct pci_dev *dev)
{
	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);

/*
 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
 * what the designers were smoking but let's not inhale...
 *
 * To be fair to AMD, it follows the spec by default, it's BIOS people who
 * turn it off!
 */
static void quirk_amd_ordering(struct pci_dev *dev)
{
	u32 pcic;
	pci_read_config_dword(dev, 0x4C, &pcic);
	if ((pcic & 6) != 6) {
		pcic |= 6;
		pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
		pci_write_config_dword(dev, 0x4C, pcic);
		pci_read_config_dword(dev, 0x84, &pcic);
		pcic |= (1 << 23);	/* Required in this mode */
		pci_write_config_dword(dev, 0x84, pcic);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);

/*
 * DreamWorks-provided workaround for Dunord I-3000 problem
 *
 * This card decodes and responds to addresses not apparently assigned to
 * it.  We force a larger allocation to ensure that nothing gets put too
 * close to it.
 */
static void quirk_dunord(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[1];

	r->flags |= IORESOURCE_UNSET;
	r->start = 0;
	r->end = 0xffffff;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,	PCI_DEVICE_ID_DUNORD_I3000,	quirk_dunord);

/*
 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
 * decoding (transparent), and does indicate this in the ProgIf.
 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
 */
static void quirk_transparent_bridge(struct pci_dev *dev)
{
	dev->transparent = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82380FB,	quirk_transparent_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA,	0x605,	quirk_transparent_bridge);

/*
 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
 * PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1 datasheets
 * found at http://www.national.com/analog for info on what these bits do.
 * <christer@weinigel.se>
 */
static void quirk_mediagx_master(struct pci_dev *dev)
{
	u8 reg;

	pci_read_config_byte(dev, 0x41, &reg);
	if (reg & 2) {
		reg &= ~2;
		pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
			 reg);
		pci_write_config_byte(dev, 0x41, reg);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);

/*
 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
 * in the odd case it is not the results are corruption hence the presence
 * of a Linux check.
 */
static void quirk_disable_pxb(struct pci_dev *pdev)
{
	u16 config;

	if (pdev->revision != 0x04)		/* Only C0 requires this */
		return;
	pci_read_config_word(pdev, 0x40, &config);
	if (config & (1<<6)) {
		config &= ~(1<<6);
		pci_write_config_word(pdev, 0x40, config);
		pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);

static void quirk_amd_ide_mode(struct pci_dev *pdev)
{
	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
	u8 tmp;

	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
	if (tmp == 0x01) {
		pci_read_config_byte(pdev, 0x40, &tmp);
		pci_write_config_byte(pdev, 0x40, tmp|1);
		pci_write_config_byte(pdev, 0x9, 1);
		pci_write_config_byte(pdev, 0xa, 6);
		pci_write_config_byte(pdev, 0x40, tmp);

		pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
		pci_info(pdev, "set SATA to AHCI mode\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);

/* Serverworks CSB5 IDE does not fully support native mode */
static void quirk_svwks_csb5ide(struct pci_dev *pdev)
{
	u8 prog;
	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
	if (prog & 5) {
		prog &= ~5;
		pdev->class &= ~5;
		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
		/* PCI layer will sort out resources */
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);

/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
static void quirk_ide_samemode(struct pci_dev *pdev)
{
	u8 prog;

	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);

	if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
		pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
		prog &= ~5;
		pdev->class &= ~5;
		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);

/* Some ATA devices break if put into D3 */
static void quirk_no_ata_d3(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
}
/* Quirk the legacy ATA devices only. The AHCI ones are ok */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
/* ALi loses some register settings that we cannot then restore */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
   occur when mode detecting */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);

/*
 * This was originally an Alpha-specific thing, but it really fits here.
 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
 */
static void quirk_eisa_bridge(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82375,	quirk_eisa_bridge);

/*
 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
 * is not activated. The myth is that Asus said that they do not want the
 * users to be irritated by just another PCI Device in the Win98 device
 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
 * package 2.7.0 for details)
 *
 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
 * becomes necessary to do this tweak in two steps -- the chosen trigger
 * is either the Host bridge (preferred) or on-board VGA controller.
 *
 * Note that we used to unhide the SMBus that way on Toshiba laptops
 * (Satellite A40 and Tecra M2) but then found that the thermal management
 * was done by SMM code, which could cause unsynchronized concurrent
 * accesses to the SMBus registers, with potentially bad effects. Thus you
 * should be very careful when adding new entries: if SMM is accessing the
 * Intel SMBus, this is a very good reason to leave it hidden.
 *
 * Likewise, many recent laptops use ACPI for thermal management. If the
 * ACPI DSDT code accesses the SMBus, then Linux should not access it
 * natively, and keeping the SMBus hidden is the right thing to do. If you
 * are about to add an entry in the table below, please first disassemble
 * the DSDT and double-check that there is no code accessing the SMBus.
 */
static int asus_hides_smbus;

static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
{
	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
		if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
			switch (dev->subsystem_device) {
			case 0x8025: /* P4B-LX */
			case 0x8070: /* P4B */
			case 0x8088: /* P4B533 */
			case 0x1626: /* L3C notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
			switch (dev->subsystem_device) {
			case 0x80b1: /* P4GE-V */
			case 0x80b2: /* P4PE */
			case 0x8093: /* P4B533-V */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
			switch (dev->subsystem_device) {
			case 0x8030: /* P4T533 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
			switch (dev->subsystem_device) {
			case 0x8070: /* P4G8X Deluxe */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
			switch (dev->subsystem_device) {
			case 0x80c9: /* PU-DLS */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
			switch (dev->subsystem_device) {
			case 0x1751: /* M2N notebook */
			case 0x1821: /* M5N notebook */
			case 0x1897: /* A6L notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x184b: /* W1N notebook */
			case 0x186a: /* M6Ne notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
			switch (dev->subsystem_device) {
			case 0x80f2: /* P4P800-X */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
			switch (dev->subsystem_device) {
			case 0x1882: /* M6V notebook */
			case 0x1977: /* A6VA notebook */
				asus_hides_smbus = 1;
			}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x088C: /* HP Compaq nc8000 */
			case 0x0890: /* HP Compaq nc6000 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
			switch (dev->subsystem_device) {
			case 0x12bc: /* HP D330L */
			case 0x12bd: /* HP D530 */
			case 0x006a: /* HP Compaq nx9500 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
			switch (dev->subsystem_device) {
			case 0x12bf: /* HP xw4100 */
				asus_hides_smbus = 1;
			}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0xC00C: /* Samsung P35 notebook */
				asus_hides_smbus = 1;
		}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x0058: /* Compaq Evo N620c */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
			switch (dev->subsystem_device) {
			case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
				/* Motherboard doesn't have Host bridge
				 * subvendor/subdevice IDs, therefore checking
				 * its on-board VGA controller */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
			switch (dev->subsystem_device) {
			case 0x00b8: /* Compaq Evo D510 CMT */
			case 0x00b9: /* Compaq Evo D510 SFF */
			case 0x00ba: /* Compaq Evo D510 USDT */
				/* Motherboard doesn't have Host bridge
				 * subvendor/subdevice IDs and on-board VGA
				 * controller is disabled if an AGP card is
				 * inserted, therefore checking USB UHCI
				 * Controller #1 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
			switch (dev->subsystem_device) {
			case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
				/* Motherboard doesn't have host bridge
				 * subvendor/subdevice IDs, therefore checking
				 * its on-board VGA controller */
				asus_hides_smbus = 1;
			}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845G_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82850_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82865_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82875_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_7205_0,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7501_MCH,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855PM_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82810_IG3,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_2,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82815_CGC,	asus_hides_smbus_hostbridge);

static void asus_hides_smbus_lpc(struct pci_dev *dev)
{
	u16 val;

	if (likely(!asus_hides_smbus))
		return;

	pci_read_config_word(dev, 0xF2, &val);
	if (val & 0x8) {
		pci_write_config_word(dev, 0xF2, val & (~0x8));
		pci_read_config_word(dev, 0xF2, &val);
		if (val & 0x8)
			pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
				 val);
		else
			pci_info(dev, "Enabled i801 SMBus device\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);

/* It appears we just have one such device. If not, we have a warning */
static void __iomem *asus_rcba_base;
static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
{
	u32 rcba;

	if (likely(!asus_hides_smbus))
		return;
	WARN_ON(asus_rcba_base);

	pci_read_config_dword(dev, 0xF0, &rcba);
	/* use bits 31:14, 16 kB aligned */
	asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
	if (asus_rcba_base == NULL)
		return;
}

static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
{
	u32 val;

	if (likely(!asus_hides_smbus || !asus_rcba_base))
		return;

	/* read the Function Disable register, dword mode only */
	val = readl(asus_rcba_base + 0x3418);

	/* enable the SMBus device */
	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
}

static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
{
	if (likely(!asus_hides_smbus || !asus_rcba_base))
		return;

	iounmap(asus_rcba_base);
	asus_rcba_base = NULL;
	pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
}

static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
{
	asus_hides_smbus_lpc_ich6_suspend(dev);
	asus_hides_smbus_lpc_ich6_resume_early(dev);
	asus_hides_smbus_lpc_ich6_resume(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6);
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_suspend);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume_early);

/* SiS 96x south bridge: BIOS typically hides SMBus device...  */
static void quirk_sis_96x_smbus(struct pci_dev *dev)
{
	u8 val = 0;
	pci_read_config_byte(dev, 0x77, &val);
	if (val & 0x10) {
		pci_info(dev, "Enabling SiS 96x SMBus\n");
		pci_write_config_byte(dev, 0x77, val & ~0x10);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);

/*
 * ... This is further complicated by the fact that some SiS96x south
 * bridges pretend to be 85C503/5513 instead.  In that case see if we
 * spotted a compatible north bridge to make sure.
 * (pci_find_device() doesn't work yet)
 *
 * We can also enable the sis96x bit in the discovery register..
 */
#define SIS_DETECT_REGISTER 0x40

static void quirk_sis_503(struct pci_dev *dev)
{
	u8 reg;
	u16 devid;

	pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
	pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
	pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
	if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
		pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
		return;
	}

	/*
	 * Ok, it now shows up as a 96x.  Run the 96x quirk by hand in case
	 * it has already been processed.  (Depends on link order, which is
	 * apparently not guaranteed)
	 */
	dev->device = devid;
	quirk_sis_96x_smbus(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);

/*
 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
 * and MC97 modem controller are disabled when a second PCI soundcard is
 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
 * -- bjd
 */
static void asus_hides_ac97_lpc(struct pci_dev *dev)
{
	u8 val;
	int asus_hides_ac97 = 0;

	if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
		if (dev->device == PCI_DEVICE_ID_VIA_8237)
			asus_hides_ac97 = 1;
	}

	if (!asus_hides_ac97)
		return;

	pci_read_config_byte(dev, 0x50, &val);
	if (val & 0xc0) {
		pci_write_config_byte(dev, 0x50, val & (~0xc0));
		pci_read_config_byte(dev, 0x50, &val);
		if (val & 0xc0)
			pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
				 val);
		else
			pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);

#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)

/*
 * If we are using libata we can drive this chip properly but must do this
 * early on to make the additional device appear during the PCI scanning.
 */
static void quirk_jmicron_ata(struct pci_dev *pdev)
{
	u32 conf1, conf5, class;
	u8 hdr;

	/* Only poke fn 0 */
	if (PCI_FUNC(pdev->devfn))
		return;

	pci_read_config_dword(pdev, 0x40, &conf1);
	pci_read_config_dword(pdev, 0x80, &conf5);

	conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
	conf5 &= ~(1 << 24);  /* Clear bit 24 */

	switch (pdev->device) {
	case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
	case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
	case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
		/* The controller should be in single function ahci mode */
		conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
		break;

	case PCI_DEVICE_ID_JMICRON_JMB365:
	case PCI_DEVICE_ID_JMICRON_JMB366:
		/* Redirect IDE second PATA port to the right spot */
		conf5 |= (1 << 24);
		/* Fall through */
	case PCI_DEVICE_ID_JMICRON_JMB361:
	case PCI_DEVICE_ID_JMICRON_JMB363:
	case PCI_DEVICE_ID_JMICRON_JMB369:
		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
		/* Set the class codes correctly and then direct IDE 0 */
		conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
		break;

	case PCI_DEVICE_ID_JMICRON_JMB368:
		/* The controller should be in single function IDE mode */
		conf1 |= 0x00C00000; /* Set 22, 23 */
		break;
	}

	pci_write_config_dword(pdev, 0x40, conf1);
	pci_write_config_dword(pdev, 0x80, conf5);

	/* Update pdev accordingly */
	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
	pdev->hdr_type = hdr & 0x7f;
	pdev->multifunction = !!(hdr & 0x80);

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
	pdev->class = class >> 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);

#endif

static void quirk_jmicron_async_suspend(struct pci_dev *dev)
{
	if (dev->multifunction) {
		device_disable_async_suspend(&dev->dev);
		pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
	}
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);

#ifdef CONFIG_X86_IO_APIC
static void quirk_alder_ioapic(struct pci_dev *pdev)
{
	int i;

	if ((pdev->class >> 8) != 0xff00)
		return;

	/*
	 * The first BAR is the location of the IO-APIC... we must
	 * not touch this (and it's already covered by the fixmap), so
	 * forcibly insert it into the resource tree.
	 */
	if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
		insert_resource(&iomem_resource, &pdev->resource[0]);

	/*
	 * The next five BARs all seem to be rubbish, so just clean
	 * them out.
	 */
	for (i = 1; i < 6; i++)
		memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_EESSC,	quirk_alder_ioapic);
#endif

static void quirk_pcie_mch(struct pci_dev *pdev)
{
	pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7520_MCH,	quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7320_MCH,	quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7525_MCH,	quirk_pcie_mch);

DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);

/*
 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
 * together on certain PXH-based systems.
 */
static void quirk_pcie_pxh(struct pci_dev *dev)
{
	dev->no_msi = 1;
	pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_0,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_1,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_pcie_pxh);

/*
 * Some Intel PCI Express chipsets have trouble with downstream device
 * power management.
 */
static void quirk_intel_pcie_pm(struct pci_dev *dev)
{
	pci_pm_d3_delay = 120;
	dev->no_d1d2 = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e2, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e3, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e4, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e5, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e6, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e7, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f7, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f8, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f9, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25fa, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2601, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2602, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2603, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2604, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2605, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2606, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2607, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2608, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);

static void quirk_radeon_pm(struct pci_dev *dev)
{
	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
	    dev->subsystem_device == 0x00e2) {
		if (dev->d3_delay < 20) {
			dev->d3_delay = 20;
			pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
				 dev->d3_delay);
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);

#ifdef CONFIG_X86_IO_APIC
static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
{
	noioapicreroute = 1;
	pr_info("%s detected: disable boot interrupt reroute\n", d->ident);

	return 0;
}

static const struct dmi_system_id boot_interrupt_dmi_table[] = {
	/*
	 * Systems to exclude from boot interrupt reroute quirks
	 */
	{
		.callback = dmi_disable_ioapicreroute,
		.ident = "ASUSTek Computer INC. M2N-LR",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
			DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
		},
	},
	{}
};

/*
 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
 * remap the original interrupt in the Linux kernel to the boot interrupt, so
 * that a PCI device's interrupt handler is installed on the boot interrupt
 * line instead.
 */
static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
{
	dmi_check_system(boot_interrupt_dmi_table);
	if (noioapicquirk || noioapicreroute)
		return;

	dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
	pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);

/*
 * On some chipsets we can disable the generation of legacy INTx boot
 * interrupts.
 */

/*
 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
 * 300641-004US, section 5.7.3.
 */
#define INTEL_6300_IOAPIC_ABAR		0x40
#define INTEL_6300_DISABLE_BOOT_IRQ	(1<<14)

static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
{
	u16 pci_config_word;

	if (noioapicquirk)
		return;

	pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
	pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
	pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,	quirk_disable_intel_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,	quirk_disable_intel_boot_interrupt);

/* Disable boot interrupts on HT-1000 */
#define BC_HT1000_FEATURE_REG		0x64
#define BC_HT1000_PIC_REGS_ENABLE	(1<<0)
#define BC_HT1000_MAP_IDX		0xC00
#define BC_HT1000_MAP_DATA		0xC01

static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
{
	u32 pci_config_dword;
	u8 irq;

	if (noioapicquirk)
		return;

	pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
			BC_HT1000_PIC_REGS_ENABLE);

	for (irq = 0x10; irq < 0x10 + 32; irq++) {
		outb(irq, BC_HT1000_MAP_IDX);
		outb(0x00, BC_HT1000_MAP_DATA);
	}

	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);

/* Disable boot interrupts on AMD and ATI chipsets */

/*
 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
 * (due to an erratum).
 */
#define AMD_813X_MISC			0x40
#define AMD_813X_NOIOAMODE		(1<<0)
#define AMD_813X_REV_B1			0x12
#define AMD_813X_REV_B2			0x13

static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
{
	u32 pci_config_dword;

	if (noioapicquirk)
		return;
	if ((dev->revision == AMD_813X_REV_B1) ||
	    (dev->revision == AMD_813X_REV_B2))
		return;

	pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
	pci_config_dword &= ~AMD_813X_NOIOAMODE;
	pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);

#define AMD_8111_PCI_IRQ_ROUTING	0x56

static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
{
	u16 pci_config_word;

	if (noioapicquirk)
		return;

	pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
	if (!pci_config_word) {
		pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
			 dev->vendor, dev->device);
		return;
	}
	pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
#endif /* CONFIG_X86_IO_APIC */

/*
 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
 * Re-allocate the region if needed...
 */
static void quirk_tc86c001_ide(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[0];

	if (r->start & 0x8) {
		r->flags |= IORESOURCE_UNSET;
		r->start = 0;
		r->end = 0xf;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
			 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
			 quirk_tc86c001_ide);

/*
 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
 * being read correctly if bit 7 of the base address is set.
 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
 * Re-allocate the regions to a 256-byte boundary if necessary.
 */
static void quirk_plx_pci9050(struct pci_dev *dev)
{
	unsigned int bar;

	/* Fixed in revision 2 (PCI 9052). */
	if (dev->revision >= 2)
		return;
	for (bar = 0; bar <= 1; bar++)
		if (pci_resource_len(dev, bar) == 0x80 &&
		    (pci_resource_start(dev, bar) & 0x80)) {
			struct resource *r = &dev->resource[bar];
			pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
				 bar);
			r->flags |= IORESOURCE_UNSET;
			r->start = 0;
			r->end = 0xff;
		}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
			 quirk_plx_pci9050);
/*
 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
 *
 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
 * driver.
 */
DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);

static void quirk_netmos(struct pci_dev *dev)
{
	unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
	unsigned int num_serial = dev->subsystem_device & 0xf;

	/*
	 * These Netmos parts are multiport serial devices with optional
	 * parallel ports.  Even when parallel ports are present, they
	 * are identified as class SERIAL, which means the serial driver
	 * will claim them.  To prevent this, mark them as class OTHER.
	 * These combo devices should be claimed by parport_serial.
	 *
	 * The subdevice ID is of the form 0x00PS, where <P> is the number
	 * of parallel ports and <S> is the number of serial ports.
	 */
	switch (dev->device) {
	case PCI_DEVICE_ID_NETMOS_9835:
		/* Well, this rule doesn't hold for the following 9835 device */
		if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
				dev->subsystem_device == 0x0299)
			return;
		/* else, fall through */
	case PCI_DEVICE_ID_NETMOS_9735:
	case PCI_DEVICE_ID_NETMOS_9745:
	case PCI_DEVICE_ID_NETMOS_9845:
	case PCI_DEVICE_ID_NETMOS_9855:
		if (num_parallel) {
			pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
				dev->device, num_parallel, num_serial);
			dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
			    (dev->class & 0xff);
		}
	}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
			 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);

static void quirk_e100_interrupt(struct pci_dev *dev)
{
	u16 command, pmcsr;
	u8 __iomem *csr;
	u8 cmd_hi;

	switch (dev->device) {
	/* PCI IDs taken from drivers/net/e100.c */
	case 0x1029:
	case 0x1030 ... 0x1034:
	case 0x1038 ... 0x103E:
	case 0x1050 ... 0x1057:
	case 0x1059:
	case 0x1064 ... 0x106B:
	case 0x1091 ... 0x1095:
	case 0x1209:
	case 0x1229:
	case 0x2449:
	case 0x2459:
	case 0x245D:
	case 0x27DC:
		break;
	default:
		return;
	}

	/*
	 * Some firmware hands off the e100 with interrupts enabled,
	 * which can cause a flood of interrupts if packets are
	 * received before the driver attaches to the device.  So
	 * disable all e100 interrupts here.  The driver will
	 * re-enable them when it's ready.
	 */
	pci_read_config_word(dev, PCI_COMMAND, &command);

	if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
		return;

	/*
	 * Check that the device is in the D0 power state. If it's not,
	 * there is no point to look any further.
	 */
	if (dev->pm_cap) {
		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
			return;
	}

	/* Convert from PCI bus to resource space.  */
	csr = ioremap(pci_resource_start(dev, 0), 8);
	if (!csr) {
		pci_warn(dev, "Can't map e100 registers\n");
		return;
	}

	cmd_hi = readb(csr + 3);
	if (cmd_hi == 0) {
		pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
		writeb(1, csr + 3);
	}

	iounmap(csr);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);

/*
 * The 82575 and 82598 may experience data corruption issues when transitioning
 * out of L0S.  To prevent this we need to disable L0S on the PCIe link.
 */
static void quirk_disable_aspm_l0s(struct pci_dev *dev)
{
	pci_info(dev, "Disabling L0s\n");
	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);

/*
 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
 * Link bit cleared after starting the link retrain process to allow this
 * process to finish.
 *
 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130.  See also the
 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
 */
static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
{
	dev->clear_retrain_link = 1;
	pci_info(dev, "Enable PCIe Retrain Link quirk\n");
}
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);

static void fixup_rev1_53c810(struct pci_dev *dev)
{
	u32 class = dev->class;

	/*
	 * rev 1 ncr53c810 chips don't set the class at all which means
	 * they don't get their resources remapped. Fix that here.
	 */
	if (class)
		return;

	dev->class = PCI_CLASS_STORAGE_SCSI << 8;
	pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
		 class, dev->class);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);

/* Enable 1k I/O space granularity on the Intel P64H2 */
static void quirk_p64h2_1k_io(struct pci_dev *dev)
{
	u16 en1k;

	pci_read_config_word(dev, 0x40, &en1k);

	if (en1k & 0x200) {
		pci_info(dev, "Enable I/O Space to 1KB granularity\n");
		dev->io_window_1k = 1;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);

/*
 * Under some circumstances, AER is not linked with extended capabilities.
 * Force it to be linked by setting the corresponding control bit in the
 * config space.
 */
static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
{
	uint8_t b;

	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
		if (!(b & 0x20)) {
			pci_write_config_byte(dev, 0xf41, b | 0x20);
			pci_info(dev, "Linking AER extended capability\n");
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_pcie_aer_ext_cap);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_pcie_aer_ext_cap);

static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
{
	/*
	 * Disable PCI Bus Parking and PCI Master read caching on CX700
	 * which causes unspecified timing errors with a VT6212L on the PCI
	 * bus leading to USB2.0 packet loss.
	 *
	 * This quirk is only enabled if a second (on the external PCI bus)
	 * VT6212L is found -- the CX700 core itself also contains a USB
	 * host controller with the same PCI ID as the VT6212L.
	 */

	/* Count VT6212L instances */
	struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
		PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
	uint8_t b;

	/*
	 * p should contain the first (internal) VT6212L -- see if we have
	 * an external one by searching again.
	 */
	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
	if (!p)
		return;
	pci_dev_put(p);

	if (pci_read_config_byte(dev, 0x76, &b) == 0) {
		if (b & 0x40) {
			/* Turn off PCI Bus Parking */
			pci_write_config_byte(dev, 0x76, b ^ 0x40);

			pci_info(dev, "Disabling VIA CX700 PCI parking\n");
		}
	}

	if (pci_read_config_byte(dev, 0x72, &b) == 0) {
		if (b != 0) {
			/* Turn off PCI Master read caching */
			pci_write_config_byte(dev, 0x72, 0x0);

			/* Set PCI Master Bus time-out to "1x16 PCLK" */
			pci_write_config_byte(dev, 0x75, 0x1);

			/* Disable "Read FIFO Timer" */
			pci_write_config_byte(dev, 0x77, 0x0);

			pci_info(dev, "Disabling VIA CX700 PCI caching\n");
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);

static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
{
	u32 rev;

	pci_read_config_dword(dev, 0xf4, &rev);

	/* Only CAP the MRRS if the device is a 5719 A0 */
	if (rev == 0x05719000) {
		int readrq = pcie_get_readrq(dev);
		if (readrq > 2048)
			pcie_set_readrq(dev, 2048);
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
			 PCI_DEVICE_ID_TIGON3_5719,
			 quirk_brcm_5719_limit_mrrs);

#ifdef CONFIG_PCIE_IPROC_PLATFORM
static void quirk_paxc_bridge(struct pci_dev *pdev)
{
	/*
	 * The PCI config space is shared with the PAXC root port and the first
	 * Ethernet device.  So, we need to workaround this by telling the PCI
	 * code that the bridge is not an Ethernet device.
	 */
	if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
		pdev->class = PCI_CLASS_BRIDGE_PCI << 8;

	/*
	 * MPSS is not being set properly (as it is currently 0).  This is
	 * because that area of the PCI config space is hard coded to zero, and
	 * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)
	 * so that the MPS can be set to the real max value.
	 */
	pdev->pcie_mpss = 2;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
#endif

/*
 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
 * hide device 6 which configures the overflow device access containing the
 * DRBs - this is where we expose device 6.
 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
 */
static void quirk_unhide_mch_dev6(struct pci_dev *dev)
{
	u8 reg;

	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
		pci_info(dev, "Enabling MCH 'Overflow' Device\n");
		pci_write_config_byte(dev, 0xF4, reg | 0x02);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
			quirk_unhide_mch_dev6);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
			quirk_unhide_mch_dev6);

#ifdef CONFIG_PCI_MSI
/*
 * Some chipsets do not support MSI. We cannot easily rely on setting
 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
 * other buses controlled by the chipset even if Linux is not aware of it.
 * Instead of setting the flag on all buses in the machine, simply disable
 * MSI globally.
 */
static void quirk_disable_all_msi(struct pci_dev *dev)
{
	pci_no_msi();
	pci_warn(dev, "MSI quirk detected; MSI disabled\n");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);

/* Disable MSI on chipsets that are known to not support it */
static void quirk_disable_msi(struct pci_dev *dev)
{
	if (dev->subordinate) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);

/*
 * The APC bridge device in AMD 780 family northbridges has some random
 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
 * we use the possible vendor/device IDs of the host bridge for the
 * declared quirk, and search for the APC bridge by slot number.
 */
static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
{
	struct pci_dev *apc_bridge;

	apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
	if (apc_bridge) {
		if (apc_bridge->device == 0x9602)
			quirk_disable_msi(apc_bridge);
		pci_dev_put(apc_bridge);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);

/*
 * Go through the list of HyperTransport capabilities and return 1 if a HT
 * MSI capability is found and enabled.
 */
static int msi_ht_cap_enabled(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Found %s HT MSI Mapping\n",
				flags & HT_MSI_FLAGS_ENABLE ?
				"enabled" : "disabled");
			return (flags & HT_MSI_FLAGS_ENABLE) != 0;
		}

		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
	return 0;
}

/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
static void quirk_msi_ht_cap(struct pci_dev *dev)
{
	if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
			quirk_msi_ht_cap);

/*
 * The nVidia CK804 chipset may have 2 HT MSI mappings.  MSI is supported
 * if the MSI capability is set in any of these mappings.
 */
static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
{
	struct pci_dev *pdev;

	if (!dev->subordinate)
		return;

	/*
	 * Check HT MSI cap on this chipset and the root one.  A single one
	 * having MSI is enough to be sure that MSI is supported.
	 */
	pdev = pci_get_slot(dev->bus, 0);
	if (!pdev)
		return;
	if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
	pci_dev_put(pdev);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_msi_ht_cap);

/* Force enable MSI mapping capability on HT bridges */
static void ht_enable_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Enabling HT MSI Mapping\n");

			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
					      flags | HT_MSI_FLAGS_ENABLE);
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
			 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
			 ht_enable_msi_mapping);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
			 ht_enable_msi_mapping);

/*
 * The P5N32-SLI motherboards from Asus have a problem with MSI
 * for the MCP55 NIC. It is not yet determined whether the MSI problem
 * also affects other devices. As for now, turn off MSI for this device.
 */
static void nvenet_msi_disable(struct pci_dev *dev)
{
	const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);

	if (board_name &&
	    (strstr(board_name, "P5N32-SLI PREMIUM") ||
	     strstr(board_name, "P5N32-E SLI"))) {
		pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
		dev->no_msi = 1;
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_NVENET_15,
			nvenet_msi_disable);

/*
 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
 * generate MSI interrupts for PME and AER events instead only INTx interrupts
 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
 * for other events, since PCIe specificiation doesn't support using a mix of
 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
 * service drivers registering their respective ISRs for MSIs.
 */
static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
{
	dev->no_msi = 1;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);

/*
 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
 * config register.  This register controls the routing of legacy
 * interrupts from devices that route through the MCP55.  If this register
 * is misprogrammed, interrupts are only sent to the BSP, unlike
 * conventional systems where the IRQ is broadcast to all online CPUs.  Not
 * having this register set properly prevents kdump from booting up
 * properly, so let's make sure that we have it set correctly.
 * Note that this is an undocumented register.
 */
static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
{
	u32 cfg;

	if (!pci_find_capability(dev, PCI_CAP_ID_HT))
		return;

	pci_read_config_dword(dev, 0x74, &cfg);

	if (cfg & ((1 << 2) | (1 << 15))) {
		pr_info("Rewriting IRQ routing register on MCP55\n");
		cfg &= ~((1 << 2) | (1 << 15));
		pci_write_config_dword(dev, 0x74, cfg);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
			nvbridge_check_legacy_irq_routing);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
			nvbridge_check_legacy_irq_routing);

static int ht_check_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;
	int found = 0;

	/* Check if there is HT MSI cap or enabled on this device */
	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (found < 1)
			found = 1;
		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			if (flags & HT_MSI_FLAGS_ENABLE) {
				if (found < 2) {
					found = 2;
					break;
				}
			}
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}

	return found;
}

static int host_bridge_with_leaf(struct pci_dev *host_bridge)
{
	struct pci_dev *dev;
	int pos;
	int i, dev_no;
	int found = 0;

	dev_no = host_bridge->devfn >> 3;
	for (i = dev_no + 1; i < 0x20; i++) {
		dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
		if (!dev)
			continue;

		/* found next host bridge? */
		pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
		if (pos != 0) {
			pci_dev_put(dev);
			break;
		}

		if (ht_check_msi_mapping(dev)) {
			found = 1;
			pci_dev_put(dev);
			break;
		}
		pci_dev_put(dev);
	}

	return found;
}

#define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
#define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */

static int is_end_of_ht_chain(struct pci_dev *dev)
{
	int pos, ctrl_off;
	int end = 0;
	u16 flags, ctrl;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);

	if (!pos)
		goto out;

	pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);

	ctrl_off = ((flags >> 10) & 1) ?
			PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
	pci_read_config_word(dev, pos + ctrl_off, &ctrl);

	if (ctrl & (1 << 6))
		end = 1;

out:
	return end;
}

static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
	struct pci_dev *host_bridge;
	int pos;
	int i, dev_no;
	int found = 0;

	dev_no = dev->devfn >> 3;
	for (i = dev_no; i >= 0; i--) {
		host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
		if (!host_bridge)
			continue;

		pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
		if (pos != 0) {
			found = 1;
			break;
		}
		pci_dev_put(host_bridge);
	}

	if (!found)
		return;

	/* don't enable end_device/host_bridge with leaf directly here */
	if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
	    host_bridge_with_leaf(host_bridge))
		goto out;

	/* root did that ! */
	if (msi_ht_cap_enabled(host_bridge))
		goto out;

	ht_enable_msi_mapping(dev);

out:
	pci_dev_put(host_bridge);
}

static void ht_disable_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Disabling HT MSI Mapping\n");

			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
					      flags & ~HT_MSI_FLAGS_ENABLE);
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
}

static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
{
	struct pci_dev *host_bridge;
	int pos;
	int found;

	if (!pci_msi_enabled())
		return;

	/* check if there is HT MSI cap or enabled on this device */
	found = ht_check_msi_mapping(dev);

	/* no HT MSI CAP */
	if (found == 0)
		return;

	/*
	 * HT MSI mapping should be disabled on devices that are below
	 * a non-Hypertransport host bridge. Locate the host bridge...
	 */
	host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
						  PCI_DEVFN(0, 0));
	if (host_bridge == NULL) {
		pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
		return;
	}

	pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
	if (pos != 0) {
		/* Host bridge is to HT */
		if (found == 1) {
			/* it is not enabled, try to enable it */
			if (all)
				ht_enable_msi_mapping(dev);
			else
				nv_ht_enable_msi_mapping(dev);
		}
		goto out;
	}

	/* HT MSI is not enabled */
	if (found == 1)
		goto out;

	/* Host bridge is not to HT, disable HT MSI mapping on this device */
	ht_disable_msi_mapping(dev);

out:
	pci_dev_put(host_bridge);
}

static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
{
	return __nv_msi_ht_cap_quirk(dev, 1);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);

static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
{
	return __nv_msi_ht_cap_quirk(dev, 0);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);

static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
}

static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
{
	struct pci_dev *p;

	/*
	 * SB700 MSI issue will be fixed at HW level from revision A21;
	 * we need check PCI REVISION ID of SMBus controller to get SB700
	 * revision.
	 */
	p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
			   NULL);
	if (!p)
		return;

	if ((p->revision < 0x3B) && (p->revision >= 0x30))
		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
	pci_dev_put(p);
}

static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
{
	/* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
	if (dev->revision < 0x18) {
		pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5780,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5780S,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5714,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5714S,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5715,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5715S,
			quirk_msi_intx_disable_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
			quirk_msi_intx_disable_ati_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
			quirk_msi_intx_disable_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
			quirk_msi_intx_disable_qca_bug);

/*
 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
 * should be disabled on platforms where the device (mistakenly) advertises it.
 *
 * Notice that this quirk also disables MSI (which may work, but hasn't been
 * tested), since currently there is no standard way to disable only MSI-X.
 *
 * The 0031 device id is reused for other non Root Port device types,
 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
 */
static void quirk_al_msi_disable(struct pci_dev *dev)
{
	dev->no_msi = 1;
	pci_warn(dev, "Disabling MSI/MSI-X\n");
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
			      PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
#endif /* CONFIG_PCI_MSI */

/*
 * Allow manual resource allocation for PCI hotplug bridges via
 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
 * allocate resources when hotplug device is inserted and PCI bus is
 * rescanned.
 */
static void quirk_hotplug_bridge(struct pci_dev *dev)
{
	dev->is_hotplug_bridge = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);

/*
 * This is a quirk for the Ricoh MMC controller found as a part of some
 * multifunction chips.
 *
 * This is very similar and based on the ricoh_mmc driver written by
 * Philip Langdale. Thank you for these magic sequences.
 *
 * These chips implement the four main memory card controllers (SD, MMC,
 * MS, xD) and one or both of CardBus or FireWire.
 *
 * It happens that they implement SD and MMC support as separate
 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
 * cards but the chip detects MMC cards in hardware and directs them to the
 * MMC controller - so the SDHCI driver never sees them.
 *
 * To get around this, we must disable the useless MMC controller.  At that
 * point, the SDHCI controller will start seeing them.  It seems to be the
 * case that the relevant PCI registers to deactivate the MMC controller
 * live on PCI function 0, which might be the CardBus controller or the
 * FireWire controller, depending on the particular chip in question
 *
 * This has to be done early, because as soon as we disable the MMC controller
 * other PCI functions shift up one level, e.g. function #2 becomes function
 * #1, and this will confuse the PCI core.
 */
#ifdef CONFIG_MMC_RICOH_MMC
-static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
-{
-       u8 write_enable;
-       u8 write_target;
-       u8 disable;
-
-       /*
-        * Disable via CardBus interface
-        *
-        * This must be done via function #0
-        */
-       if (PCI_FUNC(dev->devfn))
-               return;
-
-       pci_read_config_byte(dev, 0xB7, &disable);
-       if (disable & 0x02)
-               return;
-
-       pci_read_config_byte(dev, 0x8E, &write_enable);
-       pci_write_config_byte(dev, 0x8E, 0xAA);
-       pci_read_config_byte(dev, 0x8D, &write_target);
-       pci_write_config_byte(dev, 0x8D, 0xB7);
-       pci_write_config_byte(dev, 0xB7, disable | 0x02);
-       pci_write_config_byte(dev, 0x8E, write_enable);
-       pci_write_config_byte(dev, 0x8D, write_target);
-
-       pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
-       pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
-}
-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
-DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
-
 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
 {
        u8 write_enable;

	/*
	 * Disable via FireWire interface
	 *
	 * This must be done via function #0
	 */
	if (PCI_FUNC(dev->devfn))
		return;
	/*
	 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
	 * certain types of SD/MMC cards. Lowering the SD base clock
	 * frequency from 200Mhz to 50Mhz fixes this issue.
	 *
	 * 0x150 - SD2.0 mode enable for changing base clock
	 *	   frequency to 50Mhz
	 * 0xe1  - Base clock frequency
	 * 0x32  - 50Mhz new clock frequency
	 * 0xf9  - Key register for 0x150
	 * 0xfc  - key register for 0xe1
	 */
	if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
	    dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
		pci_write_config_byte(dev, 0xf9, 0xfc);
		pci_write_config_byte(dev, 0x150, 0x10);
		pci_write_config_byte(dev, 0xf9, 0x00);
		pci_write_config_byte(dev, 0xfc, 0x01);
		pci_write_config_byte(dev, 0xe1, 0x32);
		pci_write_config_byte(dev, 0xfc, 0x00);

		pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
	}

	pci_read_config_byte(dev, 0xCB, &disable);

	if (disable & 0x02)
		return;

	pci_read_config_byte(dev, 0xCA, &write_enable);
	pci_write_config_byte(dev, 0xCA, 0x57);
	pci_write_config_byte(dev, 0xCB, disable | 0x02);
	pci_write_config_byte(dev, 0xCA, write_enable);

	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
	pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");

}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
#endif /*CONFIG_MMC_RICOH_MMC*/

#ifdef CONFIG_DMAR_TABLE
#define VTUNCERRMSK_REG	0x1ac
#define VTD_MSK_SPEC_ERRORS	(1 << 31)
/*
 * This is a quirk for masking VT-d spec-defined errors to platform error
 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
 * on the RAS config settings of the platform) when a VT-d fault happens.
 * The resulting SMI caused the system to hang.
 *
 * VT-d spec-related errors are already handled by the VT-d OS code, so no
 * need to report the same error through other channels.
 */
static void vtd_mask_spec_errors(struct pci_dev *dev)
{
	u32 word;

	pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
	pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
#endif

static void fixup_ti816x_class(struct pci_dev *dev)
{
	u32 class = dev->class;

	/* TI 816x devices do not have class code set when in PCIe boot mode */
	dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
	pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
		 class, dev->class);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
			      PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);

/*
 * Some PCIe devices do not work reliably with the claimed maximum
 * payload size supported.
 */
static void fixup_mpss_256(struct pci_dev *dev)
{
	dev->pcie_mpss = 1; /* 256 bytes */
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);

/*
 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
 * Since there is no way of knowing what the PCIe MPS on each fabric will be
 * until all of the devices are discovered and buses walked, read completion
 * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
 * it is possible to hotplug a device with MPS of 256B.
 */
static void quirk_intel_mc_errata(struct pci_dev *dev)
{
	int err;
	u16 rcc;

	if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
	    pcie_bus_config == PCIE_BUS_DEFAULT)
		return;

	/*
	 * Intel erratum specifies bits to change but does not say what
	 * they are.  Keeping them magical until such time as the registers
	 * and values can be explained.
	 */
	err = pci_read_config_word(dev, 0x48, &rcc);
	if (err) {
		pci_err(dev, "Error attempting to read the read completion coalescing register\n");
		return;
	}

	if (!(rcc & (1 << 10)))
		return;

	rcc &= ~(1 << 10);

	err = pci_write_config_word(dev, 0x48, rcc);
	if (err) {
		pci_err(dev, "Error attempting to write the read completion coalescing register\n");
		return;
	}

	pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
}
/* Intel 5000 series memory controllers and ports 2-7 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
/* Intel 5100 series memory controllers and ports 2-7 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);

/*
 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
 * To work around this, query the size it should be configured to by the
 * device and modify the resource end to correspond to this new size.
 */
static void quirk_intel_ntb(struct pci_dev *dev)
{
	int rc;
	u8 val;

	rc = pci_read_config_byte(dev, 0x00D0, &val);
	if (rc)
		return;

	dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;

	rc = pci_read_config_byte(dev, 0x00D1, &val);
	if (rc)
		return;

	dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);

/*
 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
 * though no one is handling them (e.g., if the i915 driver is never
 * loaded).  Additionally the interrupt destination is not set up properly
 * and the interrupt ends up -somewhere-.
 *
 * These spurious interrupts are "sticky" and the kernel disables the
 * (shared) interrupt line after 100,000+ generated interrupts.
 *
 * Fix it by disabling the still enabled interrupts.  This resolves crashes
 * often seen on monitor unplug.
 */
#define I915_DEIER_REG 0x4400c
static void disable_igfx_irq(struct pci_dev *dev)
{
	void __iomem *regs = pci_iomap(dev, 0, 0);
	if (regs == NULL) {
		pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
		return;
	}

	/* Check if any interrupt line is still enabled */
	if (readl(regs + I915_DEIER_REG) != 0) {
		pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");

		writel(0, regs + I915_DEIER_REG);
	}

	pci_iounmap(dev, regs);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);

/*
 * PCI devices which are on Intel chips can skip the 10ms delay
 * before entering D3 mode.
 */
static void quirk_remove_d3_delay(struct pci_dev *dev)
{
	dev->d3_delay = 0;
}
/* C600 Series devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
/* Intel Cherrytrail devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);

/*
 * Some devices may pass our check in pci_intx_mask_supported() if
 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
 * support this feature.
 */
static void quirk_broken_intx_masking(struct pci_dev *dev)
{
	dev->broken_intx_masking = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
			quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
			quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
			quirk_broken_intx_masking);

/*
 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
 *
 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
			quirk_broken_intx_masking);

/*
 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
 * DisINTx can be set but the interrupt status bit is non-functional.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);

static u16 mellanox_broken_intx_devs[] = {
	PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
	PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
	PCI_DEVICE_ID_MELLANOX_HERMON_EN,
	PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX3,
	PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
};

#define CONNECTX_4_CURR_MAX_MINOR 99
#define CONNECTX_4_INTX_SUPPORT_MINOR 14

/*
 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
 * If so, don't mark it as broken.
 * FW minor > 99 means older FW version format and no INTx masking support.
 * FW minor < 14 means new FW version format and no INTx masking support.
 */
static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
{
	__be32 __iomem *fw_ver;
	u16 fw_major;
	u16 fw_minor;
	u16 fw_subminor;
	u32 fw_maj_min;
	u32 fw_sub_min;
	int i;

	for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
		if (pdev->device == mellanox_broken_intx_devs[i]) {
			pdev->broken_intx_masking = 1;
			return;
		}
	}

	/*
	 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
	 * support so shouldn't be checked further
	 */
	if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
		return;

	if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
	    pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
		return;

	/* For ConnectX-4 and ConnectX-4LX, need to check FW support */
	if (pci_enable_device_mem(pdev)) {
		pci_warn(pdev, "Can't enable device memory\n");
		return;
	}

	fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
	if (!fw_ver) {
		pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
		goto out;
	}

	/* Reading from resource space should be 32b aligned */
	fw_maj_min = ioread32be(fw_ver);
	fw_sub_min = ioread32be(fw_ver + 1);
	fw_major = fw_maj_min & 0xffff;
	fw_minor = fw_maj_min >> 16;
	fw_subminor = fw_sub_min & 0xffff;
	if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
	    fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
		pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
			 fw_major, fw_minor, fw_subminor, pdev->device ==
			 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
		pdev->broken_intx_masking = 1;
	}

	iounmap(fw_ver);

out:
	pci_disable_device(pdev);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
			mellanox_check_broken_intx_masking);

static void quirk_no_bus_reset(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
}

/*
 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
 * The device will throw a Link Down error on AER-capable systems and
 * regardless of AER, config space of the device is never accessible again
 * and typically causes the system to hang or reset when access is attempted.
 * http://www.spinics.net/lists/linux-pci/msg34797.html
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);

/*
 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
 * reset when used with certain child devices.  After the reset, config
 * accesses to the child may fail.
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);

static void quirk_no_pm_reset(struct pci_dev *dev)
{
	/*
	 * We can't do a bus reset on root bus devices, but an ineffective
	 * PM reset may be better than nothing.
	 */
	if (!pci_is_root_bus(dev->bus))
		dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
}

/*
 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
 * causes a reset (i.e., they advertise NoSoftRst-).  This transition seems
 * to have no effect on the device: it retains the framebuffer contents and
 * monitor sync.  Advertising this support makes other layers, like VFIO,
 * assume pci_reset_function() is viable for this device.  Mark it as
 * unavailable to skip it when testing reset methods.
 */
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
			       PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);

/*
 * Thunderbolt controllers with broken MSI hotplug signaling:
 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
 */
static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
{
	if (pdev->is_hotplug_bridge &&
	    (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
	     pdev->revision <= 1))
		pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
			quirk_thunderbolt_hotplug_msi);

#ifdef CONFIG_ACPI
/*
 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
 *
 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
 * shutdown before suspend. Otherwise the native host interface (NHI) will not
 * be present after resume if a device was plugged in before suspend.
 *
 * The Thunderbolt controller consists of a PCIe switch with downstream
 * bridges leading to the NHI and to the tunnel PCI bridges.
 *
 * This quirk cuts power to the whole chip. Therefore we have to apply it
 * during suspend_noirq of the upstream bridge.
 *
 * Power is automagically restored before resume. No action is needed.
 */
static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
{
	acpi_handle bridge, SXIO, SXFP, SXLV;

	if (!x86_apple_machine)
		return;
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
		return;
	bridge = ACPI_HANDLE(&dev->dev);
	if (!bridge)
		return;

	/*
	 * SXIO and SXLV are present only on machines requiring this quirk.
	 * Thunderbolt bridges in external devices might have the same
	 * device ID as those on the host, but they will not have the
	 * associated ACPI methods. This implicitly checks that we are at
	 * the right bridge.
	 */
	if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
		return;
	pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");

	/* magic sequence */
	acpi_execute_simple_method(SXIO, NULL, 1);
	acpi_execute_simple_method(SXFP, NULL, 0);
	msleep(300);
	acpi_execute_simple_method(SXLV, NULL, 0);
	acpi_execute_simple_method(SXIO, NULL, 0);
	acpi_execute_simple_method(SXLV, NULL, 0);
}
DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			       quirk_apple_poweroff_thunderbolt);

/*
 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
 *
 * During suspend the Thunderbolt controller is reset and all PCI
 * tunnels are lost. The NHI driver will try to reestablish all tunnels
 * during resume. We have to manually wait for the NHI since there is
 * no parent child relationship between the NHI and the tunneled
 * bridges.
 */
static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
{
	struct pci_dev *sibling = NULL;
	struct pci_dev *nhi = NULL;

	if (!x86_apple_machine)
		return;
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
		return;

	/*
	 * Find the NHI and confirm that we are a bridge on the Thunderbolt
	 * host controller and not on a Thunderbolt endpoint.
	 */
	sibling = pci_get_slot(dev->bus, 0x0);
	if (sibling == dev)
		goto out; /* we are the downstream bridge to the NHI */
	if (!sibling || !sibling->subordinate)
		goto out;
	nhi = pci_get_slot(sibling->subordinate, 0x0);
	if (!nhi)
		goto out;
	if (nhi->vendor != PCI_VENDOR_ID_INTEL
		    || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
			nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
		    || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
		goto out;
	pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
	device_pm_wait_for_dev(&dev->dev, &nhi->dev);
out:
	pci_dev_put(nhi);
	pci_dev_put(sibling);
}
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
			       quirk_apple_wait_for_thunderbolt);
#endif

/*
 * Following are device-specific reset methods which can be used to
 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
 * not available.
 */
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
{
	/*
	 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
	 *
	 * The 82599 supports FLR on VFs, but FLR support is reported only
	 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
	 * Thus we must call pcie_flr() directly without first checking if it is
	 * supported.
	 */
	if (!probe)
		pcie_flr(dev);
	return 0;
}

#define SOUTH_CHICKEN2		0xc2004
#define PCH_PP_STATUS		0xc7200
#define PCH_PP_CONTROL		0xc7204
#define MSG_CTL			0x45010
#define NSDE_PWR_STATE		0xd0100
#define IGD_OPERATION_TIMEOUT	10000     /* set timeout 10 seconds */

static int reset_ivb_igd(struct pci_dev *dev, int probe)
{
	void __iomem *mmio_base;
	unsigned long timeout;
	u32 val;

	if (probe)
		return 0;

	mmio_base = pci_iomap(dev, 0, 0);
	if (!mmio_base)
		return -ENOMEM;

	iowrite32(0x00000002, mmio_base + MSG_CTL);

	/*
	 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
	 * driver loaded sets the right bits. However, this's a reset and
	 * the bits have been set by i915 previously, so we clobber
	 * SOUTH_CHICKEN2 register directly here.
	 */
	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);

	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
	iowrite32(val, mmio_base + PCH_PP_CONTROL);

	timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
	do {
		val = ioread32(mmio_base + PCH_PP_STATUS);
		if ((val & 0xb0000000) == 0)
			goto reset_complete;
		msleep(10);
	} while (time_before(jiffies, timeout));
	pci_warn(dev, "timeout during reset\n");

reset_complete:
	iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);

	pci_iounmap(dev, mmio_base);
	return 0;
}

/* Device-specific reset method for Chelsio T4-based adapters */
static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
{
	u16 old_command;
	u16 msix_flags;

	/*
	 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
	 * that we have no device-specific reset method.
	 */
	if ((dev->device & 0xf000) != 0x4000)
		return -ENOTTY;

	/*
	 * If this is the "probe" phase, return 0 indicating that we can
	 * reset this device.
	 */
	if (probe)
		return 0;

	/*
	 * T4 can wedge if there are DMAs in flight within the chip and Bus
	 * Master has been disabled.  We need to have it on till the Function
	 * Level Reset completes.  (BUS_MASTER is disabled in
	 * pci_reset_function()).
	 */
	pci_read_config_word(dev, PCI_COMMAND, &old_command);
	pci_write_config_word(dev, PCI_COMMAND,
			      old_command | PCI_COMMAND_MASTER);

	/*
	 * Perform the actual device function reset, saving and restoring
	 * configuration information around the reset.
	 */
	pci_save_state(dev);

	/*
	 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
	 * are disabled when an MSI-X interrupt message needs to be delivered.
	 * So we briefly re-enable MSI-X interrupts for the duration of the
	 * FLR.  The pci_restore_state() below will restore the original
	 * MSI-X state.
	 */
	pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
	if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
		pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
				      msix_flags |
				      PCI_MSIX_FLAGS_ENABLE |
				      PCI_MSIX_FLAGS_MASKALL);

	pcie_flr(dev);

	/*
	 * Restore the configuration information (BAR values, etc.) including
	 * the original PCI Configuration Space Command word, and return
	 * success.
	 */
	pci_restore_state(dev);
	pci_write_config_word(dev, PCI_COMMAND, old_command);
	return 0;
}

#define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
#define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166

/*
 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
 * FLR where config space reads from the device return -1.  We seem to be
 * able to avoid this condition if we disable the NVMe controller prior to
 * FLR.  This quirk is generic for any NVMe class device requiring similar
 * assistance to quiesce the device prior to FLR.
 *
 * NVMe specification: https://nvmexpress.org/resources/specifications/
 * Revision 1.0e:
 *    Chapter 2: Required and optional PCI config registers
 *    Chapter 3: NVMe control registers
 *    Chapter 7.3: Reset behavior
 */
static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
{
	void __iomem *bar;
	u16 cmd;
	u32 cfg;

	if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
	    !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
		return -ENOTTY;

	if (probe)
		return 0;

	bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
	if (!bar)
		return -ENOTTY;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);

	cfg = readl(bar + NVME_REG_CC);

	/* Disable controller if enabled */
	if (cfg & NVME_CC_ENABLE) {
		u32 cap = readl(bar + NVME_REG_CAP);
		unsigned long timeout;

		/*
		 * Per nvme_disable_ctrl() skip shutdown notification as it
		 * could complete commands to the admin queue.  We only intend
		 * to quiesce the device before reset.
		 */
		cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);

		writel(cfg, bar + NVME_REG_CC);

		/*
		 * Some controllers require an additional delay here, see
		 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY.  None of those are yet
		 * supported by this quirk.
		 */

		/* Cap register provides max timeout in 500ms increments */
		timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;

		for (;;) {
			u32 status = readl(bar + NVME_REG_CSTS);

			/* Ready status becomes zero on disable complete */
			if (!(status & NVME_CSTS_RDY))
				break;

			msleep(100);

			if (time_after(jiffies, timeout)) {
				pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
				break;
			}
		}
	}

	pci_iounmap(dev, bar);

	pcie_flr(dev);

	return 0;
}

/*
 * Intel DC P3700 NVMe controller will timeout waiting for ready status
 * to change after NVMe enable if the driver starts interacting with the
 * device too soon after FLR.  A 250ms delay after FLR has heuristically
 * proven to produce reliably working results for device assignment cases.
 */
static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
{
	if (!pcie_has_flr(dev))
		return -ENOTTY;

	if (probe)
		return 0;

	pcie_flr(dev);

	msleep(250);

	return 0;
}

static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
		 reset_intel_82599_sfp_virtfn },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
		reset_ivb_igd },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
		reset_ivb_igd },
	{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
	{ PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
		reset_chelsio_generic_dev },
	{ 0 }
};

/*
 * These device-specific reset methods are here rather than in a driver
 * because when a host assigns a device to a guest VM, the host may need
 * to reset the device but probably doesn't have a driver for it.
 */
int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	const struct pci_dev_reset_methods *i;

	for (i = pci_dev_reset_methods; i->reset; i++) {
		if ((i->vendor == dev->vendor ||
		     i->vendor == (u16)PCI_ANY_ID) &&
		    (i->device == dev->device ||
		     i->device == (u16)PCI_ANY_ID))
			return i->reset(dev, probe);
	}

	return -ENOTTY;
}

static void quirk_dma_func0_alias(struct pci_dev *dev)
{
	if (PCI_FUNC(dev->devfn) != 0)
		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
}

/*
 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
 *
 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);

static void quirk_dma_func1_alias(struct pci_dev *dev)
{
	if (PCI_FUNC(dev->devfn) != 1)
		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
}

/*
 * Marvell 88SE9123 uses function 1 as the requester ID for DMA.  In some
 * SKUs function 1 is present and is a legacy IDE controller, in other
 * SKUs this function is not present, making this a ghost requester.
 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
			 quirk_dma_func1_alias);
/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
			 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
			 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
			 quirk_dma_func1_alias);

/*
 * Some devices DMA with the wrong devfn, not just the wrong function.
 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
 * the alias is "fixed" and independent of the device devfn.
 *
 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
 * processor.  To software, this appears as a PCIe-to-PCI/X bridge with a
 * single device on the secondary bus.  In reality, the single exposed
 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
 * that provides a bridge to the internal bus of the I/O processor.  The
 * controller supports private devices, which can be hidden from PCI config
 * space.  In the case of the Adaptec 3405, a private device at 01.0
 * appears to be the DMA engine, which therefore needs to become a DMA
 * alias for the device.
 */
static const struct pci_device_id fixed_dma_alias_tbl[] = {
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
			 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
	  .driver_data = PCI_DEVFN(1, 0) },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
			 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
	  .driver_data = PCI_DEVFN(1, 0) },
	{ 0 }
};

static void quirk_fixed_dma_alias(struct pci_dev *dev)
{
	const struct pci_device_id *id;

	id = pci_match_id(fixed_dma_alias_tbl, dev);
	if (id)
		pci_add_dma_alias(dev, id->driver_data);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);

/*
 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
 * using the wrong DMA alias for the device.  Some of these devices can be
 * used as either forward or reverse bridges, so we need to test whether the
 * device is operating in the correct mode.  We could probably apply this
 * quirk to PCI_ANY_ID, but for now we'll just use known offenders.  The test
 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
 */
static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
{
	if (!pci_is_root_bus(pdev->bus) &&
	    pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
	    !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
	    pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
		pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
}
/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
			 quirk_use_pcie_bridge_dma_alias);
/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
/* ITE 8893 has the same problem as the 8892 */
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);

/*
 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
 * be added as aliases to the DMA device in order to allow buffer access
 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
 * programmed in the EEPROM.
 */
static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
{
	pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
	pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
	pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);

/*
 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
 * associated not at the root bus, but at a bridge below. This quirk avoids
 * generating invalid DMA aliases.
 */
static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
				quirk_bridge_cavm_thrx2_pcie_root);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
				quirk_bridge_cavm_thrx2_pcie_root);

/*
 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
 * class code.  Fix it.
 */
static void quirk_tw686x_class(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	/* Use "Multimedia controller" class */
	pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
	pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
		 class, pdev->class);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);

/*
 * Some devices have problems with Transaction Layer Packets with the Relaxed
 * Ordering Attribute set.  Such devices should mark themselves and other
 * device drivers should check before sending TLPs with RO set.
 */
static void quirk_relaxedordering_disable(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
	pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
}

/*
 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
 * Complex have a Flow Control Credit issue which can cause performance
 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
 */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);

/*
 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
 * where Upstream Transaction Layer Packets with the Relaxed Ordering
 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
 * set.  This is a violation of the PCIe 3.0 Transaction Ordering Rules
 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
 * November 10, 2010).  As a result, on this platform we can't use Relaxed
 * Ordering for Upstream TLPs.
 */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);

/*
 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
 * values for the Attribute as were supplied in the header of the
 * corresponding Request, except as explicitly allowed when IDO is used."
 *
 * If a non-compliant device generates a completion with a different
 * attribute than the request, the receiver may accept it (which itself
 * seems non-compliant based on sec 2.3.2), or it may handle it as a
 * Malformed TLP or an Unexpected Completion, which will probably lead to a
 * device access timeout.
 *
 * If the non-compliant device generates completions with zero attributes
 * (instead of copying the attributes from the request), we can work around
 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
 * upstream devices so they always generate requests with zero attributes.
 *
 * This affects other devices under the same Root Port, but since these
 * attributes are performance hints, there should be no functional problem.
 *
 * Note that Configuration Space accesses are never supposed to have TLP
 * Attributes, so we're safe waiting till after any Configuration Space
 * accesses to do the Root Port fixup.
 */
static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
{
	struct pci_dev *root_port = pci_find_pcie_root_port(pdev);

	if (!root_port) {
		pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
		return;
	}

	pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
		 dev_name(&pdev->dev));
	pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
					   PCI_EXP_DEVCTL_RELAX_EN |
					   PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
}

/*
 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
 * Completion it generates.
 */
static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
{
	/*
	 * This mask/compare operation selects for Physical Function 4 on a
	 * T5.  We only need to fix up the Root Port once for any of the
	 * PFs.  PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
	 * 0x54xx so we use that one.
	 */
	if ((pdev->device & 0xff00) == 0x5400)
		quirk_disable_root_port_attributes(pdev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
			 quirk_chelsio_T5_disable_root_port_attributes);

/*
 * AMD has indicated that the devices below do not support peer-to-peer
 * in any system where they are found in the southbridge with an AMD
 * IOMMU in the system.  Multifunction devices that do not support
 * peer-to-peer between functions can claim to support a subset of ACS.
 * Such devices effectively enable request redirect (RR) and completion
 * redirect (CR) since all transactions are redirected to the upstream
 * root complex.
 *
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
 *
 * 1002:4385 SBx00 SMBus Controller
 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
 * 1002:4383 SBx00 Azalia (Intel HDA)
 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
 * 1002:4384 SBx00 PCI to PCI Bridge
 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
 *
 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
 *
 * 1022:780f [AMD] FCH PCI Bridge
 * 1022:7809 [AMD] FCH USB OHCI Controller
 */
static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
{
#ifdef CONFIG_ACPI
	struct acpi_table_header *header = NULL;
	acpi_status status;

	/* Targeting multifunction devices on the SB (appears on root bus) */
	if (!dev->multifunction || !pci_is_root_bus(dev->bus))
		return -ENODEV;

	/* The IVRS table describes the AMD IOMMU */
	status = acpi_get_table("IVRS", 0, &header);
	if (ACPI_FAILURE(status))
		return -ENODEV;

	/* Filter out flags not applicable to multifunction */
	acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);

	return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
#else
	return -ENODEV;
#endif
}

static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
{
	/*
	 * Effectively selects all downstream ports for whole ThunderX 1
	 * family by 0xf800 mask (which represents 8 SoCs), while the lower
	 * bits of device ID are used to indicate which subdevice is used
	 * within the SoC.
	 */
	return (pci_is_pcie(dev) &&
		(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
		((dev->device & 0xf800) == 0xa000));
}

static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * Cavium root ports don't advertise an ACS capability.  However,
	 * the RTL internally implements similar protection as if ACS had
	 * Request Redirection, Completion Redirection, Source Validation,
	 * and Upstream Forwarding features enabled.  Assert that the
	 * hardware implements and enables equivalent ACS functionality for
	 * these flags.
	 */
	acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);

	if (!pci_quirk_cavium_acs_match(dev))
		return -ENOTTY;

	return acs_flags ? 0 : 1;
}

static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
	 * transactions with others, allowing masking out these bits as if they
	 * were unimplemented in the ACS capability.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

/*
 * Many Intel PCH root ports do provide ACS-like features to disable peer
 * transactions and validate bus numbers in requests, but do not provide an
 * actual PCIe ACS capability.  This is the list of device IDs known to fall
 * into that category as provided by Intel in Red Hat bugzilla 1037684.
 */
static const u16 pci_quirk_intel_pch_acs_ids[] = {
	/* Ibexpeak PCH */
	0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
	0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
	/* Cougarpoint PCH */
	0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
	0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
	/* Pantherpoint PCH */
	0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
	0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
	/* Lynxpoint-H PCH */
	0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
	0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
	/* Lynxpoint-LP PCH */
	0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
	0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
	/* Wildcat PCH */
	0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
	0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
	/* Patsburg (X79) PCH */
	0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
	/* Wellsburg (X99) PCH */
	0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
	0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
	/* Lynx Point (9 series) PCH */
	0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
};

static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
{
	int i;

	/* Filter out a few obvious non-matches first */
	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return false;

	for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
		if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
			return true;

	return false;
}

#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)

static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
{
	u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
		    INTEL_PCH_ACS_FLAGS : 0;

	if (!pci_quirk_intel_pch_acs_match(dev))
		return -ENOTTY;

	return acs_flags & ~flags ? 0 : 1;
}

/*
 * These QCOM root ports do provide ACS-like features to disable peer
 * transactions and validate bus numbers in requests, but do not provide an
 * actual PCIe ACS capability.  Hardware supports source validation but it
 * will report the issue as Completer Abort instead of ACS Violation.
 * Hardware doesn't support peer-to-peer and each root port is a root
 * complex with unique segment numbers.  It is not possible for one root
 * port to pass traffic to another root port.  All PCIe transactions are
 * terminated inside the root port.
 */
static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
{
	u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
	int ret = acs_flags & ~flags ? 0 : 1;

	pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);

	return ret;
}

static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
{
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return -ENOTTY;

	/*
	 * Amazon's Annapurna Labs root ports don't include an ACS capability,
	 * but do include ACS-like functionality. The hardware doesn't support
	 * peer-to-peer transactions via the root port and each has a unique
	 * segment number.
	 *
	 * Additionally, the root ports cannot send traffic to each other.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

/*
 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
 * 7.16 ACS Extended Capability).  The bit definitions are correct, but the
 * control register is at offset 8 instead of 6 and we should probably use
 * dword accesses to them.  This applies to the following PCI Device IDs, as
 * found in volume 1 of the datasheet[2]:
 *
 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
 *
 * N.B. This doesn't fix what lspci shows.
 *
 * The 100 series chipset specification update includes this as errata #23[3].
 *
 * The 200 series chipset (Union Point) has the same bug according to the
 * specification update (Intel 200 Series Chipset Family Platform Controller
 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
 * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
 * chipset include:
 *
 * 0xa290-0xa29f PCI Express Root port #{0-16}
 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
 *
 * Mobile chipsets are also affected, 7th & 8th Generation
 * Specification update confirms ACS errata 22, status no fix: (7th Generation
 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
 * Processor Family I/O for U Quad Core Platforms Specification Update,
 * August 2017, Revision 002, Document#: 334660-002)[6]
 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
 *
 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
 *
 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
 */
static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
{
	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return false;

	switch (dev->device) {
	case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
	case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
	case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
		return true;
	}

	return false;
}

#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)

static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	/* see pci_acs_flags_enabled() */
	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	acs_flags &= (cap | PCI_ACS_EC);

	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	return acs_flags & ~ctrl ? 0 : 1;
}

static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * SV, TB, and UF are not relevant to multifunction endpoints.
	 *
	 * Multifunction devices are only required to implement RR, CR, and DT
	 * in their ACS capability if they support peer-to-peer transactions.
	 * Devices matching this quirk have been verified by the vendor to not
	 * perform peer-to-peer with other functions, allowing us to mask out
	 * these bits as if they were unimplemented in the ACS capability.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);

	return acs_flags ? 0 : 1;
}

static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * iProc PAXB Root Ports don't advertise an ACS capability, but
	 * they do not allow peer-to-peer transactions between Root Ports.
	 * Allow each Root Port to be in a separate IOMMU group by masking
	 * SV/RR/CR/UF bits.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

static const struct pci_dev_acs_enabled {
	u16 vendor;
	u16 device;
	int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
} pci_dev_acs_enabled[] = {
	{ PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
	/* 82580 */
	{ PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
	/* 82576 */
	{ PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
	/* 82575 */
	{ PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
	/* I350 */
	{ PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
	/* 82571 (Quads omitted due to non-ACS switch) */
	{ PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
	/* I219 */
	{ PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
	/* QCOM QDF2xxx root ports */
	{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
	{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
	/* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
	{ PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
	/* Intel PCH root ports */
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
	{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
	/* Cavium ThunderX */
	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
	/* APM X-Gene */
	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
	/* Ampere Computing */
	{ PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
	/* Amazon Annapurna Labs */
	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
	{ 0 }
};

int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
{
	const struct pci_dev_acs_enabled *i;
	int ret;

	/*
	 * Allow devices that do not expose standard PCIe ACS capabilities
	 * or control to indicate their support here.  Multi-function express
	 * devices which do not allow internal peer-to-peer between functions,
	 * but do not implement PCIe ACS may wish to return true here.
	 */
	for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
		if ((i->vendor == dev->vendor ||
		     i->vendor == (u16)PCI_ANY_ID) &&
		    (i->device == dev->device ||
		     i->device == (u16)PCI_ANY_ID)) {
			ret = i->acs_enabled(dev, acs_flags);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

/* Config space offset of Root Complex Base Address register */
#define INTEL_LPC_RCBA_REG 0xf0
/* 31:14 RCBA address */
#define INTEL_LPC_RCBA_MASK 0xffffc000
/* RCBA Enable */
#define INTEL_LPC_RCBA_ENABLE (1 << 0)

/* Backbone Scratch Pad Register */
#define INTEL_BSPR_REG 0x1104
/* Backbone Peer Non-Posted Disable */
#define INTEL_BSPR_REG_BPNPD (1 << 8)
/* Backbone Peer Posted Disable */
#define INTEL_BSPR_REG_BPPD  (1 << 9)

/* Upstream Peer Decode Configuration Register */
#define INTEL_UPDCR_REG 0x1114
/* 5:0 Peer Decode Enable bits */
#define INTEL_UPDCR_REG_MASK 0x3f

static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
{
	u32 rcba, bspr, updcr;
	void __iomem *rcba_mem;

	/*
	 * Read the RCBA register from the LPC (D31:F0).  PCH root ports
	 * are D28:F* and therefore get probed before LPC, thus we can't
	 * use pci_get_slot()/pci_read_config_dword() here.
	 */
	pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
				  INTEL_LPC_RCBA_REG, &rcba);
	if (!(rcba & INTEL_LPC_RCBA_ENABLE))
		return -EINVAL;

	rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
				   PAGE_ALIGN(INTEL_UPDCR_REG));
	if (!rcba_mem)
		return -ENOMEM;

	/*
	 * The BSPR can disallow peer cycles, but it's set by soft strap and
	 * therefore read-only.  If both posted and non-posted peer cycles are
	 * disallowed, we're ok.  If either are allowed, then we need to use
	 * the UPDCR to disable peer decodes for each port.  This provides the
	 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
	 */
	bspr = readl(rcba_mem + INTEL_BSPR_REG);
	bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
	if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
		updcr = readl(rcba_mem + INTEL_UPDCR_REG);
		if (updcr & INTEL_UPDCR_REG_MASK) {
			pci_info(dev, "Disabling UPDCR peer decodes\n");
			updcr &= ~INTEL_UPDCR_REG_MASK;
			writel(updcr, rcba_mem + INTEL_UPDCR_REG);
		}
	}

	iounmap(rcba_mem);
	return 0;
}

/* Miscellaneous Port Configuration register */
#define INTEL_MPC_REG 0xd8
/* MPC: Invalid Receive Bus Number Check Enable */
#define INTEL_MPC_REG_IRBNCE (1 << 26)

static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
{
	u32 mpc;

	/*
	 * When enabled, the IRBNCE bit of the MPC register enables the
	 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
	 * ensures that requester IDs fall within the bus number range
	 * of the bridge.  Enable if not already.
	 */
	pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
	if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
		pci_info(dev, "Enabling MPC IRBNCE\n");
		mpc |= INTEL_MPC_REG_IRBNCE;
		pci_write_config_word(dev, INTEL_MPC_REG, mpc);
	}
}

static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
{
	if (!pci_quirk_intel_pch_acs_match(dev))
		return -ENOTTY;

	if (pci_quirk_enable_intel_lpc_acs(dev)) {
		pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
		return 0;
	}

	pci_quirk_enable_intel_rp_mpc_acs(dev);

	dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;

	pci_info(dev, "Intel PCH root port ACS workaround enabled\n");

	return 0;
}

static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	ctrl |= (cap & PCI_ACS_SV);
	ctrl |= (cap & PCI_ACS_RR);
	ctrl |= (cap & PCI_ACS_CR);
	ctrl |= (cap & PCI_ACS_UF);

	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);

	pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");

	return 0;
}

static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);

	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);

	pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");

	return 0;
}

static const struct pci_dev_acs_ops {
	u16 vendor;
	u16 device;
	int (*enable_acs)(struct pci_dev *dev);
	int (*disable_acs_redir)(struct pci_dev *dev);
} pci_dev_acs_ops[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	    .enable_acs = pci_quirk_enable_intel_pch_acs,
	},
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	    .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
	    .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
	},
};

int pci_dev_specific_enable_acs(struct pci_dev *dev)
{
	const struct pci_dev_acs_ops *p;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
		p = &pci_dev_acs_ops[i];
		if ((p->vendor == dev->vendor ||
		     p->vendor == (u16)PCI_ANY_ID) &&
		    (p->device == dev->device ||
		     p->device == (u16)PCI_ANY_ID) &&
		    p->enable_acs) {
			ret = p->enable_acs(dev);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
{
	const struct pci_dev_acs_ops *p;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
		p = &pci_dev_acs_ops[i];
		if ((p->vendor == dev->vendor ||
		     p->vendor == (u16)PCI_ANY_ID) &&
		    (p->device == dev->device ||
		     p->device == (u16)PCI_ANY_ID) &&
		    p->disable_acs_redir) {
			ret = p->disable_acs_redir(dev);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

/*
 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
 * QuickAssist Technology (QAT) is prematurely terminated in hardware.  The
 * Next Capability pointer in the MSI Capability Structure should point to
 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
 * the list.
 */
static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
{
	int pos, i = 0;
	u8 next_cap;
	u16 reg16, *cap;
	struct pci_cap_saved_state *state;

	/* Bail if the hardware bug is fixed */
	if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
		return;

	/* Bail if MSI Capability Structure is not found for some reason */
	pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
	if (!pos)
		return;

	/*
	 * Bail if Next Capability pointer in the MSI Capability Structure
	 * is not the expected incorrect 0x00.
	 */
	pci_read_config_byte(pdev, pos + 1, &next_cap);
	if (next_cap)
		return;

	/*
	 * PCIe Capability Structure is expected to be at 0x50 and should
	 * terminate the list (Next Capability pointer is 0x00).  Verify
	 * Capability Id and Next Capability pointer is as expected.
	 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
	 * to correctly set kernel data structures which have already been
	 * set incorrectly due to the hardware bug.
	 */
	pos = 0x50;
	pci_read_config_word(pdev, pos, &reg16);
	if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
		u32 status;
#ifndef PCI_EXP_SAVE_REGS
#define PCI_EXP_SAVE_REGS     7
#endif
		int size = PCI_EXP_SAVE_REGS * sizeof(u16);

		pdev->pcie_cap = pos;
		pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
		pdev->pcie_flags_reg = reg16;
		pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
		pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;

		pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
		if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
		    PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
			pdev->cfg_size = PCI_CFG_SPACE_SIZE;

		if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
			return;

		/* Save PCIe cap */
		state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
		if (!state)
			return;

		state->cap.cap_nr = PCI_CAP_ID_EXP;
		state->cap.cap_extended = 0;
		state->cap.size = size;
		cap = (u16 *)&state->cap.data[0];
		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_RTCTL,  &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
		hlist_add_head(&state->next, &pdev->saved_cap_space);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);

/* FLR may cause some 82579 devices to hang */
static void quirk_intel_no_flr(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);

static void quirk_no_ext_tags(struct pci_dev *pdev)
{
	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);

	if (!bridge)
		return;

	bridge->no_ext_tags = 1;
	pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");

	pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);

#ifdef CONFIG_PCI_ATS
/*
 * Some devices have a broken ATS implementation causing IOMMU stalls.
 * Don't use ATS for those devices.
 */
static void quirk_no_ats(struct pci_dev *pdev)
{
	pci_info(pdev, "disabling ATS (broken on this device)\n");
	pdev->ats_cap = 0;
}

/* AMD Stoney platform GPU */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
#endif /* CONFIG_PCI_ATS */

/* Freescale PCIe doesn't support MSI in RC mode */
static void quirk_fsl_no_msi(struct pci_dev *pdev)
{
	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
		pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);

/*
 * Although not allowed by the spec, some multi-function devices have
 * dependencies of one function (consumer) on another (supplier).  For the
 * consumer to work in D0, the supplier must also be in D0.  Create a
 * device link from the consumer to the supplier to enforce this
 * dependency.  Runtime PM is allowed by default on the consumer to prevent
 * it from permanently keeping the supplier awake.
 */
static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
				   unsigned int supplier, unsigned int class,
				   unsigned int class_shift)
{
	struct pci_dev *supplier_pdev;

	if (PCI_FUNC(pdev->devfn) != consumer)
		return;

	supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
				pdev->bus->number,
				PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
	if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
		pci_dev_put(supplier_pdev);
		return;
	}

	if (device_link_add(&pdev->dev, &supplier_pdev->dev,
			    DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
		pci_info(pdev, "D0 power state depends on %s\n",
			 pci_name(supplier_pdev));
	else
		pci_err(pdev, "Cannot enforce power dependency on %s\n",
			pci_name(supplier_pdev));

	pm_runtime_allow(&pdev->dev);
	pci_dev_put(supplier_pdev);
}

/*
 * Create device link for GPUs with integrated HDA controller for streaming
 * audio to attached displays.
 */
static void quirk_gpu_hda(struct pci_dev *hda)
{
	pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);

/*
 * Create device link for NVIDIA GPU with integrated USB xHCI Host
 * controller to VGA.
 */
static void quirk_gpu_usb(struct pci_dev *usb)
{
	pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);

/*
 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
 * to VGA. Currently there is no class code defined for UCSI device over PCI
 * so using UNKNOWN class for now and it will be updated when UCSI
 * over PCI gets a class code.
 */
#define PCI_CLASS_SERIAL_UNKNOWN	0x0c80
static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
{
	pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_SERIAL_UNKNOWN, 8,
			      quirk_gpu_usb_typec_ucsi);

/*
 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
 * disabled.  https://devtalk.nvidia.com/default/topic/1024022
 */
static void quirk_nvidia_hda(struct pci_dev *gpu)
{
	u8 hdr_type;
	u32 val;

	/* There was no integrated HDA controller before MCP89 */
	if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
		return;

	/* Bit 25 at offset 0x488 enables the HDA controller */
	pci_read_config_dword(gpu, 0x488, &val);
	if (val & BIT(25))
		return;

	pci_info(gpu, "Enabling HDA controller\n");
	pci_write_config_dword(gpu, 0x488, val | BIT(25));

	/* The GPU becomes a multi-function device when the HDA is enabled */
	pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
	gpu->multifunction = !!(hdr_type & 0x80);
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			       PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			       PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);

/*
 * Some IDT switches incorrectly flag an ACS Source Validation error on
 * completions for config read requests even though PCIe r4.0, sec
 * 6.12.1.1, says that completions are never affected by ACS Source
 * Validation.  Here's the text of IDT 89H32H8G3-YC, erratum #36:
 *
 *   Item #36 - Downstream port applies ACS Source Validation to Completions
 *   Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
 *   completions are never affected by ACS Source Validation.  However,
 *   completions received by a downstream port of the PCIe switch from a
 *   device that has not yet captured a PCIe bus number are incorrectly
 *   dropped by ACS Source Validation by the switch downstream port.
 *
 * The workaround suggested by IDT is to issue a config write to the
 * downstream device before issuing the first config read.  This allows the
 * downstream device to capture its bus and device numbers (see PCIe r4.0,
 * sec 2.2.9), thus avoiding the ACS error on the completion.
 *
 * However, we don't know when the device is ready to accept the config
 * write, so we do config reads until we receive a non-Config Request Retry
 * Status, then do the config write.
 *
 * To avoid hitting the erratum when doing the config reads, we disable ACS
 * SV around this process.
 */
int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
{
	int pos;
	u16 ctrl = 0;
	bool found;
	struct pci_dev *bridge = bus->self;

	pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);

	/* Disable ACS SV before initial config reads */
	if (pos) {
		pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
		if (ctrl & PCI_ACS_SV)
			pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
					      ctrl & ~PCI_ACS_SV);
	}

	found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);

	/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
	if (found)
		pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);

	/* Re-enable ACS_SV if it was previously enabled */
	if (ctrl & PCI_ACS_SV)
		pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);

	return found;
}

/*
 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
 * NT endpoints via the internal switch fabric. These IDs replace the
 * originating requestor ID TLPs which access host memory on peer NTB
 * ports. Therefore, all proxy IDs must be aliased to the NTB device
 * to permit access when the IOMMU is turned on.
 */
static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
{
	void __iomem *mmio;
	struct ntb_info_regs __iomem *mmio_ntb;
	struct ntb_ctrl_regs __iomem *mmio_ctrl;
	u64 partition_map;
	u8 partition;
	int pp;

	if (pci_enable_device(pdev)) {
		pci_err(pdev, "Cannot enable Switchtec device\n");
		return;
	}

	mmio = pci_iomap(pdev, 0, 0);
	if (mmio == NULL) {
		pci_disable_device(pdev);
		pci_err(pdev, "Cannot iomap Switchtec device\n");
		return;
	}

	pci_info(pdev, "Setting Switchtec proxy ID aliases\n");

	mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
	mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;

	partition = ioread8(&mmio_ntb->partition_id);

	partition_map = ioread32(&mmio_ntb->ep_map);
	partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
	partition_map &= ~(1ULL << partition);

	for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
		struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
		u32 table_sz = 0;
		int te;

		if (!(partition_map & (1ULL << pp)))
			continue;

		pci_dbg(pdev, "Processing partition %d\n", pp);

		mmio_peer_ctrl = &mmio_ctrl[pp];

		table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
		if (!table_sz) {
			pci_warn(pdev, "Partition %d table_sz 0\n", pp);
			continue;
		}

		if (table_sz > 512) {
			pci_warn(pdev,
				 "Invalid Switchtec partition %d table_sz %d\n",
				 pp, table_sz);
			continue;
		}

		for (te = 0; te < table_sz; te++) {
			u32 rid_entry;
			u8 devfn;

			rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
			devfn = (rid_entry >> 1) & 0xFF;
			pci_dbg(pdev,
				"Aliasing Partition %d Proxy ID %02x.%d\n",
				pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
			pci_add_dma_alias(pdev, devfn);
		}
	}

	pci_iounmap(pdev, mmio);
	pci_disable_device(pdev);
}
#define SWITCHTEC_QUIRK(vid) \
	DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
		PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)

SWITCHTEC_QUIRK(0x8531);  /* PFX 24xG3 */
SWITCHTEC_QUIRK(0x8532);  /* PFX 32xG3 */
SWITCHTEC_QUIRK(0x8533);  /* PFX 48xG3 */
SWITCHTEC_QUIRK(0x8534);  /* PFX 64xG3 */
SWITCHTEC_QUIRK(0x8535);  /* PFX 80xG3 */
SWITCHTEC_QUIRK(0x8536);  /* PFX 96xG3 */
SWITCHTEC_QUIRK(0x8541);  /* PSX 24xG3 */
SWITCHTEC_QUIRK(0x8542);  /* PSX 32xG3 */
SWITCHTEC_QUIRK(0x8543);  /* PSX 48xG3 */
SWITCHTEC_QUIRK(0x8544);  /* PSX 64xG3 */
SWITCHTEC_QUIRK(0x8545);  /* PSX 80xG3 */
SWITCHTEC_QUIRK(0x8546);  /* PSX 96xG3 */
SWITCHTEC_QUIRK(0x8551);  /* PAX 24XG3 */
SWITCHTEC_QUIRK(0x8552);  /* PAX 32XG3 */
SWITCHTEC_QUIRK(0x8553);  /* PAX 48XG3 */
SWITCHTEC_QUIRK(0x8554);  /* PAX 64XG3 */
SWITCHTEC_QUIRK(0x8555);  /* PAX 80XG3 */
SWITCHTEC_QUIRK(0x8556);  /* PAX 96XG3 */
SWITCHTEC_QUIRK(0x8561);  /* PFXL 24XG3 */
SWITCHTEC_QUIRK(0x8562);  /* PFXL 32XG3 */
SWITCHTEC_QUIRK(0x8563);  /* PFXL 48XG3 */
SWITCHTEC_QUIRK(0x8564);  /* PFXL 64XG3 */
SWITCHTEC_QUIRK(0x8565);  /* PFXL 80XG3 */
SWITCHTEC_QUIRK(0x8566);  /* PFXL 96XG3 */
SWITCHTEC_QUIRK(0x8571);  /* PFXI 24XG3 */
SWITCHTEC_QUIRK(0x8572);  /* PFXI 32XG3 */
SWITCHTEC_QUIRK(0x8573);  /* PFXI 48XG3 */
SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */

/*
 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
 * not always reset the secondary Nvidia GPU between reboots if the system
 * is configured to use Hybrid Graphics mode.  This results in the GPU
 * being left in whatever state it was in during the *previous* boot, which
 * causes spurious interrupts from the GPU, which in turn causes us to
 * disable the wrong IRQ and end up breaking the touchpad.  Unsurprisingly,
 * this also completely breaks nouveau.
 *
 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
 * clean state and fixes all these issues.
 *
 * When the machine is configured in Dedicated display mode, the issue
 * doesn't occur.  Fortunately the GPU advertises NoReset+ when in this
 * mode, so we can detect that and avoid resetting it.
 */
static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
{
	void __iomem *map;
	int ret;

	if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
	    pdev->subsystem_device != 0x222e ||
	    !pdev->reset_fn)
		return;

	if (pci_enable_device_mem(pdev))
		return;

	/*
	 * Based on nvkm_device_ctor() in
	 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
	 */
	map = pci_iomap(pdev, 0, 0x23000);
	if (!map) {
		pci_err(pdev, "Can't map MMIO space\n");
		goto out_disable;
	}

	/*
	 * Make sure the GPU looks like it's been POSTed before resetting
	 * it.
	 */
	if (ioread32(map + 0x2240c) & 0x2) {
		pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
		ret = pci_reset_bus(pdev);
		if (ret < 0)
			pci_err(pdev, "Failed to reset GPU: %d\n", ret);
	}

	iounmap(map);
out_disable:
	pci_disable_device(pdev);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
			      PCI_CLASS_DISPLAY_VGA, 8,
			      quirk_reset_lenovo_thinkpad_p50_nvgpu);

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Dominik Brodowski]

[-- Attachment #1: Type: text/plain, Size: 597 bytes --]

The patch doesn't seem to have been applied correctly (using the patch(1)
utility). Attached is the file how it should look like.

	Dominik

On Fri, Oct 25, 2019 at 01:38:46PM +1100, Michael . wrote:
> Here's the resulting output of the failed compilation of 5.4rc1 with
> the patch applied to quirks.c:
>  CC      drivers/pci/quirks.o
> drivers/pci/quirks.c:3039:1: error: expected identifier or ‘(’ before ‘-’ token
>  3039 | -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
>       | ^
> drivers/pci/quirks.c:3068:1: error: expected identifier or ‘(’ before ‘-’ token


[-- Attachment #2: quirks.c --]
[-- Type: text/plain, Size: 192701 bytes --]

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains work-arounds for many known PCI hardware bugs.
 * Devices present only on certain architectures (host bridges et cetera)
 * should be handled in arch-specific code.
 *
 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
 *
 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
 *
 * Init/reset quirks for USB host controllers should be in the USB quirks
 * file, where their drivers can use them.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/switchtec.h>
#include <asm/dma.h>	/* isa_dma_bridge_buggy */
#include "pci.h"

static ktime_t fixup_debug_start(struct pci_dev *dev,
				 void (*fn)(struct pci_dev *dev))
{
	if (initcall_debug)
		pci_info(dev, "calling  %pS @ %i\n", fn, task_pid_nr(current));

	return ktime_get();
}

static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
			       void (*fn)(struct pci_dev *dev))
{
	ktime_t delta, rettime;
	unsigned long long duration;

	rettime = ktime_get();
	delta = ktime_sub(rettime, calltime);
	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
	if (initcall_debug || duration > 10000)
		pci_info(dev, "%pS took %lld usecs\n", fn, duration);
}

static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
			  struct pci_fixup *end)
{
	ktime_t calltime;

	for (; f < end; f++)
		if ((f->class == (u32) (dev->class >> f->class_shift) ||
		     f->class == (u32) PCI_ANY_ID) &&
		    (f->vendor == dev->vendor ||
		     f->vendor == (u16) PCI_ANY_ID) &&
		    (f->device == dev->device ||
		     f->device == (u16) PCI_ANY_ID)) {
			void (*hook)(struct pci_dev *dev);
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
			hook = offset_to_ptr(&f->hook_offset);
#else
			hook = f->hook;
#endif
			calltime = fixup_debug_start(dev, hook);
			hook(dev);
			fixup_debug_report(dev, calltime, hook);
		}
}

extern struct pci_fixup __start_pci_fixups_early[];
extern struct pci_fixup __end_pci_fixups_early[];
extern struct pci_fixup __start_pci_fixups_header[];
extern struct pci_fixup __end_pci_fixups_header[];
extern struct pci_fixup __start_pci_fixups_final[];
extern struct pci_fixup __end_pci_fixups_final[];
extern struct pci_fixup __start_pci_fixups_enable[];
extern struct pci_fixup __end_pci_fixups_enable[];
extern struct pci_fixup __start_pci_fixups_resume[];
extern struct pci_fixup __end_pci_fixups_resume[];
extern struct pci_fixup __start_pci_fixups_resume_early[];
extern struct pci_fixup __end_pci_fixups_resume_early[];
extern struct pci_fixup __start_pci_fixups_suspend[];
extern struct pci_fixup __end_pci_fixups_suspend[];
extern struct pci_fixup __start_pci_fixups_suspend_late[];
extern struct pci_fixup __end_pci_fixups_suspend_late[];

static bool pci_apply_fixup_final_quirks;

void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
{
	struct pci_fixup *start, *end;

	switch (pass) {
	case pci_fixup_early:
		start = __start_pci_fixups_early;
		end = __end_pci_fixups_early;
		break;

	case pci_fixup_header:
		start = __start_pci_fixups_header;
		end = __end_pci_fixups_header;
		break;

	case pci_fixup_final:
		if (!pci_apply_fixup_final_quirks)
			return;
		start = __start_pci_fixups_final;
		end = __end_pci_fixups_final;
		break;

	case pci_fixup_enable:
		start = __start_pci_fixups_enable;
		end = __end_pci_fixups_enable;
		break;

	case pci_fixup_resume:
		start = __start_pci_fixups_resume;
		end = __end_pci_fixups_resume;
		break;

	case pci_fixup_resume_early:
		start = __start_pci_fixups_resume_early;
		end = __end_pci_fixups_resume_early;
		break;

	case pci_fixup_suspend:
		start = __start_pci_fixups_suspend;
		end = __end_pci_fixups_suspend;
		break;

	case pci_fixup_suspend_late:
		start = __start_pci_fixups_suspend_late;
		end = __end_pci_fixups_suspend_late;
		break;

	default:
		/* stupid compiler warning, you would think with an enum... */
		return;
	}
	pci_do_fixups(dev, start, end);
}
EXPORT_SYMBOL(pci_fixup_device);

static int __init pci_apply_final_quirks(void)
{
	struct pci_dev *dev = NULL;
	u8 cls = 0;
	u8 tmp;

	if (pci_cache_line_size)
		pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);

	pci_apply_fixup_final_quirks = true;
	for_each_pci_dev(dev) {
		pci_fixup_device(pci_fixup_final, dev);
		/*
		 * If arch hasn't set it explicitly yet, use the CLS
		 * value shared by all PCI devices.  If there's a
		 * mismatch, fall back to the default value.
		 */
		if (!pci_cache_line_size) {
			pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
			if (!cls)
				cls = tmp;
			if (!tmp || cls == tmp)
				continue;

			pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
			         cls << 2, tmp << 2,
				 pci_dfl_cache_line_size << 2);
			pci_cache_line_size = pci_dfl_cache_line_size;
		}
	}

	if (!pci_cache_line_size) {
		pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
			pci_dfl_cache_line_size << 2);
		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
	}

	return 0;
}
fs_initcall_sync(pci_apply_final_quirks);

/*
 * Decoding should be disabled for a PCI device during BAR sizing to avoid
 * conflict. But doing so may cause problems on host bridge and perhaps other
 * key system devices. For devices that need to have mmio decoding always-on,
 * we need to set the dev->mmio_always_on bit.
 */
static void quirk_mmio_always_on(struct pci_dev *dev)
{
	dev->mmio_always_on = 1;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
				PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);

/*
 * The Mellanox Tavor device gives false positive parity errors.  Mark this
 * device with a broken_parity_status to allow PCI scanning code to "skip"
 * this now blacklisted device.
 */
static void quirk_mellanox_tavor(struct pci_dev *dev)
{
	dev->broken_parity_status = 1;	/* This device gives false positives */
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);

/*
 * Deal with broken BIOSes that neglect to enable passive release,
 * which can cause problems in combination with the 82441FX/PPro MTRRs
 */
static void quirk_passive_release(struct pci_dev *dev)
{
	struct pci_dev *d = NULL;
	unsigned char dlc;

	/*
	 * We have to make sure a particular bit is set in the PIIX3
	 * ISA bridge, so we have to go out and find it.
	 */
	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
		pci_read_config_byte(d, 0x82, &dlc);
		if (!(dlc & 1<<1)) {
			pci_info(d, "PIIX3: Enabling Passive Release\n");
			dlc |= 1<<1;
			pci_write_config_byte(d, 0x82, dlc);
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);

/*
 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
 * workaround but VIA don't answer queries. If you happen to have good
 * contacts at VIA ask them for me please -- Alan
 *
 * This appears to be BIOS not version dependent. So presumably there is a
 * chipset level fix.
 */
static void quirk_isa_dma_hangs(struct pci_dev *dev)
{
	if (!isa_dma_bridge_buggy) {
		isa_dma_bridge_buggy = 1;
		pci_info(dev, "Activating ISA DMA hang workarounds\n");
	}
}
/*
 * It's not totally clear which chipsets are the problematic ones.  We know
 * 82C586 and 82C596 variants are affected.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_0,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C596,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1533,		quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_1,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs);

/*
 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
 * for some HT machines to use C4 w/o hanging.
 */
static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
{
	u32 pmbase;
	u16 pm1a;

	pci_read_config_dword(dev, 0x40, &pmbase);
	pmbase = pmbase & 0xff80;
	pm1a = inw(pmbase);

	if (pm1a & 0x10) {
		pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
		outw(0x10, pmbase);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);

/* Chipsets where PCI->PCI transfers vanish or hang */
static void quirk_nopcipci(struct pci_dev *dev)
{
	if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
		pci_info(dev, "Disabling direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_FAIL;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci);

static void quirk_nopciamd(struct pci_dev *dev)
{
	u8 rev;
	pci_read_config_byte(dev, 0x08, &rev);
	if (rev == 0x13) {
		/* Erratum 24 */
		pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
		pci_pci_problems |= PCIAGP_FAIL;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopciamd);

/* Triton requires workarounds to be used by the drivers */
static void quirk_triton(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_TRITON;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437VX,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439,	quirk_triton);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439TX,	quirk_triton);

/*
 * VIA Apollo KT133 needs PCI latency patch
 * Made according to a Windows driver-based patch by George E. Breese;
 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
 * which Mr Breese based his work.
 *
 * Updated based on further information from the site and also on
 * information provided by VIA
 */
static void quirk_vialatency(struct pci_dev *dev)
{
	struct pci_dev *p;
	u8 busarb;

	/*
	 * Ok, we have a potential problem chipset here. Now see if we have
	 * a buggy southbridge.
	 */
	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
	if (p != NULL) {

		/*
		 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
		 * thanks Dan Hollis.
		 * Check for buggy part revisions
		 */
		if (p->revision < 0x40 || p->revision > 0x42)
			goto exit;
	} else {
		p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
		if (p == NULL)	/* No problem parts */
			goto exit;

		/* Check for buggy part revisions */
		if (p->revision < 0x10 || p->revision > 0x12)
			goto exit;
	}

	/*
	 * Ok we have the problem. Now set the PCI master grant to occur
	 * every master grant. The apparent bug is that under high PCI load
	 * (quite common in Linux of course) you can get data loss when the
	 * CPU is held off the bus for 3 bus master requests.  This happens
	 * to include the IDE controllers....
	 *
	 * VIA only apply this fix when an SB Live! is present but under
	 * both Linux and Windows this isn't enough, and we have seen
	 * corruption without SB Live! but with things like 3 UDMA IDE
	 * controllers. So we ignore that bit of the VIA recommendation..
	 */
	pci_read_config_byte(dev, 0x76, &busarb);

	/*
	 * Set bit 4 and bit 5 of byte 76 to 0x01
	 * "Master priority rotation on every PCI master grant"
	 */
	busarb &= ~(1<<5);
	busarb |= (1<<4);
	pci_write_config_byte(dev, 0x76, busarb);
	pci_info(dev, "Applying VIA southbridge workaround\n");
exit:
	pci_dev_put(p);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
/* Must restore this on a resume from RAM */
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);

/* VIA Apollo VP3 needs ETBF on BT848/878 */
static void quirk_viaetbf(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_VIAETBF;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_viaetbf);

static void quirk_vsfx(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_VSFX;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx);

/*
 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
 * space. Latency must be set to 0xA and Triton workaround applied too.
 * [Info kindly provided by ALi]
 */
static void quirk_alimagik(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1647,		quirk_alimagik);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagik);

/* Natoma has some interesting boundary conditions with Zoran stuff at least */
static void quirk_natoma(struct pci_dev *dev)
{
	if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
		pci_pci_problems |= PCIPCI_NATOMA;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_0,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_1,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_0,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_1,	quirk_natoma);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_2,	quirk_natoma);

/*
 * This chip can cause PCI parity errors if config register 0xA0 is read
 * while DMAs are occurring.
 */
static void quirk_citrine(struct pci_dev *dev)
{
	dev->cfg_size = 0xA0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine);

/*
 * This chip can cause bus lockups if config addresses above 0x600
 * are read or written.
 */
static void quirk_nfp6000(struct pci_dev *dev)
{
	dev->cfg_size = 0x600;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP4000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP5000,	quirk_nfp6000);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000_VF,	quirk_nfp6000);

/*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
static void quirk_extend_bar_to_page(struct pci_dev *dev)
{
	int i;

	for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
		struct resource *r = &dev->resource[i];

		if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
			r->end = PAGE_SIZE - 1;
			r->start = 0;
			r->flags |= IORESOURCE_UNSET;
			pci_info(dev, "expanded BAR %d to page size: %pR\n",
				 i, r);
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);

/*
 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
 * If it's needed, re-allocate the region.
 */
static void quirk_s3_64M(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[0];

	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
		r->flags |= IORESOURCE_UNSET;
		r->start = 0;
		r->end = 0x3ffffff;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_868,		quirk_s3_64M);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_968,		quirk_s3_64M);

static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
		     const char *name)
{
	u32 region;
	struct pci_bus_region bus_region;
	struct resource *res = dev->resource + pos;

	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);

	if (!region)
		return;

	res->name = pci_name(dev);
	res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
	res->flags |=
		(IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
	region &= ~(size - 1);

	/* Convert from PCI bus to resource space */
	bus_region.start = region;
	bus_region.end = region + size - 1;
	pcibios_bus_to_resource(dev->bus, res, &bus_region);

	pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
		 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
}

/*
 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
 * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
 * (which conflicts w/ BAR1's memory range).
 *
 * CS553x's ISA PCI BARs may also be read-only (ref:
 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
 */
static void quirk_cs5536_vsa(struct pci_dev *dev)
{
	static char *name = "CS5536 ISA bridge";

	if (pci_resource_len(dev, 0) != 8) {
		quirk_io(dev, 0,   8, name);	/* SMB */
		quirk_io(dev, 1, 256, name);	/* GPIO */
		quirk_io(dev, 2,  64, name);	/* MFGPT */
		pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
			 name);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);

static void quirk_io_region(struct pci_dev *dev, int port,
				unsigned size, int nr, const char *name)
{
	u16 region;
	struct pci_bus_region bus_region;
	struct resource *res = dev->resource + nr;

	pci_read_config_word(dev, port, &region);
	region &= ~(size - 1);

	if (!region)
		return;

	res->name = pci_name(dev);
	res->flags = IORESOURCE_IO;

	/* Convert from PCI bus to resource space */
	bus_region.start = region;
	bus_region.end = region + size - 1;
	pcibios_bus_to_resource(dev->bus, res, &bus_region);

	if (!pci_claim_resource(dev, nr))
		pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
}

/*
 * ATI Northbridge setups MCE the processor if you even read somewhere
 * between 0x3b0->0x3bb or read 0x3d3
 */
static void quirk_ati_exploding_mce(struct pci_dev *dev)
{
	pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
	/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
	request_region(0x3b0, 0x0C, "RadeonIGP");
	request_region(0x3d3, 0x01, "RadeonIGP");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);

/*
 * In the AMD NL platform, this device ([1022:7912]) has a class code of
 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
 * claim it.
 *
 * But the dwc3 driver is a more specific driver for this device, and we'd
 * prefer to use it instead of xhci. To prevent xhci from claiming the
 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
 * defines as "USB device (not host controller)". The dwc3 driver can then
 * claim it based on its Vendor and Device ID.
 */
static void quirk_amd_nl_class(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	/* Use "USB Device (not host controller)" class */
	pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
	pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
		 class, pdev->class);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
		quirk_amd_nl_class);

/*
 * Synopsys USB 3.x host HAPS platform has a class code of
 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it.  However, these
 * devices should use dwc3-haps driver.  Change these devices' class code to
 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
 * them.
 */
static void quirk_synopsys_haps(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	switch (pdev->device) {
	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
		pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
		pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
			 class, pdev->class);
		break;
	}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
			       PCI_CLASS_SERIAL_USB_XHCI, 0,
			       quirk_synopsys_haps);

/*
 * Let's make the southbridge information explicit instead of having to
 * worry about people probing the ACPI areas, for example.. (Yes, it
 * happens, and if you read the wrong ACPI register it will put the machine
 * to sleep with no way of waking it up again. Bummer).
 *
 * ALI M7101: Two IO regions pointed to by words at
 *	0xE0 (64 bytes of ACPI registers)
 *	0xE2 (32 bytes of SMB registers)
 */
static void quirk_ali7101_acpi(struct pci_dev *dev)
{
	quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
	quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi);

static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
{
	u32 devres;
	u32 mask, size, base;

	pci_read_config_dword(dev, port, &devres);
	if ((devres & enable) != enable)
		return;
	mask = (devres >> 16) & 15;
	base = devres & 0xffff;
	size = 16;
	for (;;) {
		unsigned bit = size >> 1;
		if ((bit & mask) == bit)
			break;
		size = bit;
	}
	/*
	 * For now we only print it out. Eventually we'll want to
	 * reserve it (at least if it's in the 0x1000+ range), but
	 * let's get enough confirmation reports first.
	 */
	base &= -size;
	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
}

static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
{
	u32 devres;
	u32 mask, size, base;

	pci_read_config_dword(dev, port, &devres);
	if ((devres & enable) != enable)
		return;
	base = devres & 0xffff0000;
	mask = (devres & 0x3f) << 16;
	size = 128 << 16;
	for (;;) {
		unsigned bit = size >> 1;
		if ((bit & mask) == bit)
			break;
		size = bit;
	}

	/*
	 * For now we only print it out. Eventually we'll want to
	 * reserve it, but let's get enough confirmation reports first.
	 */
	base &= -size;
	pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
}

/*
 * PIIX4 ACPI: Two IO regions pointed to by longwords at
 *	0x40 (64 bytes of ACPI registers)
 *	0x90 (16 bytes of SMB registers)
 * and a few strange programmable PIIX4 device resources.
 */
static void quirk_piix4_acpi(struct pci_dev *dev)
{
	u32 res_a;

	quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");

	/* Device resource A has enables for some of the other ones */
	pci_read_config_dword(dev, 0x5c, &res_a);

	piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
	piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);

	/* Device resource D is just bitfields for static resources */

	/* Device 12 enabled? */
	if (res_a & (1 << 29)) {
		piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
		piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
	}
	/* Device 13 enabled? */
	if (res_a & (1 << 30)) {
		piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
		piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
	}
	piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
	piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_3,	quirk_piix4_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443MX_3,	quirk_piix4_acpi);

#define ICH_PMBASE	0x40
#define ICH_ACPI_CNTL	0x44
#define  ICH4_ACPI_EN	0x10
#define  ICH6_ACPI_EN	0x80
#define ICH4_GPIOBASE	0x58
#define ICH4_GPIO_CNTL	0x5c
#define  ICH4_GPIO_EN	0x10
#define ICH6_GPIOBASE	0x48
#define ICH6_GPIO_CNTL	0x4c
#define  ICH6_GPIO_EN	0x10

/*
 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
 *	0x40 (128 bytes of ACPI, GPIO & TCO registers)
 *	0x58 (64 bytes of GPIO I/O space)
 */
static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
{
	u8 enable;

	/*
	 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
	 * with low legacy (and fixed) ports. We don't know the decoding
	 * priority and can't tell whether the legacy device or the one created
	 * here is really at that address.  This happens on boards with broken
	 * BIOSes.
	 */
	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
	if (enable & ICH4_ACPI_EN)
		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
				 "ICH4 ACPI/GPIO/TCO");

	pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
	if (enable & ICH4_GPIO_EN)
		quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
				"ICH4 GPIO");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,	quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi);

static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
{
	u8 enable;

	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
	if (enable & ICH6_ACPI_EN)
		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
				 "ICH6 ACPI/GPIO/TCO");

	pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
	if (enable & ICH6_GPIO_EN)
		quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
				"ICH6 GPIO");
}

static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
				    const char *name, int dynsize)
{
	u32 val;
	u32 size, base;

	pci_read_config_dword(dev, reg, &val);

	/* Enabled? */
	if (!(val & 1))
		return;
	base = val & 0xfffc;
	if (dynsize) {
		/*
		 * This is not correct. It is 16, 32 or 64 bytes depending on
		 * register D31:F0:ADh bits 5:4.
		 *
		 * But this gets us at least _part_ of it.
		 */
		size = 16;
	} else {
		size = 128;
	}
	base &= ~(size-1);

	/*
	 * Just print it out for now. We should reserve it after more
	 * debugging.
	 */
	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
}

static void quirk_ich6_lpc(struct pci_dev *dev)
{
	/* Shared ACPI/GPIO decode with all ICH6+ */
	ich6_lpc_acpi_gpio(dev);

	/* ICH6-specific generic IO decode */
	ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
	ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);

static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
				    const char *name)
{
	u32 val;
	u32 mask, base;

	pci_read_config_dword(dev, reg, &val);

	/* Enabled? */
	if (!(val & 1))
		return;

	/* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
	base = val & 0xfffc;
	mask = (val >> 16) & 0xfc;
	mask |= 3;

	/*
	 * Just print it out for now. We should reserve it after more
	 * debugging.
	 */
	pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
}

/* ICH7-10 has the same common LPC generic IO decode registers */
static void quirk_ich7_lpc(struct pci_dev *dev)
{
	/* We share the common ACPI/GPIO decode with ICH6 */
	ich6_lpc_acpi_gpio(dev);

	/* And have 4 ICH7+ generic decodes */
	ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
	ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
	ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
	ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);

/*
 * VIA ACPI: One IO region pointed to by longword at
 *	0x48 or 0x20 (256 bytes of ACPI registers)
 */
static void quirk_vt82c586_acpi(struct pci_dev *dev)
{
	if (dev->revision & 0x10)
		quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
				"vt82c586 ACPI");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_vt82c586_acpi);

/*
 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
 *	0x48 (256 bytes of ACPI registers)
 *	0x70 (128 bytes of hardware monitoring register)
 *	0x90 (16 bytes of SMB registers)
 */
static void quirk_vt82c686_acpi(struct pci_dev *dev)
{
	quirk_vt82c586_acpi(dev);

	quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
				 "vt82c686 HW-mon");

	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi);

/*
 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
 *	0x88 (128 bytes of power management registers)
 *	0xd0 (16 bytes of SMB registers)
 */
static void quirk_vt8235_acpi(struct pci_dev *dev)
{
	quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
	quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);

/*
 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
 * back-to-back: Disable fast back-to-back on the secondary bus segment
 */
static void quirk_xio2000a(struct pci_dev *dev)
{
	struct pci_dev *pdev;
	u16 command;

	pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
	list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
		pci_read_config_word(pdev, PCI_COMMAND, &command);
		if (command & PCI_COMMAND_FAST_BACK)
			pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
			quirk_xio2000a);

#ifdef CONFIG_X86_IO_APIC

#include <asm/io_apic.h>

/*
 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
 * devices to the external APIC.
 *
 * TODO: When we have device-specific interrupt routers, this code will go
 * away from quirks.
 */
static void quirk_via_ioapic(struct pci_dev *dev)
{
	u8 tmp;

	if (nr_ioapics < 1)
		tmp = 0;    /* nothing routed to external APIC */
	else
		tmp = 0x1f; /* all known bits (4-0) routed to external APIC */

	pci_info(dev, "%sbling VIA external APIC routing\n",
	       tmp == 0 ? "Disa" : "Ena");

	/* Offset 0x58: External APIC IRQ output control */
	pci_write_config_byte(dev, 0x58, tmp);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);

/*
 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
 * This leads to doubled level interrupt rates.
 * Set this bit to get rid of cycle wastage.
 * Otherwise uncritical.
 */
static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
{
	u8 misc_control2;
#define BYPASS_APIC_DEASSERT 8

	pci_read_config_byte(dev, 0x5B, &misc_control2);
	if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
		pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
		pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);

/*
 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
 * We check all revs >= B0 (yet not in the pre production!) as the bug
 * is currently marked NoFix
 *
 * We have multiple reports of hangs with this chipset that went away with
 * noapic specified. For the moment we assume it's the erratum. We may be wrong
 * of course. However the advice is demonstrably good even if so.
 */
static void quirk_amd_ioapic(struct pci_dev *dev)
{
	if (dev->revision >= 0x02) {
		pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
		pci_warn(dev, "        : booting with the \"noapic\" option\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);
#endif /* CONFIG_X86_IO_APIC */

#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)

static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
{
	/* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
	if (dev->subsystem_device == 0xa118)
		dev->sriov->link = dev->devfn;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
#endif

/*
 * Some settings of MMRBC can lead to data corruption so block changes.
 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
 */
static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
{
	if (dev->subordinate && dev->revision <= 0x12) {
		pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
			 dev->revision);
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);

/*
 * FIXME: it is questionable that quirk_via_acpi() is needed.  It shows up
 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
 * at all.  Therefore it seems like setting the pci_dev's IRQ to the value
 * of the ACPI SCI interrupt is only done for convenience.
 *	-jgarzik
 */
static void quirk_via_acpi(struct pci_dev *d)
{
	u8 irq;

	/* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
	pci_read_config_byte(d, 0x42, &irq);
	irq &= 0xf;
	if (irq && (irq != 2))
		d->irq = irq;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi);

/* VIA bridges which have VLink */
static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;

static void quirk_via_bridge(struct pci_dev *dev)
{
	/* See what bridge we have and find the device ranges */
	switch (dev->device) {
	case PCI_DEVICE_ID_VIA_82C686:
		/*
		 * The VT82C686 is special; it attaches to PCI and can have
		 * any device number. All its subdevices are functions of
		 * that single device.
		 */
		via_vlink_dev_lo = PCI_SLOT(dev->devfn);
		via_vlink_dev_hi = PCI_SLOT(dev->devfn);
		break;
	case PCI_DEVICE_ID_VIA_8237:
	case PCI_DEVICE_ID_VIA_8237A:
		via_vlink_dev_lo = 15;
		break;
	case PCI_DEVICE_ID_VIA_8235:
		via_vlink_dev_lo = 16;
		break;
	case PCI_DEVICE_ID_VIA_8231:
	case PCI_DEVICE_ID_VIA_8233_0:
	case PCI_DEVICE_ID_VIA_8233A:
	case PCI_DEVICE_ID_VIA_8233C_0:
		via_vlink_dev_lo = 17;
		break;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8231,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233_0,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233A,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233C_0,	quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237A,	quirk_via_bridge);

/*
 * quirk_via_vlink		-	VIA VLink IRQ number update
 * @dev: PCI device
 *
 * If the device we are dealing with is on a PIC IRQ we need to ensure that
 * the IRQ line register which usually is not relevant for PCI cards, is
 * actually written so that interrupts get sent to the right place.
 *
 * We only do this on systems where a VIA south bridge was detected, and
 * only for VIA devices on the motherboard (see quirk_via_bridge above).
 */
static void quirk_via_vlink(struct pci_dev *dev)
{
	u8 irq, new_irq;

	/* Check if we have VLink at all */
	if (via_vlink_dev_lo == -1)
		return;

	new_irq = dev->irq;

	/* Don't quirk interrupts outside the legacy IRQ range */
	if (!new_irq || new_irq > 15)
		return;

	/* Internal device ? */
	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
	    PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
		return;

	/*
	 * This is an internal VLink device on a PIC interrupt. The BIOS
	 * ought to have set this but may not have, so we redo it.
	 */
	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	if (new_irq != irq) {
		pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
			irq, new_irq);
		udelay(15);	/* unknown if delay really needed */
		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);

/*
 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
 * of VT82C597 for backward compatibility.  We need to switch it off to be
 * able to recognize the real type of the chip.
 */
static void quirk_vt82c598_id(struct pci_dev *dev)
{
	pci_write_config_byte(dev, 0xfc, 0);
	pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_vt82c598_id);

/*
 * CardBus controllers have a legacy base address that enables them to
 * respond as i82365 pcmcia controllers.  We don't want them to do this
 * even if the Linux CardBus driver is not loaded, because the Linux i82365
 * driver does not (and should not) handle CardBus.
 */
static void quirk_cardbus_legacy(struct pci_dev *dev)
{
	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);

/*
 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
 * what the designers were smoking but let's not inhale...
 *
 * To be fair to AMD, it follows the spec by default, it's BIOS people who
 * turn it off!
 */
static void quirk_amd_ordering(struct pci_dev *dev)
{
	u32 pcic;
	pci_read_config_dword(dev, 0x4C, &pcic);
	if ((pcic & 6) != 6) {
		pcic |= 6;
		pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
		pci_write_config_dword(dev, 0x4C, pcic);
		pci_read_config_dword(dev, 0x84, &pcic);
		pcic |= (1 << 23);	/* Required in this mode */
		pci_write_config_dword(dev, 0x84, pcic);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);

/*
 * DreamWorks-provided workaround for Dunord I-3000 problem
 *
 * This card decodes and responds to addresses not apparently assigned to
 * it.  We force a larger allocation to ensure that nothing gets put too
 * close to it.
 */
static void quirk_dunord(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[1];

	r->flags |= IORESOURCE_UNSET;
	r->start = 0;
	r->end = 0xffffff;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,	PCI_DEVICE_ID_DUNORD_I3000,	quirk_dunord);

/*
 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
 * decoding (transparent), and does indicate this in the ProgIf.
 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
 */
static void quirk_transparent_bridge(struct pci_dev *dev)
{
	dev->transparent = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82380FB,	quirk_transparent_bridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA,	0x605,	quirk_transparent_bridge);

/*
 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
 * PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1 datasheets
 * found at http://www.national.com/analog for info on what these bits do.
 * <christer@weinigel.se>
 */
static void quirk_mediagx_master(struct pci_dev *dev)
{
	u8 reg;

	pci_read_config_byte(dev, 0x41, &reg);
	if (reg & 2) {
		reg &= ~2;
		pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
			 reg);
		pci_write_config_byte(dev, 0x41, reg);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);

/*
 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
 * in the odd case it is not the results are corruption hence the presence
 * of a Linux check.
 */
static void quirk_disable_pxb(struct pci_dev *pdev)
{
	u16 config;

	if (pdev->revision != 0x04)		/* Only C0 requires this */
		return;
	pci_read_config_word(pdev, 0x40, &config);
	if (config & (1<<6)) {
		config &= ~(1<<6);
		pci_write_config_word(pdev, 0x40, config);
		pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);

static void quirk_amd_ide_mode(struct pci_dev *pdev)
{
	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
	u8 tmp;

	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
	if (tmp == 0x01) {
		pci_read_config_byte(pdev, 0x40, &tmp);
		pci_write_config_byte(pdev, 0x40, tmp|1);
		pci_write_config_byte(pdev, 0x9, 1);
		pci_write_config_byte(pdev, 0xa, 6);
		pci_write_config_byte(pdev, 0x40, tmp);

		pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
		pci_info(pdev, "set SATA to AHCI mode\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);

/* Serverworks CSB5 IDE does not fully support native mode */
static void quirk_svwks_csb5ide(struct pci_dev *pdev)
{
	u8 prog;
	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
	if (prog & 5) {
		prog &= ~5;
		pdev->class &= ~5;
		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
		/* PCI layer will sort out resources */
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);

/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
static void quirk_ide_samemode(struct pci_dev *pdev)
{
	u8 prog;

	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);

	if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
		pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
		prog &= ~5;
		pdev->class &= ~5;
		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);

/* Some ATA devices break if put into D3 */
static void quirk_no_ata_d3(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
}
/* Quirk the legacy ATA devices only. The AHCI ones are ok */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
/* ALi loses some register settings that we cannot then restore */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
   occur when mode detecting */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);

/*
 * This was originally an Alpha-specific thing, but it really fits here.
 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
 */
static void quirk_eisa_bridge(struct pci_dev *dev)
{
	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82375,	quirk_eisa_bridge);

/*
 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
 * is not activated. The myth is that Asus said that they do not want the
 * users to be irritated by just another PCI Device in the Win98 device
 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
 * package 2.7.0 for details)
 *
 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
 * becomes necessary to do this tweak in two steps -- the chosen trigger
 * is either the Host bridge (preferred) or on-board VGA controller.
 *
 * Note that we used to unhide the SMBus that way on Toshiba laptops
 * (Satellite A40 and Tecra M2) but then found that the thermal management
 * was done by SMM code, which could cause unsynchronized concurrent
 * accesses to the SMBus registers, with potentially bad effects. Thus you
 * should be very careful when adding new entries: if SMM is accessing the
 * Intel SMBus, this is a very good reason to leave it hidden.
 *
 * Likewise, many recent laptops use ACPI for thermal management. If the
 * ACPI DSDT code accesses the SMBus, then Linux should not access it
 * natively, and keeping the SMBus hidden is the right thing to do. If you
 * are about to add an entry in the table below, please first disassemble
 * the DSDT and double-check that there is no code accessing the SMBus.
 */
static int asus_hides_smbus;

static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
{
	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
		if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
			switch (dev->subsystem_device) {
			case 0x8025: /* P4B-LX */
			case 0x8070: /* P4B */
			case 0x8088: /* P4B533 */
			case 0x1626: /* L3C notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
			switch (dev->subsystem_device) {
			case 0x80b1: /* P4GE-V */
			case 0x80b2: /* P4PE */
			case 0x8093: /* P4B533-V */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
			switch (dev->subsystem_device) {
			case 0x8030: /* P4T533 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
			switch (dev->subsystem_device) {
			case 0x8070: /* P4G8X Deluxe */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
			switch (dev->subsystem_device) {
			case 0x80c9: /* PU-DLS */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
			switch (dev->subsystem_device) {
			case 0x1751: /* M2N notebook */
			case 0x1821: /* M5N notebook */
			case 0x1897: /* A6L notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x184b: /* W1N notebook */
			case 0x186a: /* M6Ne notebook */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
			switch (dev->subsystem_device) {
			case 0x80f2: /* P4P800-X */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
			switch (dev->subsystem_device) {
			case 0x1882: /* M6V notebook */
			case 0x1977: /* A6VA notebook */
				asus_hides_smbus = 1;
			}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x088C: /* HP Compaq nc8000 */
			case 0x0890: /* HP Compaq nc6000 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
			switch (dev->subsystem_device) {
			case 0x12bc: /* HP D330L */
			case 0x12bd: /* HP D530 */
			case 0x006a: /* HP Compaq nx9500 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
			switch (dev->subsystem_device) {
			case 0x12bf: /* HP xw4100 */
				asus_hides_smbus = 1;
			}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0xC00C: /* Samsung P35 notebook */
				asus_hides_smbus = 1;
		}
	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
			switch (dev->subsystem_device) {
			case 0x0058: /* Compaq Evo N620c */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
			switch (dev->subsystem_device) {
			case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
				/* Motherboard doesn't have Host bridge
				 * subvendor/subdevice IDs, therefore checking
				 * its on-board VGA controller */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
			switch (dev->subsystem_device) {
			case 0x00b8: /* Compaq Evo D510 CMT */
			case 0x00b9: /* Compaq Evo D510 SFF */
			case 0x00ba: /* Compaq Evo D510 USDT */
				/* Motherboard doesn't have Host bridge
				 * subvendor/subdevice IDs and on-board VGA
				 * controller is disabled if an AGP card is
				 * inserted, therefore checking USB UHCI
				 * Controller #1 */
				asus_hides_smbus = 1;
			}
		else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
			switch (dev->subsystem_device) {
			case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
				/* Motherboard doesn't have host bridge
				 * subvendor/subdevice IDs, therefore checking
				 * its on-board VGA controller */
				asus_hides_smbus = 1;
			}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845G_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82850_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82865_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82875_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_7205_0,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7501_MCH,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855PM_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82810_IG3,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_2,	asus_hides_smbus_hostbridge);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82815_CGC,	asus_hides_smbus_hostbridge);

static void asus_hides_smbus_lpc(struct pci_dev *dev)
{
	u16 val;

	if (likely(!asus_hides_smbus))
		return;

	pci_read_config_word(dev, 0xF2, &val);
	if (val & 0x8) {
		pci_write_config_word(dev, 0xF2, val & (~0x8));
		pci_read_config_word(dev, 0xF2, &val);
		if (val & 0x8)
			pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
				 val);
		else
			pci_info(dev, "Enabled i801 SMBus device\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);

/* It appears we just have one such device. If not, we have a warning */
static void __iomem *asus_rcba_base;
static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
{
	u32 rcba;

	if (likely(!asus_hides_smbus))
		return;
	WARN_ON(asus_rcba_base);

	pci_read_config_dword(dev, 0xF0, &rcba);
	/* use bits 31:14, 16 kB aligned */
	asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
	if (asus_rcba_base == NULL)
		return;
}

static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
{
	u32 val;

	if (likely(!asus_hides_smbus || !asus_rcba_base))
		return;

	/* read the Function Disable register, dword mode only */
	val = readl(asus_rcba_base + 0x3418);

	/* enable the SMBus device */
	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
}

static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
{
	if (likely(!asus_hides_smbus || !asus_rcba_base))
		return;

	iounmap(asus_rcba_base);
	asus_rcba_base = NULL;
	pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
}

static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
{
	asus_hides_smbus_lpc_ich6_suspend(dev);
	asus_hides_smbus_lpc_ich6_resume_early(dev);
	asus_hides_smbus_lpc_ich6_resume(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6);
DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_suspend);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume_early);

/* SiS 96x south bridge: BIOS typically hides SMBus device...  */
static void quirk_sis_96x_smbus(struct pci_dev *dev)
{
	u8 val = 0;
	pci_read_config_byte(dev, 0x77, &val);
	if (val & 0x10) {
		pci_info(dev, "Enabling SiS 96x SMBus\n");
		pci_write_config_byte(dev, 0x77, val & ~0x10);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);

/*
 * ... This is further complicated by the fact that some SiS96x south
 * bridges pretend to be 85C503/5513 instead.  In that case see if we
 * spotted a compatible north bridge to make sure.
 * (pci_find_device() doesn't work yet)
 *
 * We can also enable the sis96x bit in the discovery register..
 */
#define SIS_DETECT_REGISTER 0x40

static void quirk_sis_503(struct pci_dev *dev)
{
	u8 reg;
	u16 devid;

	pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
	pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
	pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
	if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
		pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
		return;
	}

	/*
	 * Ok, it now shows up as a 96x.  Run the 96x quirk by hand in case
	 * it has already been processed.  (Depends on link order, which is
	 * apparently not guaranteed)
	 */
	dev->device = devid;
	quirk_sis_96x_smbus(dev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);

/*
 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
 * and MC97 modem controller are disabled when a second PCI soundcard is
 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
 * -- bjd
 */
static void asus_hides_ac97_lpc(struct pci_dev *dev)
{
	u8 val;
	int asus_hides_ac97 = 0;

	if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
		if (dev->device == PCI_DEVICE_ID_VIA_8237)
			asus_hides_ac97 = 1;
	}

	if (!asus_hides_ac97)
		return;

	pci_read_config_byte(dev, 0x50, &val);
	if (val & 0xc0) {
		pci_write_config_byte(dev, 0x50, val & (~0xc0));
		pci_read_config_byte(dev, 0x50, &val);
		if (val & 0xc0)
			pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
				 val);
		else
			pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);

#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)

/*
 * If we are using libata we can drive this chip properly but must do this
 * early on to make the additional device appear during the PCI scanning.
 */
static void quirk_jmicron_ata(struct pci_dev *pdev)
{
	u32 conf1, conf5, class;
	u8 hdr;

	/* Only poke fn 0 */
	if (PCI_FUNC(pdev->devfn))
		return;

	pci_read_config_dword(pdev, 0x40, &conf1);
	pci_read_config_dword(pdev, 0x80, &conf5);

	conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
	conf5 &= ~(1 << 24);  /* Clear bit 24 */

	switch (pdev->device) {
	case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
	case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
	case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
		/* The controller should be in single function ahci mode */
		conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
		break;

	case PCI_DEVICE_ID_JMICRON_JMB365:
	case PCI_DEVICE_ID_JMICRON_JMB366:
		/* Redirect IDE second PATA port to the right spot */
		conf5 |= (1 << 24);
		/* Fall through */
	case PCI_DEVICE_ID_JMICRON_JMB361:
	case PCI_DEVICE_ID_JMICRON_JMB363:
	case PCI_DEVICE_ID_JMICRON_JMB369:
		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
		/* Set the class codes correctly and then direct IDE 0 */
		conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
		break;

	case PCI_DEVICE_ID_JMICRON_JMB368:
		/* The controller should be in single function IDE mode */
		conf1 |= 0x00C00000; /* Set 22, 23 */
		break;
	}

	pci_write_config_dword(pdev, 0x40, conf1);
	pci_write_config_dword(pdev, 0x80, conf5);

	/* Update pdev accordingly */
	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
	pdev->hdr_type = hdr & 0x7f;
	pdev->multifunction = !!(hdr & 0x80);

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
	pdev->class = class >> 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);

#endif

static void quirk_jmicron_async_suspend(struct pci_dev *dev)
{
	if (dev->multifunction) {
		device_disable_async_suspend(&dev->dev);
		pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
	}
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);

#ifdef CONFIG_X86_IO_APIC
static void quirk_alder_ioapic(struct pci_dev *pdev)
{
	int i;

	if ((pdev->class >> 8) != 0xff00)
		return;

	/*
	 * The first BAR is the location of the IO-APIC... we must
	 * not touch this (and it's already covered by the fixmap), so
	 * forcibly insert it into the resource tree.
	 */
	if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
		insert_resource(&iomem_resource, &pdev->resource[0]);

	/*
	 * The next five BARs all seem to be rubbish, so just clean
	 * them out.
	 */
	for (i = 1; i < 6; i++)
		memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_EESSC,	quirk_alder_ioapic);
#endif

static void quirk_pcie_mch(struct pci_dev *pdev)
{
	pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7520_MCH,	quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7320_MCH,	quirk_pcie_mch);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7525_MCH,	quirk_pcie_mch);

DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);

/*
 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
 * together on certain PXH-based systems.
 */
static void quirk_pcie_pxh(struct pci_dev *dev)
{
	dev->no_msi = 1;
	pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_0,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_1,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_pcie_pxh);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_pcie_pxh);

/*
 * Some Intel PCI Express chipsets have trouble with downstream device
 * power management.
 */
static void quirk_intel_pcie_pm(struct pci_dev *dev)
{
	pci_pm_d3_delay = 120;
	dev->no_d1d2 = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e2, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e3, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e4, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e5, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e6, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e7, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f7, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f8, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f9, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25fa, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2601, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2602, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2603, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2604, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2605, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2606, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2607, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2608, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);

static void quirk_radeon_pm(struct pci_dev *dev)
{
	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
	    dev->subsystem_device == 0x00e2) {
		if (dev->d3_delay < 20) {
			dev->d3_delay = 20;
			pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
				 dev->d3_delay);
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);

#ifdef CONFIG_X86_IO_APIC
static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
{
	noioapicreroute = 1;
	pr_info("%s detected: disable boot interrupt reroute\n", d->ident);

	return 0;
}

static const struct dmi_system_id boot_interrupt_dmi_table[] = {
	/*
	 * Systems to exclude from boot interrupt reroute quirks
	 */
	{
		.callback = dmi_disable_ioapicreroute,
		.ident = "ASUSTek Computer INC. M2N-LR",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
			DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
		},
	},
	{}
};

/*
 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
 * remap the original interrupt in the Linux kernel to the boot interrupt, so
 * that a PCI device's interrupt handler is installed on the boot interrupt
 * line instead.
 */
static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
{
	dmi_check_system(boot_interrupt_dmi_table);
	if (noioapicquirk || noioapicreroute)
		return;

	dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
	pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);

/*
 * On some chipsets we can disable the generation of legacy INTx boot
 * interrupts.
 */

/*
 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
 * 300641-004US, section 5.7.3.
 */
#define INTEL_6300_IOAPIC_ABAR		0x40
#define INTEL_6300_DISABLE_BOOT_IRQ	(1<<14)

static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
{
	u16 pci_config_word;

	if (noioapicquirk)
		return;

	pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
	pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
	pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,	quirk_disable_intel_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,	quirk_disable_intel_boot_interrupt);

/* Disable boot interrupts on HT-1000 */
#define BC_HT1000_FEATURE_REG		0x64
#define BC_HT1000_PIC_REGS_ENABLE	(1<<0)
#define BC_HT1000_MAP_IDX		0xC00
#define BC_HT1000_MAP_DATA		0xC01

static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
{
	u32 pci_config_dword;
	u8 irq;

	if (noioapicquirk)
		return;

	pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
			BC_HT1000_PIC_REGS_ENABLE);

	for (irq = 0x10; irq < 0x10 + 32; irq++) {
		outb(irq, BC_HT1000_MAP_IDX);
		outb(0x00, BC_HT1000_MAP_DATA);
	}

	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);

/* Disable boot interrupts on AMD and ATI chipsets */

/*
 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
 * (due to an erratum).
 */
#define AMD_813X_MISC			0x40
#define AMD_813X_NOIOAMODE		(1<<0)
#define AMD_813X_REV_B1			0x12
#define AMD_813X_REV_B2			0x13

static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
{
	u32 pci_config_dword;

	if (noioapicquirk)
		return;
	if ((dev->revision == AMD_813X_REV_B1) ||
	    (dev->revision == AMD_813X_REV_B2))
		return;

	pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
	pci_config_dword &= ~AMD_813X_NOIOAMODE;
	pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);

	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);

#define AMD_8111_PCI_IRQ_ROUTING	0x56

static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
{
	u16 pci_config_word;

	if (noioapicquirk)
		return;

	pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
	if (!pci_config_word) {
		pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
			 dev->vendor, dev->device);
		return;
	}
	pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
		 dev->vendor, dev->device);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
#endif /* CONFIG_X86_IO_APIC */

/*
 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
 * Re-allocate the region if needed...
 */
static void quirk_tc86c001_ide(struct pci_dev *dev)
{
	struct resource *r = &dev->resource[0];

	if (r->start & 0x8) {
		r->flags |= IORESOURCE_UNSET;
		r->start = 0;
		r->end = 0xf;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
			 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
			 quirk_tc86c001_ide);

/*
 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
 * being read correctly if bit 7 of the base address is set.
 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
 * Re-allocate the regions to a 256-byte boundary if necessary.
 */
static void quirk_plx_pci9050(struct pci_dev *dev)
{
	unsigned int bar;

	/* Fixed in revision 2 (PCI 9052). */
	if (dev->revision >= 2)
		return;
	for (bar = 0; bar <= 1; bar++)
		if (pci_resource_len(dev, bar) == 0x80 &&
		    (pci_resource_start(dev, bar) & 0x80)) {
			struct resource *r = &dev->resource[bar];
			pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
				 bar);
			r->flags |= IORESOURCE_UNSET;
			r->start = 0;
			r->end = 0xff;
		}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
			 quirk_plx_pci9050);
/*
 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
 *
 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
 * driver.
 */
DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);

static void quirk_netmos(struct pci_dev *dev)
{
	unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
	unsigned int num_serial = dev->subsystem_device & 0xf;

	/*
	 * These Netmos parts are multiport serial devices with optional
	 * parallel ports.  Even when parallel ports are present, they
	 * are identified as class SERIAL, which means the serial driver
	 * will claim them.  To prevent this, mark them as class OTHER.
	 * These combo devices should be claimed by parport_serial.
	 *
	 * The subdevice ID is of the form 0x00PS, where <P> is the number
	 * of parallel ports and <S> is the number of serial ports.
	 */
	switch (dev->device) {
	case PCI_DEVICE_ID_NETMOS_9835:
		/* Well, this rule doesn't hold for the following 9835 device */
		if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
				dev->subsystem_device == 0x0299)
			return;
		/* else, fall through */
	case PCI_DEVICE_ID_NETMOS_9735:
	case PCI_DEVICE_ID_NETMOS_9745:
	case PCI_DEVICE_ID_NETMOS_9845:
	case PCI_DEVICE_ID_NETMOS_9855:
		if (num_parallel) {
			pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
				dev->device, num_parallel, num_serial);
			dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
			    (dev->class & 0xff);
		}
	}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
			 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);

static void quirk_e100_interrupt(struct pci_dev *dev)
{
	u16 command, pmcsr;
	u8 __iomem *csr;
	u8 cmd_hi;

	switch (dev->device) {
	/* PCI IDs taken from drivers/net/e100.c */
	case 0x1029:
	case 0x1030 ... 0x1034:
	case 0x1038 ... 0x103E:
	case 0x1050 ... 0x1057:
	case 0x1059:
	case 0x1064 ... 0x106B:
	case 0x1091 ... 0x1095:
	case 0x1209:
	case 0x1229:
	case 0x2449:
	case 0x2459:
	case 0x245D:
	case 0x27DC:
		break;
	default:
		return;
	}

	/*
	 * Some firmware hands off the e100 with interrupts enabled,
	 * which can cause a flood of interrupts if packets are
	 * received before the driver attaches to the device.  So
	 * disable all e100 interrupts here.  The driver will
	 * re-enable them when it's ready.
	 */
	pci_read_config_word(dev, PCI_COMMAND, &command);

	if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
		return;

	/*
	 * Check that the device is in the D0 power state. If it's not,
	 * there is no point to look any further.
	 */
	if (dev->pm_cap) {
		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
			return;
	}

	/* Convert from PCI bus to resource space.  */
	csr = ioremap(pci_resource_start(dev, 0), 8);
	if (!csr) {
		pci_warn(dev, "Can't map e100 registers\n");
		return;
	}

	cmd_hi = readb(csr + 3);
	if (cmd_hi == 0) {
		pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
		writeb(1, csr + 3);
	}

	iounmap(csr);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);

/*
 * The 82575 and 82598 may experience data corruption issues when transitioning
 * out of L0S.  To prevent this we need to disable L0S on the PCIe link.
 */
static void quirk_disable_aspm_l0s(struct pci_dev *dev)
{
	pci_info(dev, "Disabling L0s\n");
	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);

/*
 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
 * Link bit cleared after starting the link retrain process to allow this
 * process to finish.
 *
 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130.  See also the
 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
 */
static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
{
	dev->clear_retrain_link = 1;
	pci_info(dev, "Enable PCIe Retrain Link quirk\n");
}
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);

static void fixup_rev1_53c810(struct pci_dev *dev)
{
	u32 class = dev->class;

	/*
	 * rev 1 ncr53c810 chips don't set the class at all which means
	 * they don't get their resources remapped. Fix that here.
	 */
	if (class)
		return;

	dev->class = PCI_CLASS_STORAGE_SCSI << 8;
	pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
		 class, dev->class);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);

/* Enable 1k I/O space granularity on the Intel P64H2 */
static void quirk_p64h2_1k_io(struct pci_dev *dev)
{
	u16 en1k;

	pci_read_config_word(dev, 0x40, &en1k);

	if (en1k & 0x200) {
		pci_info(dev, "Enable I/O Space to 1KB granularity\n");
		dev->io_window_1k = 1;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);

/*
 * Under some circumstances, AER is not linked with extended capabilities.
 * Force it to be linked by setting the corresponding control bit in the
 * config space.
 */
static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
{
	uint8_t b;

	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
		if (!(b & 0x20)) {
			pci_write_config_byte(dev, 0xf41, b | 0x20);
			pci_info(dev, "Linking AER extended capability\n");
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_pcie_aer_ext_cap);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_pcie_aer_ext_cap);

static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
{
	/*
	 * Disable PCI Bus Parking and PCI Master read caching on CX700
	 * which causes unspecified timing errors with a VT6212L on the PCI
	 * bus leading to USB2.0 packet loss.
	 *
	 * This quirk is only enabled if a second (on the external PCI bus)
	 * VT6212L is found -- the CX700 core itself also contains a USB
	 * host controller with the same PCI ID as the VT6212L.
	 */

	/* Count VT6212L instances */
	struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
		PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
	uint8_t b;

	/*
	 * p should contain the first (internal) VT6212L -- see if we have
	 * an external one by searching again.
	 */
	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
	if (!p)
		return;
	pci_dev_put(p);

	if (pci_read_config_byte(dev, 0x76, &b) == 0) {
		if (b & 0x40) {
			/* Turn off PCI Bus Parking */
			pci_write_config_byte(dev, 0x76, b ^ 0x40);

			pci_info(dev, "Disabling VIA CX700 PCI parking\n");
		}
	}

	if (pci_read_config_byte(dev, 0x72, &b) == 0) {
		if (b != 0) {
			/* Turn off PCI Master read caching */
			pci_write_config_byte(dev, 0x72, 0x0);

			/* Set PCI Master Bus time-out to "1x16 PCLK" */
			pci_write_config_byte(dev, 0x75, 0x1);

			/* Disable "Read FIFO Timer" */
			pci_write_config_byte(dev, 0x77, 0x0);

			pci_info(dev, "Disabling VIA CX700 PCI caching\n");
		}
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);

static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
{
	u32 rev;

	pci_read_config_dword(dev, 0xf4, &rev);

	/* Only CAP the MRRS if the device is a 5719 A0 */
	if (rev == 0x05719000) {
		int readrq = pcie_get_readrq(dev);
		if (readrq > 2048)
			pcie_set_readrq(dev, 2048);
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
			 PCI_DEVICE_ID_TIGON3_5719,
			 quirk_brcm_5719_limit_mrrs);

#ifdef CONFIG_PCIE_IPROC_PLATFORM
static void quirk_paxc_bridge(struct pci_dev *pdev)
{
	/*
	 * The PCI config space is shared with the PAXC root port and the first
	 * Ethernet device.  So, we need to workaround this by telling the PCI
	 * code that the bridge is not an Ethernet device.
	 */
	if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
		pdev->class = PCI_CLASS_BRIDGE_PCI << 8;

	/*
	 * MPSS is not being set properly (as it is currently 0).  This is
	 * because that area of the PCI config space is hard coded to zero, and
	 * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)
	 * so that the MPS can be set to the real max value.
	 */
	pdev->pcie_mpss = 2;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);
#endif

/*
 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
 * hide device 6 which configures the overflow device access containing the
 * DRBs - this is where we expose device 6.
 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
 */
static void quirk_unhide_mch_dev6(struct pci_dev *dev)
{
	u8 reg;

	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
		pci_info(dev, "Enabling MCH 'Overflow' Device\n");
		pci_write_config_byte(dev, 0xF4, reg | 0x02);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
			quirk_unhide_mch_dev6);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
			quirk_unhide_mch_dev6);

#ifdef CONFIG_PCI_MSI
/*
 * Some chipsets do not support MSI. We cannot easily rely on setting
 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
 * other buses controlled by the chipset even if Linux is not aware of it.
 * Instead of setting the flag on all buses in the machine, simply disable
 * MSI globally.
 */
static void quirk_disable_all_msi(struct pci_dev *dev)
{
	pci_no_msi();
	pci_warn(dev, "MSI quirk detected; MSI disabled\n");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);

/* Disable MSI on chipsets that are known to not support it */
static void quirk_disable_msi(struct pci_dev *dev)
{
	if (dev->subordinate) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);

/*
 * The APC bridge device in AMD 780 family northbridges has some random
 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
 * we use the possible vendor/device IDs of the host bridge for the
 * declared quirk, and search for the APC bridge by slot number.
 */
static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
{
	struct pci_dev *apc_bridge;

	apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
	if (apc_bridge) {
		if (apc_bridge->device == 0x9602)
			quirk_disable_msi(apc_bridge);
		pci_dev_put(apc_bridge);
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);

/*
 * Go through the list of HyperTransport capabilities and return 1 if a HT
 * MSI capability is found and enabled.
 */
static int msi_ht_cap_enabled(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Found %s HT MSI Mapping\n",
				flags & HT_MSI_FLAGS_ENABLE ?
				"enabled" : "disabled");
			return (flags & HT_MSI_FLAGS_ENABLE) != 0;
		}

		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
	return 0;
}

/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
static void quirk_msi_ht_cap(struct pci_dev *dev)
{
	if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
			quirk_msi_ht_cap);

/*
 * The nVidia CK804 chipset may have 2 HT MSI mappings.  MSI is supported
 * if the MSI capability is set in any of these mappings.
 */
static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
{
	struct pci_dev *pdev;

	if (!dev->subordinate)
		return;

	/*
	 * Check HT MSI cap on this chipset and the root one.  A single one
	 * having MSI is enough to be sure that MSI is supported.
	 */
	pdev = pci_get_slot(dev->bus, 0);
	if (!pdev)
		return;
	if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
	}
	pci_dev_put(pdev);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
			quirk_nvidia_ck804_msi_ht_cap);

/* Force enable MSI mapping capability on HT bridges */
static void ht_enable_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Enabling HT MSI Mapping\n");

			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
					      flags | HT_MSI_FLAGS_ENABLE);
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
			 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
			 ht_enable_msi_mapping);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
			 ht_enable_msi_mapping);

/*
 * The P5N32-SLI motherboards from Asus have a problem with MSI
 * for the MCP55 NIC. It is not yet determined whether the MSI problem
 * also affects other devices. As for now, turn off MSI for this device.
 */
static void nvenet_msi_disable(struct pci_dev *dev)
{
	const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);

	if (board_name &&
	    (strstr(board_name, "P5N32-SLI PREMIUM") ||
	     strstr(board_name, "P5N32-E SLI"))) {
		pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
		dev->no_msi = 1;
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_NVENET_15,
			nvenet_msi_disable);

/*
 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
 * generate MSI interrupts for PME and AER events instead only INTx interrupts
 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
 * for other events, since PCIe specificiation doesn't support using a mix of
 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
 * service drivers registering their respective ISRs for MSIs.
 */
static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
{
	dev->no_msi = 1;
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
			      PCI_CLASS_BRIDGE_PCI, 8,
			      pci_quirk_nvidia_tegra_disable_rp_msi);

/*
 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
 * config register.  This register controls the routing of legacy
 * interrupts from devices that route through the MCP55.  If this register
 * is misprogrammed, interrupts are only sent to the BSP, unlike
 * conventional systems where the IRQ is broadcast to all online CPUs.  Not
 * having this register set properly prevents kdump from booting up
 * properly, so let's make sure that we have it set correctly.
 * Note that this is an undocumented register.
 */
static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
{
	u32 cfg;

	if (!pci_find_capability(dev, PCI_CAP_ID_HT))
		return;

	pci_read_config_dword(dev, 0x74, &cfg);

	if (cfg & ((1 << 2) | (1 << 15))) {
		pr_info("Rewriting IRQ routing register on MCP55\n");
		cfg &= ~((1 << 2) | (1 << 15));
		pci_write_config_dword(dev, 0x74, cfg);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
			nvbridge_check_legacy_irq_routing);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
			nvbridge_check_legacy_irq_routing);

static int ht_check_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;
	int found = 0;

	/* Check if there is HT MSI cap or enabled on this device */
	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (found < 1)
			found = 1;
		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			if (flags & HT_MSI_FLAGS_ENABLE) {
				if (found < 2) {
					found = 2;
					break;
				}
			}
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}

	return found;
}

static int host_bridge_with_leaf(struct pci_dev *host_bridge)
{
	struct pci_dev *dev;
	int pos;
	int i, dev_no;
	int found = 0;

	dev_no = host_bridge->devfn >> 3;
	for (i = dev_no + 1; i < 0x20; i++) {
		dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
		if (!dev)
			continue;

		/* found next host bridge? */
		pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
		if (pos != 0) {
			pci_dev_put(dev);
			break;
		}

		if (ht_check_msi_mapping(dev)) {
			found = 1;
			pci_dev_put(dev);
			break;
		}
		pci_dev_put(dev);
	}

	return found;
}

#define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
#define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */

static int is_end_of_ht_chain(struct pci_dev *dev)
{
	int pos, ctrl_off;
	int end = 0;
	u16 flags, ctrl;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);

	if (!pos)
		goto out;

	pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);

	ctrl_off = ((flags >> 10) & 1) ?
			PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
	pci_read_config_word(dev, pos + ctrl_off, &ctrl);

	if (ctrl & (1 << 6))
		end = 1;

out:
	return end;
}

static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
	struct pci_dev *host_bridge;
	int pos;
	int i, dev_no;
	int found = 0;

	dev_no = dev->devfn >> 3;
	for (i = dev_no; i >= 0; i--) {
		host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
		if (!host_bridge)
			continue;

		pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
		if (pos != 0) {
			found = 1;
			break;
		}
		pci_dev_put(host_bridge);
	}

	if (!found)
		return;

	/* don't enable end_device/host_bridge with leaf directly here */
	if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
	    host_bridge_with_leaf(host_bridge))
		goto out;

	/* root did that ! */
	if (msi_ht_cap_enabled(host_bridge))
		goto out;

	ht_enable_msi_mapping(dev);

out:
	pci_dev_put(host_bridge);
}

static void ht_disable_msi_mapping(struct pci_dev *dev)
{
	int pos, ttl = PCI_FIND_CAP_TTL;

	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
	while (pos && ttl--) {
		u8 flags;

		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
					 &flags) == 0) {
			pci_info(dev, "Disabling HT MSI Mapping\n");

			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
					      flags & ~HT_MSI_FLAGS_ENABLE);
		}
		pos = pci_find_next_ht_capability(dev, pos,
						  HT_CAPTYPE_MSI_MAPPING);
	}
}

static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
{
	struct pci_dev *host_bridge;
	int pos;
	int found;

	if (!pci_msi_enabled())
		return;

	/* check if there is HT MSI cap or enabled on this device */
	found = ht_check_msi_mapping(dev);

	/* no HT MSI CAP */
	if (found == 0)
		return;

	/*
	 * HT MSI mapping should be disabled on devices that are below
	 * a non-Hypertransport host bridge. Locate the host bridge...
	 */
	host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
						  PCI_DEVFN(0, 0));
	if (host_bridge == NULL) {
		pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
		return;
	}

	pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
	if (pos != 0) {
		/* Host bridge is to HT */
		if (found == 1) {
			/* it is not enabled, try to enable it */
			if (all)
				ht_enable_msi_mapping(dev);
			else
				nv_ht_enable_msi_mapping(dev);
		}
		goto out;
	}

	/* HT MSI is not enabled */
	if (found == 1)
		goto out;

	/* Host bridge is not to HT, disable HT MSI mapping on this device */
	ht_disable_msi_mapping(dev);

out:
	pci_dev_put(host_bridge);
}

static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
{
	return __nv_msi_ht_cap_quirk(dev, 1);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);

static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
{
	return __nv_msi_ht_cap_quirk(dev, 0);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);

static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
}

static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
{
	struct pci_dev *p;

	/*
	 * SB700 MSI issue will be fixed at HW level from revision A21;
	 * we need check PCI REVISION ID of SMBus controller to get SB700
	 * revision.
	 */
	p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
			   NULL);
	if (!p)
		return;

	if ((p->revision < 0x3B) && (p->revision >= 0x30))
		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
	pci_dev_put(p);
}

static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
{
	/* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
	if (dev->revision < 0x18) {
		pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5780,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5780S,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5714,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5714S,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5715,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
			PCI_DEVICE_ID_TIGON3_5715S,
			quirk_msi_intx_disable_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
			quirk_msi_intx_disable_ati_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
			quirk_msi_intx_disable_ati_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
			quirk_msi_intx_disable_bug);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
			quirk_msi_intx_disable_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
			quirk_msi_intx_disable_qca_bug);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
			quirk_msi_intx_disable_qca_bug);

/*
 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
 * should be disabled on platforms where the device (mistakenly) advertises it.
 *
 * Notice that this quirk also disables MSI (which may work, but hasn't been
 * tested), since currently there is no standard way to disable only MSI-X.
 *
 * The 0031 device id is reused for other non Root Port device types,
 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
 */
static void quirk_al_msi_disable(struct pci_dev *dev)
{
	dev->no_msi = 1;
	pci_warn(dev, "Disabling MSI/MSI-X\n");
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
			      PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
#endif /* CONFIG_PCI_MSI */

/*
 * Allow manual resource allocation for PCI hotplug bridges via
 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
 * allocate resources when hotplug device is inserted and PCI bus is
 * rescanned.
 */
static void quirk_hotplug_bridge(struct pci_dev *dev)
{
	dev->is_hotplug_bridge = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);

/*
 * This is a quirk for the Ricoh MMC controller found as a part of some
 * multifunction chips.
 *
 * This is very similar and based on the ricoh_mmc driver written by
 * Philip Langdale. Thank you for these magic sequences.
 *
 * These chips implement the four main memory card controllers (SD, MMC,
 * MS, xD) and one or both of CardBus or FireWire.
 *
 * It happens that they implement SD and MMC support as separate
 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
 * cards but the chip detects MMC cards in hardware and directs them to the
 * MMC controller - so the SDHCI driver never sees them.
 *
 * To get around this, we must disable the useless MMC controller.  At that
 * point, the SDHCI controller will start seeing them.  It seems to be the
 * case that the relevant PCI registers to deactivate the MMC controller
 * live on PCI function 0, which might be the CardBus controller or the
 * FireWire controller, depending on the particular chip in question
 *
 * This has to be done early, because as soon as we disable the MMC controller
 * other PCI functions shift up one level, e.g. function #2 becomes function
 * #1, and this will confuse the PCI core.
 */
#ifdef CONFIG_MMC_RICOH_MMC
static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
{
	u8 write_enable;
	u8 disable;

	/*
	 * Disable via FireWire interface
	 *
	 * This must be done via function #0
	 */
	if (PCI_FUNC(dev->devfn))
		return;
	/*
	 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
	 * certain types of SD/MMC cards. Lowering the SD base clock
	 * frequency from 200Mhz to 50Mhz fixes this issue.
	 *
	 * 0x150 - SD2.0 mode enable for changing base clock
	 *	   frequency to 50Mhz
	 * 0xe1  - Base clock frequency
	 * 0x32  - 50Mhz new clock frequency
	 * 0xf9  - Key register for 0x150
	 * 0xfc  - key register for 0xe1
	 */
	if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
	    dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
		pci_write_config_byte(dev, 0xf9, 0xfc);
		pci_write_config_byte(dev, 0x150, 0x10);
		pci_write_config_byte(dev, 0xf9, 0x00);
		pci_write_config_byte(dev, 0xfc, 0x01);
		pci_write_config_byte(dev, 0xe1, 0x32);
		pci_write_config_byte(dev, 0xfc, 0x00);

		pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
	}

	pci_read_config_byte(dev, 0xCB, &disable);

	if (disable & 0x02)
		return;

	pci_read_config_byte(dev, 0xCA, &write_enable);
	pci_write_config_byte(dev, 0xCA, 0x57);
	pci_write_config_byte(dev, 0xCB, disable | 0x02);
	pci_write_config_byte(dev, 0xCA, write_enable);

	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
	pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");

}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
#endif /*CONFIG_MMC_RICOH_MMC*/

#ifdef CONFIG_DMAR_TABLE
#define VTUNCERRMSK_REG	0x1ac
#define VTD_MSK_SPEC_ERRORS	(1 << 31)
/*
 * This is a quirk for masking VT-d spec-defined errors to platform error
 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
 * on the RAS config settings of the platform) when a VT-d fault happens.
 * The resulting SMI caused the system to hang.
 *
 * VT-d spec-related errors are already handled by the VT-d OS code, so no
 * need to report the same error through other channels.
 */
static void vtd_mask_spec_errors(struct pci_dev *dev)
{
	u32 word;

	pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
	pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
#endif

static void fixup_ti816x_class(struct pci_dev *dev)
{
	u32 class = dev->class;

	/* TI 816x devices do not have class code set when in PCIe boot mode */
	dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
	pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
		 class, dev->class);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
			      PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);

/*
 * Some PCIe devices do not work reliably with the claimed maximum
 * payload size supported.
 */
static void fixup_mpss_256(struct pci_dev *dev)
{
	dev->pcie_mpss = 1; /* 256 bytes */
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
			 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);

/*
 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
 * Since there is no way of knowing what the PCIe MPS on each fabric will be
 * until all of the devices are discovered and buses walked, read completion
 * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
 * it is possible to hotplug a device with MPS of 256B.
 */
static void quirk_intel_mc_errata(struct pci_dev *dev)
{
	int err;
	u16 rcc;

	if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
	    pcie_bus_config == PCIE_BUS_DEFAULT)
		return;

	/*
	 * Intel erratum specifies bits to change but does not say what
	 * they are.  Keeping them magical until such time as the registers
	 * and values can be explained.
	 */
	err = pci_read_config_word(dev, 0x48, &rcc);
	if (err) {
		pci_err(dev, "Error attempting to read the read completion coalescing register\n");
		return;
	}

	if (!(rcc & (1 << 10)))
		return;

	rcc &= ~(1 << 10);

	err = pci_write_config_word(dev, 0x48, rcc);
	if (err) {
		pci_err(dev, "Error attempting to write the read completion coalescing register\n");
		return;
	}

	pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
}
/* Intel 5000 series memory controllers and ports 2-7 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
/* Intel 5100 series memory controllers and ports 2-7 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);

/*
 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
 * To work around this, query the size it should be configured to by the
 * device and modify the resource end to correspond to this new size.
 */
static void quirk_intel_ntb(struct pci_dev *dev)
{
	int rc;
	u8 val;

	rc = pci_read_config_byte(dev, 0x00D0, &val);
	if (rc)
		return;

	dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;

	rc = pci_read_config_byte(dev, 0x00D1, &val);
	if (rc)
		return;

	dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);

/*
 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
 * though no one is handling them (e.g., if the i915 driver is never
 * loaded).  Additionally the interrupt destination is not set up properly
 * and the interrupt ends up -somewhere-.
 *
 * These spurious interrupts are "sticky" and the kernel disables the
 * (shared) interrupt line after 100,000+ generated interrupts.
 *
 * Fix it by disabling the still enabled interrupts.  This resolves crashes
 * often seen on monitor unplug.
 */
#define I915_DEIER_REG 0x4400c
static void disable_igfx_irq(struct pci_dev *dev)
{
	void __iomem *regs = pci_iomap(dev, 0, 0);
	if (regs == NULL) {
		pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
		return;
	}

	/* Check if any interrupt line is still enabled */
	if (readl(regs + I915_DEIER_REG) != 0) {
		pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");

		writel(0, regs + I915_DEIER_REG);
	}

	pci_iounmap(dev, regs);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);

/*
 * PCI devices which are on Intel chips can skip the 10ms delay
 * before entering D3 mode.
 */
static void quirk_remove_d3_delay(struct pci_dev *dev)
{
	dev->d3_delay = 0;
}
/* C600 Series devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
/* Intel Cherrytrail devices do not need 10ms d3_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);

/*
 * Some devices may pass our check in pci_intx_mask_supported() if
 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
 * support this feature.
 */
static void quirk_broken_intx_masking(struct pci_dev *dev)
{
	dev->broken_intx_masking = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
			quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
			quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
			quirk_broken_intx_masking);

/*
 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
 *
 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
			quirk_broken_intx_masking);

/*
 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
 * DisINTx can be set but the interrupt status bit is non-functional.
 */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);

static u16 mellanox_broken_intx_devs[] = {
	PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
	PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
	PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
	PCI_DEVICE_ID_MELLANOX_HERMON_EN,
	PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX2,
	PCI_DEVICE_ID_MELLANOX_CONNECTX3,
	PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
};

#define CONNECTX_4_CURR_MAX_MINOR 99
#define CONNECTX_4_INTX_SUPPORT_MINOR 14

/*
 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
 * If so, don't mark it as broken.
 * FW minor > 99 means older FW version format and no INTx masking support.
 * FW minor < 14 means new FW version format and no INTx masking support.
 */
static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
{
	__be32 __iomem *fw_ver;
	u16 fw_major;
	u16 fw_minor;
	u16 fw_subminor;
	u32 fw_maj_min;
	u32 fw_sub_min;
	int i;

	for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
		if (pdev->device == mellanox_broken_intx_devs[i]) {
			pdev->broken_intx_masking = 1;
			return;
		}
	}

	/*
	 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
	 * support so shouldn't be checked further
	 */
	if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
		return;

	if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
	    pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
		return;

	/* For ConnectX-4 and ConnectX-4LX, need to check FW support */
	if (pci_enable_device_mem(pdev)) {
		pci_warn(pdev, "Can't enable device memory\n");
		return;
	}

	fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
	if (!fw_ver) {
		pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
		goto out;
	}

	/* Reading from resource space should be 32b aligned */
	fw_maj_min = ioread32be(fw_ver);
	fw_sub_min = ioread32be(fw_ver + 1);
	fw_major = fw_maj_min & 0xffff;
	fw_minor = fw_maj_min >> 16;
	fw_subminor = fw_sub_min & 0xffff;
	if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
	    fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
		pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
			 fw_major, fw_minor, fw_subminor, pdev->device ==
			 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
		pdev->broken_intx_masking = 1;
	}

	iounmap(fw_ver);

out:
	pci_disable_device(pdev);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
			mellanox_check_broken_intx_masking);

static void quirk_no_bus_reset(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
}

/*
 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
 * The device will throw a Link Down error on AER-capable systems and
 * regardless of AER, config space of the device is never accessible again
 * and typically causes the system to hang or reset when access is attempted.
 * http://www.spinics.net/lists/linux-pci/msg34797.html
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);

/*
 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
 * reset when used with certain child devices.  After the reset, config
 * accesses to the child may fail.
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);

static void quirk_no_pm_reset(struct pci_dev *dev)
{
	/*
	 * We can't do a bus reset on root bus devices, but an ineffective
	 * PM reset may be better than nothing.
	 */
	if (!pci_is_root_bus(dev->bus))
		dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
}

/*
 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
 * causes a reset (i.e., they advertise NoSoftRst-).  This transition seems
 * to have no effect on the device: it retains the framebuffer contents and
 * monitor sync.  Advertising this support makes other layers, like VFIO,
 * assume pci_reset_function() is viable for this device.  Mark it as
 * unavailable to skip it when testing reset methods.
 */
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
			       PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);

/*
 * Thunderbolt controllers with broken MSI hotplug signaling:
 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
 */
static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
{
	if (pdev->is_hotplug_bridge &&
	    (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
	     pdev->revision <= 1))
		pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			quirk_thunderbolt_hotplug_msi);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
			quirk_thunderbolt_hotplug_msi);

#ifdef CONFIG_ACPI
/*
 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
 *
 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
 * shutdown before suspend. Otherwise the native host interface (NHI) will not
 * be present after resume if a device was plugged in before suspend.
 *
 * The Thunderbolt controller consists of a PCIe switch with downstream
 * bridges leading to the NHI and to the tunnel PCI bridges.
 *
 * This quirk cuts power to the whole chip. Therefore we have to apply it
 * during suspend_noirq of the upstream bridge.
 *
 * Power is automagically restored before resume. No action is needed.
 */
static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
{
	acpi_handle bridge, SXIO, SXFP, SXLV;

	if (!x86_apple_machine)
		return;
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
		return;
	bridge = ACPI_HANDLE(&dev->dev);
	if (!bridge)
		return;

	/*
	 * SXIO and SXLV are present only on machines requiring this quirk.
	 * Thunderbolt bridges in external devices might have the same
	 * device ID as those on the host, but they will not have the
	 * associated ACPI methods. This implicitly checks that we are at
	 * the right bridge.
	 */
	if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
		return;
	pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");

	/* magic sequence */
	acpi_execute_simple_method(SXIO, NULL, 1);
	acpi_execute_simple_method(SXFP, NULL, 0);
	msleep(300);
	acpi_execute_simple_method(SXLV, NULL, 0);
	acpi_execute_simple_method(SXIO, NULL, 0);
	acpi_execute_simple_method(SXLV, NULL, 0);
}
DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			       quirk_apple_poweroff_thunderbolt);

/*
 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
 *
 * During suspend the Thunderbolt controller is reset and all PCI
 * tunnels are lost. The NHI driver will try to reestablish all tunnels
 * during resume. We have to manually wait for the NHI since there is
 * no parent child relationship between the NHI and the tunneled
 * bridges.
 */
static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
{
	struct pci_dev *sibling = NULL;
	struct pci_dev *nhi = NULL;

	if (!x86_apple_machine)
		return;
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
		return;

	/*
	 * Find the NHI and confirm that we are a bridge on the Thunderbolt
	 * host controller and not on a Thunderbolt endpoint.
	 */
	sibling = pci_get_slot(dev->bus, 0x0);
	if (sibling == dev)
		goto out; /* we are the downstream bridge to the NHI */
	if (!sibling || !sibling->subordinate)
		goto out;
	nhi = pci_get_slot(sibling->subordinate, 0x0);
	if (!nhi)
		goto out;
	if (nhi->vendor != PCI_VENDOR_ID_INTEL
		    || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
			nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
			nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
		    || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
		goto out;
	pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
	device_pm_wait_for_dev(&dev->dev, &nhi->dev);
out:
	pci_dev_put(nhi);
	pci_dev_put(sibling);
}
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
			       quirk_apple_wait_for_thunderbolt);
DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
			       PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
			       quirk_apple_wait_for_thunderbolt);
#endif

/*
 * Following are device-specific reset methods which can be used to
 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
 * not available.
 */
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
{
	/*
	 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
	 *
	 * The 82599 supports FLR on VFs, but FLR support is reported only
	 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
	 * Thus we must call pcie_flr() directly without first checking if it is
	 * supported.
	 */
	if (!probe)
		pcie_flr(dev);
	return 0;
}

#define SOUTH_CHICKEN2		0xc2004
#define PCH_PP_STATUS		0xc7200
#define PCH_PP_CONTROL		0xc7204
#define MSG_CTL			0x45010
#define NSDE_PWR_STATE		0xd0100
#define IGD_OPERATION_TIMEOUT	10000     /* set timeout 10 seconds */

static int reset_ivb_igd(struct pci_dev *dev, int probe)
{
	void __iomem *mmio_base;
	unsigned long timeout;
	u32 val;

	if (probe)
		return 0;

	mmio_base = pci_iomap(dev, 0, 0);
	if (!mmio_base)
		return -ENOMEM;

	iowrite32(0x00000002, mmio_base + MSG_CTL);

	/*
	 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
	 * driver loaded sets the right bits. However, this's a reset and
	 * the bits have been set by i915 previously, so we clobber
	 * SOUTH_CHICKEN2 register directly here.
	 */
	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);

	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
	iowrite32(val, mmio_base + PCH_PP_CONTROL);

	timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
	do {
		val = ioread32(mmio_base + PCH_PP_STATUS);
		if ((val & 0xb0000000) == 0)
			goto reset_complete;
		msleep(10);
	} while (time_before(jiffies, timeout));
	pci_warn(dev, "timeout during reset\n");

reset_complete:
	iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);

	pci_iounmap(dev, mmio_base);
	return 0;
}

/* Device-specific reset method for Chelsio T4-based adapters */
static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
{
	u16 old_command;
	u16 msix_flags;

	/*
	 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
	 * that we have no device-specific reset method.
	 */
	if ((dev->device & 0xf000) != 0x4000)
		return -ENOTTY;

	/*
	 * If this is the "probe" phase, return 0 indicating that we can
	 * reset this device.
	 */
	if (probe)
		return 0;

	/*
	 * T4 can wedge if there are DMAs in flight within the chip and Bus
	 * Master has been disabled.  We need to have it on till the Function
	 * Level Reset completes.  (BUS_MASTER is disabled in
	 * pci_reset_function()).
	 */
	pci_read_config_word(dev, PCI_COMMAND, &old_command);
	pci_write_config_word(dev, PCI_COMMAND,
			      old_command | PCI_COMMAND_MASTER);

	/*
	 * Perform the actual device function reset, saving and restoring
	 * configuration information around the reset.
	 */
	pci_save_state(dev);

	/*
	 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
	 * are disabled when an MSI-X interrupt message needs to be delivered.
	 * So we briefly re-enable MSI-X interrupts for the duration of the
	 * FLR.  The pci_restore_state() below will restore the original
	 * MSI-X state.
	 */
	pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
	if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
		pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
				      msix_flags |
				      PCI_MSIX_FLAGS_ENABLE |
				      PCI_MSIX_FLAGS_MASKALL);

	pcie_flr(dev);

	/*
	 * Restore the configuration information (BAR values, etc.) including
	 * the original PCI Configuration Space Command word, and return
	 * success.
	 */
	pci_restore_state(dev);
	pci_write_config_word(dev, PCI_COMMAND, old_command);
	return 0;
}

#define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
#define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166

/*
 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
 * FLR where config space reads from the device return -1.  We seem to be
 * able to avoid this condition if we disable the NVMe controller prior to
 * FLR.  This quirk is generic for any NVMe class device requiring similar
 * assistance to quiesce the device prior to FLR.
 *
 * NVMe specification: https://nvmexpress.org/resources/specifications/
 * Revision 1.0e:
 *    Chapter 2: Required and optional PCI config registers
 *    Chapter 3: NVMe control registers
 *    Chapter 7.3: Reset behavior
 */
static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
{
	void __iomem *bar;
	u16 cmd;
	u32 cfg;

	if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
	    !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
		return -ENOTTY;

	if (probe)
		return 0;

	bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
	if (!bar)
		return -ENOTTY;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);

	cfg = readl(bar + NVME_REG_CC);

	/* Disable controller if enabled */
	if (cfg & NVME_CC_ENABLE) {
		u32 cap = readl(bar + NVME_REG_CAP);
		unsigned long timeout;

		/*
		 * Per nvme_disable_ctrl() skip shutdown notification as it
		 * could complete commands to the admin queue.  We only intend
		 * to quiesce the device before reset.
		 */
		cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);

		writel(cfg, bar + NVME_REG_CC);

		/*
		 * Some controllers require an additional delay here, see
		 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY.  None of those are yet
		 * supported by this quirk.
		 */

		/* Cap register provides max timeout in 500ms increments */
		timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;

		for (;;) {
			u32 status = readl(bar + NVME_REG_CSTS);

			/* Ready status becomes zero on disable complete */
			if (!(status & NVME_CSTS_RDY))
				break;

			msleep(100);

			if (time_after(jiffies, timeout)) {
				pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
				break;
			}
		}
	}

	pci_iounmap(dev, bar);

	pcie_flr(dev);

	return 0;
}

/*
 * Intel DC P3700 NVMe controller will timeout waiting for ready status
 * to change after NVMe enable if the driver starts interacting with the
 * device too soon after FLR.  A 250ms delay after FLR has heuristically
 * proven to produce reliably working results for device assignment cases.
 */
static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
{
	if (!pcie_has_flr(dev))
		return -ENOTTY;

	if (probe)
		return 0;

	pcie_flr(dev);

	msleep(250);

	return 0;
}

static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
		 reset_intel_82599_sfp_virtfn },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
		reset_ivb_igd },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
		reset_ivb_igd },
	{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
	{ PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
		reset_chelsio_generic_dev },
	{ 0 }
};

/*
 * These device-specific reset methods are here rather than in a driver
 * because when a host assigns a device to a guest VM, the host may need
 * to reset the device but probably doesn't have a driver for it.
 */
int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	const struct pci_dev_reset_methods *i;

	for (i = pci_dev_reset_methods; i->reset; i++) {
		if ((i->vendor == dev->vendor ||
		     i->vendor == (u16)PCI_ANY_ID) &&
		    (i->device == dev->device ||
		     i->device == (u16)PCI_ANY_ID))
			return i->reset(dev, probe);
	}

	return -ENOTTY;
}

static void quirk_dma_func0_alias(struct pci_dev *dev)
{
	if (PCI_FUNC(dev->devfn) != 0)
		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
}

/*
 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
 *
 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);

static void quirk_dma_func1_alias(struct pci_dev *dev)
{
	if (PCI_FUNC(dev->devfn) != 1)
		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
}

/*
 * Marvell 88SE9123 uses function 1 as the requester ID for DMA.  In some
 * SKUs function 1 is present and is a legacy IDE controller, in other
 * SKUs this function is not present, making this a ghost requester.
 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
			 quirk_dma_func1_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
			 quirk_dma_func1_alias);
/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
			 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
			 quirk_dma_func1_alias);
/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
			 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
			 quirk_dma_func1_alias);

/*
 * Some devices DMA with the wrong devfn, not just the wrong function.
 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
 * the alias is "fixed" and independent of the device devfn.
 *
 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
 * processor.  To software, this appears as a PCIe-to-PCI/X bridge with a
 * single device on the secondary bus.  In reality, the single exposed
 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
 * that provides a bridge to the internal bus of the I/O processor.  The
 * controller supports private devices, which can be hidden from PCI config
 * space.  In the case of the Adaptec 3405, a private device at 01.0
 * appears to be the DMA engine, which therefore needs to become a DMA
 * alias for the device.
 */
static const struct pci_device_id fixed_dma_alias_tbl[] = {
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
			 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
	  .driver_data = PCI_DEVFN(1, 0) },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
			 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
	  .driver_data = PCI_DEVFN(1, 0) },
	{ 0 }
};

static void quirk_fixed_dma_alias(struct pci_dev *dev)
{
	const struct pci_device_id *id;

	id = pci_match_id(fixed_dma_alias_tbl, dev);
	if (id)
		pci_add_dma_alias(dev, id->driver_data);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);

/*
 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
 * using the wrong DMA alias for the device.  Some of these devices can be
 * used as either forward or reverse bridges, so we need to test whether the
 * device is operating in the correct mode.  We could probably apply this
 * quirk to PCI_ANY_ID, but for now we'll just use known offenders.  The test
 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
 */
static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
{
	if (!pci_is_root_bus(pdev->bus) &&
	    pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
	    !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
	    pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
		pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
}
/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
			 quirk_use_pcie_bridge_dma_alias);
/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
/* ITE 8893 has the same problem as the 8892 */
DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);

/*
 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
 * be added as aliases to the DMA device in order to allow buffer access
 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
 * programmed in the EEPROM.
 */
static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
{
	pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
	pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
	pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);

/*
 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
 * associated not at the root bus, but at a bridge below. This quirk avoids
 * generating invalid DMA aliases.
 */
static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
{
	pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
				quirk_bridge_cavm_thrx2_pcie_root);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
				quirk_bridge_cavm_thrx2_pcie_root);

/*
 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
 * class code.  Fix it.
 */
static void quirk_tw686x_class(struct pci_dev *pdev)
{
	u32 class = pdev->class;

	/* Use "Multimedia controller" class */
	pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
	pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
		 class, pdev->class);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);
DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_tw686x_class);

/*
 * Some devices have problems with Transaction Layer Packets with the Relaxed
 * Ordering Attribute set.  Such devices should mark themselves and other
 * device drivers should check before sending TLPs with RO set.
 */
static void quirk_relaxedordering_disable(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
	pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
}

/*
 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
 * Complex have a Flow Control Credit issue which can cause performance
 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
 */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);

/*
 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
 * where Upstream Transaction Layer Packets with the Relaxed Ordering
 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
 * set.  This is a violation of the PCIe 3.0 Transaction Ordering Rules
 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
 * November 10, 2010).  As a result, on this platform we can't use Relaxed
 * Ordering for Upstream TLPs.
 */
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
			      quirk_relaxedordering_disable);

/*
 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
 * values for the Attribute as were supplied in the header of the
 * corresponding Request, except as explicitly allowed when IDO is used."
 *
 * If a non-compliant device generates a completion with a different
 * attribute than the request, the receiver may accept it (which itself
 * seems non-compliant based on sec 2.3.2), or it may handle it as a
 * Malformed TLP or an Unexpected Completion, which will probably lead to a
 * device access timeout.
 *
 * If the non-compliant device generates completions with zero attributes
 * (instead of copying the attributes from the request), we can work around
 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
 * upstream devices so they always generate requests with zero attributes.
 *
 * This affects other devices under the same Root Port, but since these
 * attributes are performance hints, there should be no functional problem.
 *
 * Note that Configuration Space accesses are never supposed to have TLP
 * Attributes, so we're safe waiting till after any Configuration Space
 * accesses to do the Root Port fixup.
 */
static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
{
	struct pci_dev *root_port = pci_find_pcie_root_port(pdev);

	if (!root_port) {
		pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
		return;
	}

	pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
		 dev_name(&pdev->dev));
	pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
					   PCI_EXP_DEVCTL_RELAX_EN |
					   PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
}

/*
 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
 * Completion it generates.
 */
static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
{
	/*
	 * This mask/compare operation selects for Physical Function 4 on a
	 * T5.  We only need to fix up the Root Port once for any of the
	 * PFs.  PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
	 * 0x54xx so we use that one.
	 */
	if ((pdev->device & 0xff00) == 0x5400)
		quirk_disable_root_port_attributes(pdev);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
			 quirk_chelsio_T5_disable_root_port_attributes);

/*
 * AMD has indicated that the devices below do not support peer-to-peer
 * in any system where they are found in the southbridge with an AMD
 * IOMMU in the system.  Multifunction devices that do not support
 * peer-to-peer between functions can claim to support a subset of ACS.
 * Such devices effectively enable request redirect (RR) and completion
 * redirect (CR) since all transactions are redirected to the upstream
 * root complex.
 *
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
 *
 * 1002:4385 SBx00 SMBus Controller
 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
 * 1002:4383 SBx00 Azalia (Intel HDA)
 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
 * 1002:4384 SBx00 PCI to PCI Bridge
 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
 *
 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
 *
 * 1022:780f [AMD] FCH PCI Bridge
 * 1022:7809 [AMD] FCH USB OHCI Controller
 */
static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
{
#ifdef CONFIG_ACPI
	struct acpi_table_header *header = NULL;
	acpi_status status;

	/* Targeting multifunction devices on the SB (appears on root bus) */
	if (!dev->multifunction || !pci_is_root_bus(dev->bus))
		return -ENODEV;

	/* The IVRS table describes the AMD IOMMU */
	status = acpi_get_table("IVRS", 0, &header);
	if (ACPI_FAILURE(status))
		return -ENODEV;

	/* Filter out flags not applicable to multifunction */
	acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);

	return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
#else
	return -ENODEV;
#endif
}

static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
{
	/*
	 * Effectively selects all downstream ports for whole ThunderX 1
	 * family by 0xf800 mask (which represents 8 SoCs), while the lower
	 * bits of device ID are used to indicate which subdevice is used
	 * within the SoC.
	 */
	return (pci_is_pcie(dev) &&
		(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
		((dev->device & 0xf800) == 0xa000));
}

static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * Cavium root ports don't advertise an ACS capability.  However,
	 * the RTL internally implements similar protection as if ACS had
	 * Request Redirection, Completion Redirection, Source Validation,
	 * and Upstream Forwarding features enabled.  Assert that the
	 * hardware implements and enables equivalent ACS functionality for
	 * these flags.
	 */
	acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);

	if (!pci_quirk_cavium_acs_match(dev))
		return -ENOTTY;

	return acs_flags ? 0 : 1;
}

static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
	 * transactions with others, allowing masking out these bits as if they
	 * were unimplemented in the ACS capability.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

/*
 * Many Intel PCH root ports do provide ACS-like features to disable peer
 * transactions and validate bus numbers in requests, but do not provide an
 * actual PCIe ACS capability.  This is the list of device IDs known to fall
 * into that category as provided by Intel in Red Hat bugzilla 1037684.
 */
static const u16 pci_quirk_intel_pch_acs_ids[] = {
	/* Ibexpeak PCH */
	0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
	0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
	/* Cougarpoint PCH */
	0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
	0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
	/* Pantherpoint PCH */
	0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
	0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
	/* Lynxpoint-H PCH */
	0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
	0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
	/* Lynxpoint-LP PCH */
	0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
	0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
	/* Wildcat PCH */
	0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
	0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
	/* Patsburg (X79) PCH */
	0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
	/* Wellsburg (X99) PCH */
	0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
	0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
	/* Lynx Point (9 series) PCH */
	0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
};

static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
{
	int i;

	/* Filter out a few obvious non-matches first */
	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return false;

	for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
		if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
			return true;

	return false;
}

#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)

static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
{
	u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
		    INTEL_PCH_ACS_FLAGS : 0;

	if (!pci_quirk_intel_pch_acs_match(dev))
		return -ENOTTY;

	return acs_flags & ~flags ? 0 : 1;
}

/*
 * These QCOM root ports do provide ACS-like features to disable peer
 * transactions and validate bus numbers in requests, but do not provide an
 * actual PCIe ACS capability.  Hardware supports source validation but it
 * will report the issue as Completer Abort instead of ACS Violation.
 * Hardware doesn't support peer-to-peer and each root port is a root
 * complex with unique segment numbers.  It is not possible for one root
 * port to pass traffic to another root port.  All PCIe transactions are
 * terminated inside the root port.
 */
static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
{
	u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
	int ret = acs_flags & ~flags ? 0 : 1;

	pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);

	return ret;
}

static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
{
	if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return -ENOTTY;

	/*
	 * Amazon's Annapurna Labs root ports don't include an ACS capability,
	 * but do include ACS-like functionality. The hardware doesn't support
	 * peer-to-peer transactions via the root port and each has a unique
	 * segment number.
	 *
	 * Additionally, the root ports cannot send traffic to each other.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

/*
 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
 * 7.16 ACS Extended Capability).  The bit definitions are correct, but the
 * control register is at offset 8 instead of 6 and we should probably use
 * dword accesses to them.  This applies to the following PCI Device IDs, as
 * found in volume 1 of the datasheet[2]:
 *
 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
 *
 * N.B. This doesn't fix what lspci shows.
 *
 * The 100 series chipset specification update includes this as errata #23[3].
 *
 * The 200 series chipset (Union Point) has the same bug according to the
 * specification update (Intel 200 Series Chipset Family Platform Controller
 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
 * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
 * chipset include:
 *
 * 0xa290-0xa29f PCI Express Root port #{0-16}
 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
 *
 * Mobile chipsets are also affected, 7th & 8th Generation
 * Specification update confirms ACS errata 22, status no fix: (7th Generation
 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
 * Processor Family I/O for U Quad Core Platforms Specification Update,
 * August 2017, Revision 002, Document#: 334660-002)[6]
 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
 *
 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
 *
 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
 */
static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
{
	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
		return false;

	switch (dev->device) {
	case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
	case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
	case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
		return true;
	}

	return false;
}

#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)

static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	/* see pci_acs_flags_enabled() */
	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	acs_flags &= (cap | PCI_ACS_EC);

	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	return acs_flags & ~ctrl ? 0 : 1;
}

static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * SV, TB, and UF are not relevant to multifunction endpoints.
	 *
	 * Multifunction devices are only required to implement RR, CR, and DT
	 * in their ACS capability if they support peer-to-peer transactions.
	 * Devices matching this quirk have been verified by the vendor to not
	 * perform peer-to-peer with other functions, allowing us to mask out
	 * these bits as if they were unimplemented in the ACS capability.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);

	return acs_flags ? 0 : 1;
}

static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
{
	/*
	 * iProc PAXB Root Ports don't advertise an ACS capability, but
	 * they do not allow peer-to-peer transactions between Root Ports.
	 * Allow each Root Port to be in a separate IOMMU group by masking
	 * SV/RR/CR/UF bits.
	 */
	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	return acs_flags ? 0 : 1;
}

static const struct pci_dev_acs_enabled {
	u16 vendor;
	u16 device;
	int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
} pci_dev_acs_enabled[] = {
	{ PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
	/* 82580 */
	{ PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
	/* 82576 */
	{ PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
	/* 82575 */
	{ PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
	/* I350 */
	{ PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
	/* 82571 (Quads omitted due to non-ACS switch) */
	{ PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
	/* I219 */
	{ PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
	{ PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
	/* QCOM QDF2xxx root ports */
	{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
	{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
	/* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
	{ PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
	/* Intel PCH root ports */
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
	{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
	/* Cavium ThunderX */
	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
	/* APM X-Gene */
	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
	/* Ampere Computing */
	{ PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
	/* Amazon Annapurna Labs */
	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
	{ 0 }
};

int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
{
	const struct pci_dev_acs_enabled *i;
	int ret;

	/*
	 * Allow devices that do not expose standard PCIe ACS capabilities
	 * or control to indicate their support here.  Multi-function express
	 * devices which do not allow internal peer-to-peer between functions,
	 * but do not implement PCIe ACS may wish to return true here.
	 */
	for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
		if ((i->vendor == dev->vendor ||
		     i->vendor == (u16)PCI_ANY_ID) &&
		    (i->device == dev->device ||
		     i->device == (u16)PCI_ANY_ID)) {
			ret = i->acs_enabled(dev, acs_flags);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

/* Config space offset of Root Complex Base Address register */
#define INTEL_LPC_RCBA_REG 0xf0
/* 31:14 RCBA address */
#define INTEL_LPC_RCBA_MASK 0xffffc000
/* RCBA Enable */
#define INTEL_LPC_RCBA_ENABLE (1 << 0)

/* Backbone Scratch Pad Register */
#define INTEL_BSPR_REG 0x1104
/* Backbone Peer Non-Posted Disable */
#define INTEL_BSPR_REG_BPNPD (1 << 8)
/* Backbone Peer Posted Disable */
#define INTEL_BSPR_REG_BPPD  (1 << 9)

/* Upstream Peer Decode Configuration Register */
#define INTEL_UPDCR_REG 0x1114
/* 5:0 Peer Decode Enable bits */
#define INTEL_UPDCR_REG_MASK 0x3f

static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
{
	u32 rcba, bspr, updcr;
	void __iomem *rcba_mem;

	/*
	 * Read the RCBA register from the LPC (D31:F0).  PCH root ports
	 * are D28:F* and therefore get probed before LPC, thus we can't
	 * use pci_get_slot()/pci_read_config_dword() here.
	 */
	pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
				  INTEL_LPC_RCBA_REG, &rcba);
	if (!(rcba & INTEL_LPC_RCBA_ENABLE))
		return -EINVAL;

	rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
				   PAGE_ALIGN(INTEL_UPDCR_REG));
	if (!rcba_mem)
		return -ENOMEM;

	/*
	 * The BSPR can disallow peer cycles, but it's set by soft strap and
	 * therefore read-only.  If both posted and non-posted peer cycles are
	 * disallowed, we're ok.  If either are allowed, then we need to use
	 * the UPDCR to disable peer decodes for each port.  This provides the
	 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
	 */
	bspr = readl(rcba_mem + INTEL_BSPR_REG);
	bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
	if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
		updcr = readl(rcba_mem + INTEL_UPDCR_REG);
		if (updcr & INTEL_UPDCR_REG_MASK) {
			pci_info(dev, "Disabling UPDCR peer decodes\n");
			updcr &= ~INTEL_UPDCR_REG_MASK;
			writel(updcr, rcba_mem + INTEL_UPDCR_REG);
		}
	}

	iounmap(rcba_mem);
	return 0;
}

/* Miscellaneous Port Configuration register */
#define INTEL_MPC_REG 0xd8
/* MPC: Invalid Receive Bus Number Check Enable */
#define INTEL_MPC_REG_IRBNCE (1 << 26)

static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
{
	u32 mpc;

	/*
	 * When enabled, the IRBNCE bit of the MPC register enables the
	 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
	 * ensures that requester IDs fall within the bus number range
	 * of the bridge.  Enable if not already.
	 */
	pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
	if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
		pci_info(dev, "Enabling MPC IRBNCE\n");
		mpc |= INTEL_MPC_REG_IRBNCE;
		pci_write_config_word(dev, INTEL_MPC_REG, mpc);
	}
}

static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
{
	if (!pci_quirk_intel_pch_acs_match(dev))
		return -ENOTTY;

	if (pci_quirk_enable_intel_lpc_acs(dev)) {
		pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
		return 0;
	}

	pci_quirk_enable_intel_rp_mpc_acs(dev);

	dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;

	pci_info(dev, "Intel PCH root port ACS workaround enabled\n");

	return 0;
}

static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	ctrl |= (cap & PCI_ACS_SV);
	ctrl |= (cap & PCI_ACS_RR);
	ctrl |= (cap & PCI_ACS_CR);
	ctrl |= (cap & PCI_ACS_UF);

	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);

	pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");

	return 0;
}

static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
{
	int pos;
	u32 cap, ctrl;

	if (!pci_quirk_intel_spt_pch_acs_match(dev))
		return -ENOTTY;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return -ENOTTY;

	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);

	ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);

	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);

	pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");

	return 0;
}

static const struct pci_dev_acs_ops {
	u16 vendor;
	u16 device;
	int (*enable_acs)(struct pci_dev *dev);
	int (*disable_acs_redir)(struct pci_dev *dev);
} pci_dev_acs_ops[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	    .enable_acs = pci_quirk_enable_intel_pch_acs,
	},
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	    .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
	    .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
	},
};

int pci_dev_specific_enable_acs(struct pci_dev *dev)
{
	const struct pci_dev_acs_ops *p;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
		p = &pci_dev_acs_ops[i];
		if ((p->vendor == dev->vendor ||
		     p->vendor == (u16)PCI_ANY_ID) &&
		    (p->device == dev->device ||
		     p->device == (u16)PCI_ANY_ID) &&
		    p->enable_acs) {
			ret = p->enable_acs(dev);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
{
	const struct pci_dev_acs_ops *p;
	int i, ret;

	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
		p = &pci_dev_acs_ops[i];
		if ((p->vendor == dev->vendor ||
		     p->vendor == (u16)PCI_ANY_ID) &&
		    (p->device == dev->device ||
		     p->device == (u16)PCI_ANY_ID) &&
		    p->disable_acs_redir) {
			ret = p->disable_acs_redir(dev);
			if (ret >= 0)
				return ret;
		}
	}

	return -ENOTTY;
}

/*
 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
 * QuickAssist Technology (QAT) is prematurely terminated in hardware.  The
 * Next Capability pointer in the MSI Capability Structure should point to
 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
 * the list.
 */
static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
{
	int pos, i = 0;
	u8 next_cap;
	u16 reg16, *cap;
	struct pci_cap_saved_state *state;

	/* Bail if the hardware bug is fixed */
	if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
		return;

	/* Bail if MSI Capability Structure is not found for some reason */
	pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
	if (!pos)
		return;

	/*
	 * Bail if Next Capability pointer in the MSI Capability Structure
	 * is not the expected incorrect 0x00.
	 */
	pci_read_config_byte(pdev, pos + 1, &next_cap);
	if (next_cap)
		return;

	/*
	 * PCIe Capability Structure is expected to be at 0x50 and should
	 * terminate the list (Next Capability pointer is 0x00).  Verify
	 * Capability Id and Next Capability pointer is as expected.
	 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
	 * to correctly set kernel data structures which have already been
	 * set incorrectly due to the hardware bug.
	 */
	pos = 0x50;
	pci_read_config_word(pdev, pos, &reg16);
	if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
		u32 status;
#ifndef PCI_EXP_SAVE_REGS
#define PCI_EXP_SAVE_REGS     7
#endif
		int size = PCI_EXP_SAVE_REGS * sizeof(u16);

		pdev->pcie_cap = pos;
		pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
		pdev->pcie_flags_reg = reg16;
		pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
		pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;

		pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
		if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
		    PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
			pdev->cfg_size = PCI_CFG_SPACE_SIZE;

		if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
			return;

		/* Save PCIe cap */
		state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
		if (!state)
			return;

		state->cap.cap_nr = PCI_CAP_ID_EXP;
		state->cap.cap_extended = 0;
		state->cap.size = size;
		cap = (u16 *)&state->cap.data[0];
		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_RTCTL,  &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
		hlist_add_head(&state->next, &pdev->saved_cap_space);
	}
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);

/* FLR may cause some 82579 devices to hang */
static void quirk_intel_no_flr(struct pci_dev *dev)
{
	dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);

static void quirk_no_ext_tags(struct pci_dev *pdev)
{
	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);

	if (!bridge)
		return;

	bridge->no_ext_tags = 1;
	pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");

	pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);

#ifdef CONFIG_PCI_ATS
/*
 * Some devices have a broken ATS implementation causing IOMMU stalls.
 * Don't use ATS for those devices.
 */
static void quirk_no_ats(struct pci_dev *pdev)
{
	pci_info(pdev, "disabling ATS (broken on this device)\n");
	pdev->ats_cap = 0;
}

/* AMD Stoney platform GPU */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
#endif /* CONFIG_PCI_ATS */

/* Freescale PCIe doesn't support MSI in RC mode */
static void quirk_fsl_no_msi(struct pci_dev *pdev)
{
	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
		pdev->no_msi = 1;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);

/*
 * Although not allowed by the spec, some multi-function devices have
 * dependencies of one function (consumer) on another (supplier).  For the
 * consumer to work in D0, the supplier must also be in D0.  Create a
 * device link from the consumer to the supplier to enforce this
 * dependency.  Runtime PM is allowed by default on the consumer to prevent
 * it from permanently keeping the supplier awake.
 */
static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
				   unsigned int supplier, unsigned int class,
				   unsigned int class_shift)
{
	struct pci_dev *supplier_pdev;

	if (PCI_FUNC(pdev->devfn) != consumer)
		return;

	supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
				pdev->bus->number,
				PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
	if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
		pci_dev_put(supplier_pdev);
		return;
	}

	if (device_link_add(&pdev->dev, &supplier_pdev->dev,
			    DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
		pci_info(pdev, "D0 power state depends on %s\n",
			 pci_name(supplier_pdev));
	else
		pci_err(pdev, "Cannot enforce power dependency on %s\n",
			pci_name(supplier_pdev));

	pm_runtime_allow(&pdev->dev);
	pci_dev_put(supplier_pdev);
}

/*
 * Create device link for GPUs with integrated HDA controller for streaming
 * audio to attached displays.
 */
static void quirk_gpu_hda(struct pci_dev *hda)
{
	pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);

/*
 * Create device link for NVIDIA GPU with integrated USB xHCI Host
 * controller to VGA.
 */
static void quirk_gpu_usb(struct pci_dev *usb)
{
	pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);

/*
 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
 * to VGA. Currently there is no class code defined for UCSI device over PCI
 * so using UNKNOWN class for now and it will be updated when UCSI
 * over PCI gets a class code.
 */
#define PCI_CLASS_SERIAL_UNKNOWN	0x0c80
static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
{
	pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			      PCI_CLASS_SERIAL_UNKNOWN, 8,
			      quirk_gpu_usb_typec_ucsi);

/*
 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
 * disabled.  https://devtalk.nvidia.com/default/topic/1024022
 */
static void quirk_nvidia_hda(struct pci_dev *gpu)
{
	u8 hdr_type;
	u32 val;

	/* There was no integrated HDA controller before MCP89 */
	if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
		return;

	/* Bit 25 at offset 0x488 enables the HDA controller */
	pci_read_config_dword(gpu, 0x488, &val);
	if (val & BIT(25))
		return;

	pci_info(gpu, "Enabling HDA controller\n");
	pci_write_config_dword(gpu, 0x488, val | BIT(25));

	/* The GPU becomes a multi-function device when the HDA is enabled */
	pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
	gpu->multifunction = !!(hdr_type & 0x80);
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			       PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
			       PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);

/*
 * Some IDT switches incorrectly flag an ACS Source Validation error on
 * completions for config read requests even though PCIe r4.0, sec
 * 6.12.1.1, says that completions are never affected by ACS Source
 * Validation.  Here's the text of IDT 89H32H8G3-YC, erratum #36:
 *
 *   Item #36 - Downstream port applies ACS Source Validation to Completions
 *   Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
 *   completions are never affected by ACS Source Validation.  However,
 *   completions received by a downstream port of the PCIe switch from a
 *   device that has not yet captured a PCIe bus number are incorrectly
 *   dropped by ACS Source Validation by the switch downstream port.
 *
 * The workaround suggested by IDT is to issue a config write to the
 * downstream device before issuing the first config read.  This allows the
 * downstream device to capture its bus and device numbers (see PCIe r4.0,
 * sec 2.2.9), thus avoiding the ACS error on the completion.
 *
 * However, we don't know when the device is ready to accept the config
 * write, so we do config reads until we receive a non-Config Request Retry
 * Status, then do the config write.
 *
 * To avoid hitting the erratum when doing the config reads, we disable ACS
 * SV around this process.
 */
int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
{
	int pos;
	u16 ctrl = 0;
	bool found;
	struct pci_dev *bridge = bus->self;

	pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS);

	/* Disable ACS SV before initial config reads */
	if (pos) {
		pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
		if (ctrl & PCI_ACS_SV)
			pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
					      ctrl & ~PCI_ACS_SV);
	}

	found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);

	/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
	if (found)
		pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);

	/* Re-enable ACS_SV if it was previously enabled */
	if (ctrl & PCI_ACS_SV)
		pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);

	return found;
}

/*
 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
 * NT endpoints via the internal switch fabric. These IDs replace the
 * originating requestor ID TLPs which access host memory on peer NTB
 * ports. Therefore, all proxy IDs must be aliased to the NTB device
 * to permit access when the IOMMU is turned on.
 */
static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
{
	void __iomem *mmio;
	struct ntb_info_regs __iomem *mmio_ntb;
	struct ntb_ctrl_regs __iomem *mmio_ctrl;
	u64 partition_map;
	u8 partition;
	int pp;

	if (pci_enable_device(pdev)) {
		pci_err(pdev, "Cannot enable Switchtec device\n");
		return;
	}

	mmio = pci_iomap(pdev, 0, 0);
	if (mmio == NULL) {
		pci_disable_device(pdev);
		pci_err(pdev, "Cannot iomap Switchtec device\n");
		return;
	}

	pci_info(pdev, "Setting Switchtec proxy ID aliases\n");

	mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
	mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;

	partition = ioread8(&mmio_ntb->partition_id);

	partition_map = ioread32(&mmio_ntb->ep_map);
	partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
	partition_map &= ~(1ULL << partition);

	for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
		struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
		u32 table_sz = 0;
		int te;

		if (!(partition_map & (1ULL << pp)))
			continue;

		pci_dbg(pdev, "Processing partition %d\n", pp);

		mmio_peer_ctrl = &mmio_ctrl[pp];

		table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
		if (!table_sz) {
			pci_warn(pdev, "Partition %d table_sz 0\n", pp);
			continue;
		}

		if (table_sz > 512) {
			pci_warn(pdev,
				 "Invalid Switchtec partition %d table_sz %d\n",
				 pp, table_sz);
			continue;
		}

		for (te = 0; te < table_sz; te++) {
			u32 rid_entry;
			u8 devfn;

			rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
			devfn = (rid_entry >> 1) & 0xFF;
			pci_dbg(pdev,
				"Aliasing Partition %d Proxy ID %02x.%d\n",
				pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
			pci_add_dma_alias(pdev, devfn);
		}
	}

	pci_iounmap(pdev, mmio);
	pci_disable_device(pdev);
}
#define SWITCHTEC_QUIRK(vid) \
	DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
		PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)

SWITCHTEC_QUIRK(0x8531);  /* PFX 24xG3 */
SWITCHTEC_QUIRK(0x8532);  /* PFX 32xG3 */
SWITCHTEC_QUIRK(0x8533);  /* PFX 48xG3 */
SWITCHTEC_QUIRK(0x8534);  /* PFX 64xG3 */
SWITCHTEC_QUIRK(0x8535);  /* PFX 80xG3 */
SWITCHTEC_QUIRK(0x8536);  /* PFX 96xG3 */
SWITCHTEC_QUIRK(0x8541);  /* PSX 24xG3 */
SWITCHTEC_QUIRK(0x8542);  /* PSX 32xG3 */
SWITCHTEC_QUIRK(0x8543);  /* PSX 48xG3 */
SWITCHTEC_QUIRK(0x8544);  /* PSX 64xG3 */
SWITCHTEC_QUIRK(0x8545);  /* PSX 80xG3 */
SWITCHTEC_QUIRK(0x8546);  /* PSX 96xG3 */
SWITCHTEC_QUIRK(0x8551);  /* PAX 24XG3 */
SWITCHTEC_QUIRK(0x8552);  /* PAX 32XG3 */
SWITCHTEC_QUIRK(0x8553);  /* PAX 48XG3 */
SWITCHTEC_QUIRK(0x8554);  /* PAX 64XG3 */
SWITCHTEC_QUIRK(0x8555);  /* PAX 80XG3 */
SWITCHTEC_QUIRK(0x8556);  /* PAX 96XG3 */
SWITCHTEC_QUIRK(0x8561);  /* PFXL 24XG3 */
SWITCHTEC_QUIRK(0x8562);  /* PFXL 32XG3 */
SWITCHTEC_QUIRK(0x8563);  /* PFXL 48XG3 */
SWITCHTEC_QUIRK(0x8564);  /* PFXL 64XG3 */
SWITCHTEC_QUIRK(0x8565);  /* PFXL 80XG3 */
SWITCHTEC_QUIRK(0x8566);  /* PFXL 96XG3 */
SWITCHTEC_QUIRK(0x8571);  /* PFXI 24XG3 */
SWITCHTEC_QUIRK(0x8572);  /* PFXI 32XG3 */
SWITCHTEC_QUIRK(0x8573);  /* PFXI 48XG3 */
SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */

/*
 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
 * not always reset the secondary Nvidia GPU between reboots if the system
 * is configured to use Hybrid Graphics mode.  This results in the GPU
 * being left in whatever state it was in during the *previous* boot, which
 * causes spurious interrupts from the GPU, which in turn causes us to
 * disable the wrong IRQ and end up breaking the touchpad.  Unsurprisingly,
 * this also completely breaks nouveau.
 *
 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
 * clean state and fixes all these issues.
 *
 * When the machine is configured in Dedicated display mode, the issue
 * doesn't occur.  Fortunately the GPU advertises NoReset+ when in this
 * mode, so we can detect that and avoid resetting it.
 */
static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
{
	void __iomem *map;
	int ret;

	if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
	    pdev->subsystem_device != 0x222e ||
	    !pdev->reset_fn)
		return;

	if (pci_enable_device_mem(pdev))
		return;

	/*
	 * Based on nvkm_device_ctor() in
	 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
	 */
	map = pci_iomap(pdev, 0, 0x23000);
	if (!map) {
		pci_err(pdev, "Can't map MMIO space\n");
		goto out_disable;
	}

	/*
	 * Make sure the GPU looks like it's been POSTed before resetting
	 * it.
	 */
	if (ioread32(map + 0x2240c) & 0x2) {
		pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
		ret = pci_reset_bus(pdev);
		if (ret < 0)
			pci_err(pdev, "Failed to reset GPU: %d\n", ret);
	}

	iounmap(map);
out_disable:
	pci_disable_device(pdev);
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
			      PCI_CLASS_DISPLAY_VGA, 8,
			      quirk_reset_lenovo_thinkpad_p50_nvgpu);

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Hi Dominik
Thanks for your continued help. I used the file you attached and tried
a compile on 4.19.80 here is the outout of the failure
  CC [M]  drivers/net/wireless/marvell/mwifiex/uap_txrx.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/cfg80211.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/ethtool.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/11h.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/tdls.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/debugfs.o
  LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/sdio.o
  LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex_sdio.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/pcie.o
  LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex_pcie.o
  CC [M]  drivers/net/wireless/marvell/mwifiex/usb.o
  LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex_usb.o
  AR      drivers/net/wireless/marvell/built-in.a
  CC [M]  drivers/net/wireless/marvell/mwl8k.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/usb.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/init.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/main.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/mcu.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/trace.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/dma.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/phy.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/mac.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/util.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/debugfs.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/tx.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/core.o
  LD [M]  drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mmio.o
  CC [M]  drivers/net/wireless/mediatek/mt76/util.o
  CC [M]  drivers/net/wireless/mediatek/mt76/trace.o
  CC [M]  drivers/net/wireless/mediatek/mt76/dma.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mac80211.o
  CC [M]  drivers/net/wireless/mediatek/mt76/debugfs.o
  CC [M]  drivers/net/wireless/mediatek/mt76/eeprom.o
  CC [M]  drivers/net/wireless/mediatek/mt76/tx.o
  CC [M]  drivers/net/wireless/mediatek/mt76/agg-rx.o
  LD [M]  drivers/net/wireless/mediatek/mt76/mt76.o
  CC [M]  drivers/net/wireless/mediatek/mt76/usb.o
  CC [M]  drivers/net/wireless/mediatek/mt76/usb_trace.o
  CC [M]  drivers/net/wireless/mediatek/mt76/usb_mcu.o
  LD [M]  drivers/net/wireless/mediatek/mt76/mt76-usb.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_eeprom.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_tx_common.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_mac_common.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_init_common.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_common.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_phy_common.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_debugfs.o
  LD [M]  drivers/net/wireless/mediatek/mt76/mt76x2-common.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_pci.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_dma.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_main.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_init.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_tx.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_core.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_mac.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_mcu.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_phy.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_dfs.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_trace.o
  LD [M]  drivers/net/wireless/mediatek/mt76/mt76x2e.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_usb.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_init.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_main.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_mac.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_mcu.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_phy.o
  CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_core.o
  LD [M]  drivers/net/wireless/mediatek/mt76/mt76x2u.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/usb.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/init.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/main.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/mcu.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/trace.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/dma.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/core.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/eeprom.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/phy.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/mac.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/util.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/debugfs.o
  CC [M]  drivers/net/wireless/mediatek/mt7601u/tx.o
  LD [M]  drivers/net/wireless/mediatek/mt7601u/mt7601u.o
  AR      drivers/net/wireless/mediatek/built-in.a
  AR      drivers/net/wireless/quantenna/built-in.a
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00dev.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00mac.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00config.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00queue.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00link.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00crypto.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00firmware.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00leds.o
  LD [M]  drivers/net/wireless/ralink/rt2x00/rt2x00lib.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00mmio.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00pci.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00usb.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800lib.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800mmio.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2400pci.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2500pci.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt61pci.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800pci.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2500usb.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt73usb.o
  CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800usb.o
  AR      drivers/net/wireless/ralink/built-in.a
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/dev.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/sa2400.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/max2820.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/grf5101.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225se.o
  LD [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/rtl818x_pci.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/dev.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/leds.o
  CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/rfkill.o
  LD [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.o
  CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.o
  CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.o
  CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.o
  CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.o
  CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.o
  LD [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/rtl_btc.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/btcoexist.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rtl8188ee.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/main.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/rtl8192c-common.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rtl8192ce.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/mac.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/rtl8192cu.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/rtl8192de.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/rtl8192ee.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/rtl8192se.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/rtl8723ae.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/rtl8723be.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/main.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/dm_common.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/rtl8723-common.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rtl8821ae.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/base.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/cam.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/core.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/debug.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/efuse.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/ps.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/rc.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/regd.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/stats.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtlwifi.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/pci.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl_pci.o
  CC [M]  drivers/net/wireless/realtek/rtlwifi/usb.o
  LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl_usb.o
  AR      drivers/net/wireless/realtek/built-in.a
  AR      drivers/net/wireless/rsi/built-in.a
  CC [M]  drivers/net/wireless/rsi/rsi_91x_main.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_core.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_mac80211.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_mgmt.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_hal.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_ps.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_coex.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_debugfs.o
  LD [M]  drivers/net/wireless/rsi/rsi_91x.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_usb.o
  CC [M]  drivers/net/wireless/rsi/rsi_91x_usb_ops.o
  LD [M]  drivers/net/wireless/rsi/rsi_usb.o
  AR      drivers/net/wireless/st/built-in.a
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_chip.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_mac.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_al2230.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_al7230b.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf.o
  CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_usb.o
  LD [M]  drivers/net/wireless/zydas/zd1211rw/zd1211rw.o
  AR      drivers/net/wireless/zydas/built-in.a
  CC [M]  drivers/net/wireless/zydas/zd1201.o
  AR      drivers/net/wireless/built-in.a
  CC [M]  drivers/net/wireless/ray_cs.o
  CC [M]  drivers/net/wireless/wl3501_cs.o
  CC [M]  drivers/net/wireless/rndis_wlan.o
  CC [M]  drivers/net/wireless/mac80211_hwsim.o
  CC [M]  drivers/net/xen-netback/netback.o
  CC [M]  drivers/net/xen-netback/xenbus.o
  CC [M]  drivers/net/xen-netback/interface.o
  CC [M]  drivers/net/xen-netback/hash.o
  CC [M]  drivers/net/xen-netback/rx.o
  LD [M]  drivers/net/xen-netback/xen-netback.o
  CC      drivers/net/Space.o
  CC      drivers/net/loopback.o
  AR      drivers/net/built-in.a
  CC [M]  drivers/net/dummy.o
  CC [M]  drivers/net/eql.o
  CC [M]  drivers/net/ifb.o
  CC [M]  drivers/net/macsec.o
  CC [M]  drivers/net/macvlan.o
  CC [M]  drivers/net/macvtap.o
  CC [M]  drivers/net/mii.o
  CC [M]  drivers/net/mdio.o
  CC [M]  drivers/net/netconsole.o
  CC [M]  drivers/net/tun.o
  CC [M]  drivers/net/tap.o
  CC [M]  drivers/net/veth.o
  CC [M]  drivers/net/virtio_net.o
  CC [M]  drivers/net/vxlan.o
  CC [M]  drivers/net/geneve.o
  CC [M]  drivers/net/gtp.o
  CC [M]  drivers/net/nlmon.o
  CC [M]  drivers/net/vrf.o
  CC [M]  drivers/net/vsockmon.o
  CC [M]  drivers/net/sb1000.o
  CC [M]  drivers/net/sungem_phy.o
  CC [M]  drivers/net/xen-netfront.o
  CC [M]  drivers/net/thunderbolt.o
  LD [M]  drivers/net/thunderbolt-net.o
  CC [M]  drivers/net/net_failover.o
  CC [M]  drivers/nfc/pn533/pn533.o
  CC [M]  drivers/nfc/pn533/usb.o
  LD [M]  drivers/nfc/pn533/pn533_usb.o
  CC [M]  drivers/nfc/pn544/pn544.o
  CC [M]  drivers/nfc/pn544/mei.o
  LD [M]  drivers/nfc/pn544/pn544_mei.o
  AR      drivers/nfc/built-in.a
  CC [M]  drivers/nfc/mei_phy.o
  CC [M]  drivers/nfc/nfcsim.o
  CC [M]  drivers/nfc/port100.o
  CC [M]  drivers/nvdimm/core.o
  CC [M]  drivers/nvdimm/bus.o
  CC [M]  drivers/nvdimm/dimm_devs.o
  CC [M]  drivers/nvdimm/dimm.o
  CC [M]  drivers/nvdimm/region_devs.o
  CC [M]  drivers/nvdimm/region.o
  CC [M]  drivers/nvdimm/namespace_devs.o
  CC [M]  drivers/nvdimm/label.o
  CC [M]  drivers/nvdimm/badrange.o
  CC [M]  drivers/nvdimm/claim.o
  CC [M]  drivers/nvdimm/btt_devs.o
  LD [M]  drivers/nvdimm/libnvdimm.o
  CC [M]  drivers/nvdimm/pmem.o
  LD [M]  drivers/nvdimm/nd_pmem.o
  CC [M]  drivers/nvdimm/btt.o
  LD [M]  drivers/nvdimm/nd_btt.o
  CC [M]  drivers/nvdimm/blk.o
  LD [M]  drivers/nvdimm/nd_blk.o
  CC [M]  drivers/nvdimm/e820.o
  LD [M]  drivers/nvdimm/nd_e820.o
  AR      drivers/nvme/host/built-in.a
  CC [M]  drivers/nvme/host/core.o
  CC [M]  drivers/nvme/host/trace.o
  CC [M]  drivers/nvme/host/multipath.o
  LD [M]  drivers/nvme/host/nvme-core.o
  CC [M]  drivers/nvme/host/pci.o
  LD [M]  drivers/nvme/host/nvme.o
  CC [M]  drivers/nvme/host/fabrics.o
  LD [M]  drivers/nvme/host/nvme-fabrics.o
  CC [M]  drivers/nvme/host/rdma.o
  LD [M]  drivers/nvme/host/nvme-rdma.o
  CC [M]  drivers/nvme/host/fc.o
  LD [M]  drivers/nvme/host/nvme-fc.o
  AR      drivers/nvme/target/built-in.a
  CC [M]  drivers/nvme/target/core.o
  CC [M]  drivers/nvme/target/configfs.o
  CC [M]  drivers/nvme/target/admin-cmd.o
  CC [M]  drivers/nvme/target/fabrics-cmd.o
  CC [M]  drivers/nvme/target/discovery.o
  CC [M]  drivers/nvme/target/io-cmd-file.o
  CC [M]  drivers/nvme/target/io-cmd-bdev.o
  LD [M]  drivers/nvme/target/nvmet.o
  CC [M]  drivers/nvme/target/rdma.o
  LD [M]  drivers/nvme/target/nvmet-rdma.o
  CC [M]  drivers/nvme/target/fc.o
  LD [M]  drivers/nvme/target/nvmet-fc.o
  AR      drivers/nvme/built-in.a
  CC      drivers/nvmem/core.o
  AR      drivers/nvmem/built-in.a
  CC      drivers/opp/core.o
  CC      drivers/opp/cpu.o
  CC      drivers/opp/debugfs.o
  AR      drivers/opp/built-in.a
  CC [M]  drivers/parport/share.o
  CC [M]  drivers/parport/ieee1284.o
  CC [M]  drivers/parport/ieee1284_ops.o
  CC [M]  drivers/parport/procfs.o
  CC [M]  drivers/parport/daisy.o
  CC [M]  drivers/parport/probe.o
  LD [M]  drivers/parport/parport.o
  CC [M]  drivers/parport/parport_pc.o
  CC [M]  drivers/parport/parport_serial.o
  CC [M]  drivers/parport/parport_cs.o
  AR      drivers/pci/controller/dwc/built-in.a
  AR      drivers/pci/controller/built-in.a
  CC      drivers/pci/hotplug/pci_hotplug_core.o
  CC      drivers/pci/hotplug/cpci_hotplug_core.o
  CC      drivers/pci/hotplug/cpci_hotplug_pci.o
  CC      drivers/pci/hotplug/acpi_pcihp.o
  CC      drivers/pci/hotplug/pciehp_core.o
  CC      drivers/pci/hotplug/pciehp_ctrl.o
  CC      drivers/pci/hotplug/pciehp_pci.o
  CC      drivers/pci/hotplug/pciehp_hpc.o
  CC      drivers/pci/hotplug/shpchp_core.o
  CC      drivers/pci/hotplug/shpchp_ctrl.o
  CC      drivers/pci/hotplug/shpchp_pci.o
  CC      drivers/pci/hotplug/shpchp_sysfs.o
  CC      drivers/pci/hotplug/shpchp_hpc.o
  CC      drivers/pci/hotplug/acpiphp_core.o
  CC      drivers/pci/hotplug/acpiphp_glue.o
  AR      drivers/pci/hotplug/built-in.a
  CC [M]  drivers/pci/hotplug/cpqphp_core.o
  CC [M]  drivers/pci/hotplug/cpqphp_ctrl.o
  CC [M]  drivers/pci/hotplug/cpqphp_sysfs.o
  CC [M]  drivers/pci/hotplug/cpqphp_pci.o
  LD [M]  drivers/pci/hotplug/cpqphp.o
  CC [M]  drivers/pci/hotplug/ibmphp_core.o
  CC [M]  drivers/pci/hotplug/ibmphp_ebda.o
  CC [M]  drivers/pci/hotplug/ibmphp_pci.o
  CC [M]  drivers/pci/hotplug/ibmphp_res.o
  CC [M]  drivers/pci/hotplug/ibmphp_hpc.o
  LD [M]  drivers/pci/hotplug/ibmphp.o
  CC [M]  drivers/pci/hotplug/cpcihp_zt5550.o
  CC [M]  drivers/pci/hotplug/cpcihp_generic.o
  CC [M]  drivers/pci/hotplug/acpiphp_ibm.o
  CC      drivers/pci/pcie/portdrv_core.o
  CC      drivers/pci/pcie/portdrv_pci.o
  CC      drivers/pci/pcie/err.o
  CC      drivers/pci/pcie/aspm.o
  CC      drivers/pci/pcie/aer.o
  CC      drivers/pci/pcie/pme.o
  CC      drivers/pci/pcie/dpc.o
  CC      drivers/pci/pcie/ptm.o
  AR      drivers/pci/pcie/built-in.a
  CC [M]  drivers/pci/pcie/aer_inject.o
  AR      drivers/pci/switch/built-in.a
  CC      drivers/pci/access.o
  CC      drivers/pci/bus.o
  CC      drivers/pci/probe.o
  CC      drivers/pci/host-bridge.o
  CC      drivers/pci/remove.o
  CC      drivers/pci/pci.o
  CC      drivers/pci/pci-driver.o
  CC      drivers/pci/search.o
  CC      drivers/pci/pci-sysfs.o
  CC      drivers/pci/rom.o
  CC      drivers/pci/setup-res.o
  CC      drivers/pci/irq.o
  CC      drivers/pci/vpd.o
  CC      drivers/pci/setup-bus.o
  CC      drivers/pci/vc.o
  CC      drivers/pci/mmap.o
  CC      drivers/pci/setup-irq.o
  CC      drivers/pci/proc.o
  CC      drivers/pci/slot.o
  CC      drivers/pci/quirks.o
drivers/pci/quirks.c: In function ‘quirk_synopsys_haps’:
drivers/pci/quirks.c:631:7: error: ‘PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3’
undeclared (first use in this function); did you mean
‘PCI_DEVICE_ID_ESS_MAESTRO3’?
  case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
       PCI_DEVICE_ID_ESS_MAESTRO3
drivers/pci/quirks.c:631:7: note: each undeclared identifier is
reported only once for each function it appears in
drivers/pci/quirks.c:632:7: error:
‘PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI’ undeclared (first use in this
function); did you mean ‘PCI_DEVICE_ID_SUN_CASSINI’?
  case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
       PCI_DEVICE_ID_SUN_CASSINI
drivers/pci/quirks.c:633:7: error: ‘PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31’
undeclared (first use in this function); did you mean
‘PCI_DEVICE_ID_SUN_CASSINI’?
  case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
       PCI_DEVICE_ID_SUN_CASSINI
drivers/pci/quirks.c: In function ‘quirk_disable_aspm_l0s’:
drivers/pci/quirks.c:2229:2: error: implicit declaration of function
‘pci_disable_link_state’; did you mean ‘pci_restore_iov_state’?
[-Werror=implicit-function-declaration]
  pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
  ^~~~~~~~~~~~~~~~~~~~~~
  pci_restore_iov_state
drivers/pci/quirks.c:2229:30: error: ‘PCIE_LINK_STATE_L0S’ undeclared
(first use in this function); did you mean ‘PCIE_LNK_WIDTH_RESRV’?
  pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
                              ^~~~~~~~~~~~~~~~~~~
                              PCIE_LNK_WIDTH_RESRV
drivers/pci/quirks.c: At top level:
drivers/pci/quirks.c:4612:4: error: ‘PCI_VENDOR_ID_HXT’ undeclared
here (not in a function); did you mean ‘PCI_VENDOR_ID_ATT’?
  { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
    ^~~~~~~~~~~~~~~~~
    PCI_VENDOR_ID_ATT
drivers/pci/quirks.c:4633:4: error:
‘PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS’ undeclared here (not in a
function); did you mean ‘PCI_VENDOR_ID_AMAZON’?
  { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    PCI_VENDOR_ID_AMAZON
drivers/pci/quirks.c: In function ‘quirk_nvidia_hda’:
drivers/pci/quirks.c:5096:20: error:
‘PCI_DEVICE_ID_NVIDIA_GEFORCE_320M’ undeclared (first use in this
function); did you mean ‘PCI_DEVICE_ID_NVIDIA_GEFORCE_6200’?
  if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                    PCI_DEVICE_ID_NVIDIA_GEFORCE_6200
drivers/pci/quirks.c:5096:18: warning: comparison between pointer and integer
  if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
                  ^
cc1: some warnings being treated as errors
make[5]: *** [scripts/Makefile.build:304: drivers/pci/quirks.o] Error 1
make[4]: *** [scripts/Makefile.build:544: drivers/pci] Error 2
make[3]: *** [Makefile:1046: drivers] Error 2
make[2]: *** [debian/rules:4: build] Error 2
dpkg-buildpackage: error: debian/rules build subprocess returned exit status 2
make[1]: *** [scripts/package/Makefile:75: deb-pkg] Error 2
make: *** [Makefile:1359: deb-pkg] Error 2
root@CF-29:/home/michael/kernel/linux-4.19.80#

I will now try a compile of 5.4-rc1
Cheers.
Michael.


On 25/10/2019, Dominik Brodowski <linux@dominikbrodowski.net> wrote:
> The patch doesn't seem to have been applied correctly (using the patch(1)
> utility). Attached is the file how it should look like.
>
> 	Dominik
>
> On Fri, Oct 25, 2019 at 01:38:46PM +1100, Michael . wrote:
>> Here's the resulting output of the failed compilation of 5.4rc1 with
>> the patch applied to quirks.c:
>>  CC      drivers/pci/quirks.o
>> drivers/pci/quirks.c:3039:1: error: expected identifier or ‘(’ before ‘-’
>> token
>>  3039 | -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
>>       | ^
>> drivers/pci/quirks.c:3068:1: error: expected identifier or ‘(’ before ‘-’
>> token
>
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Bjorn and Dominik.
I am happy to let you know the patch did the trick, it compiled well
on 5.4-rc4 and my friends in the CC list have tested the modified
kernel and confirmed that both slots are now working as they should.
As a group of dedicated Toughbook users and Linux users please accept
our thanks your efforts and assistance is greatly appreciated.

Now that we knwo this patch works what kernel do you think it will be
released in? Will it make 5.4 or will it be put into 5.5 development
for further testing?

Thanks again.
Michael Findlay on behalf of many others.

On 26/10/2019, Michael . <keltoiboy@gmail.com> wrote:
> Hi Dominik
> Thanks for your continued help. I used the file you attached and tried
> a compile on 4.19.80 here is the outout of the failure
>   CC [M]  drivers/net/wireless/marvell/mwifiex/uap_txrx.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/cfg80211.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/ethtool.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/11h.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/tdls.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/debugfs.o
>   LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/sdio.o
>   LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex_sdio.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/pcie.o
>   LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex_pcie.o
>   CC [M]  drivers/net/wireless/marvell/mwifiex/usb.o
>   LD [M]  drivers/net/wireless/marvell/mwifiex/mwifiex_usb.o
>   AR      drivers/net/wireless/marvell/built-in.a
>   CC [M]  drivers/net/wireless/marvell/mwl8k.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/usb.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/init.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/main.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/mcu.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/trace.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/dma.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/phy.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/mac.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/util.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/debugfs.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/tx.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x0/core.o
>   LD [M]  drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mmio.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/util.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/trace.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/dma.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mac80211.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/debugfs.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/eeprom.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/tx.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/agg-rx.o
>   LD [M]  drivers/net/wireless/mediatek/mt76/mt76.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/usb.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/usb_trace.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/usb_mcu.o
>   LD [M]  drivers/net/wireless/mediatek/mt76/mt76-usb.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_eeprom.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_tx_common.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_mac_common.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_init_common.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_common.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_phy_common.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_debugfs.o
>   LD [M]  drivers/net/wireless/mediatek/mt76/mt76x2-common.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_pci.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_dma.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_main.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_init.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_tx.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_core.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_mac.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_mcu.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_phy.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_dfs.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_trace.o
>   LD [M]  drivers/net/wireless/mediatek/mt76/mt76x2e.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2_usb.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_init.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_main.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_mac.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_mcu.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_phy.o
>   CC [M]  drivers/net/wireless/mediatek/mt76/mt76x2u_core.o
>   LD [M]  drivers/net/wireless/mediatek/mt76/mt76x2u.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/usb.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/init.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/main.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/mcu.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/trace.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/dma.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/core.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/eeprom.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/phy.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/mac.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/util.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/debugfs.o
>   CC [M]  drivers/net/wireless/mediatek/mt7601u/tx.o
>   LD [M]  drivers/net/wireless/mediatek/mt7601u/mt7601u.o
>   AR      drivers/net/wireless/mediatek/built-in.a
>   AR      drivers/net/wireless/quantenna/built-in.a
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00dev.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00mac.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00config.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00queue.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00link.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00crypto.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00firmware.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00leds.o
>   LD [M]  drivers/net/wireless/ralink/rt2x00/rt2x00lib.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00mmio.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00pci.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2x00usb.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800lib.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800mmio.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2400pci.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2500pci.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt61pci.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800pci.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2500usb.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt73usb.o
>   CC [M]  drivers/net/wireless/ralink/rt2x00/rt2800usb.o
>   AR      drivers/net/wireless/ralink/built-in.a
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/dev.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/sa2400.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/max2820.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/grf5101.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225se.o
>   LD [M]  drivers/net/wireless/realtek/rtl818x/rtl8180/rtl818x_pci.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/dev.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/leds.o
>   CC [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/rfkill.o
>   LD [M]  drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.o
>   CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.o
>   CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.o
>   CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.o
>   CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.o
>   CC [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.o
>   LD [M]  drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8192e2ant.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b1ant.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8723b2ant.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a1ant.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtc8821a2ant.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/rtl_btc.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/btcoexist/btcoexist.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8188ee/rtl8188ee.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/main.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/fw_common.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192c/rtl8192c-common.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rtl8192ce.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/mac.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192cu/rtl8192cu.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192de/rtl8192de.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192ee/rtl8192ee.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8192se/rtl8192se.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_btc.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hal_bt_coexist.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723ae/rtl8723ae.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723be/rtl8723be.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/main.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/dm_common.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/fw_common.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8723com/rtl8723-common.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/fw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/led.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rf.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rtl8821ae.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/base.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/cam.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/core.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/debug.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/efuse.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/ps.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/rc.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/regd.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/stats.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtlwifi.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/pci.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl_pci.o
>   CC [M]  drivers/net/wireless/realtek/rtlwifi/usb.o
>   LD [M]  drivers/net/wireless/realtek/rtlwifi/rtl_usb.o
>   AR      drivers/net/wireless/realtek/built-in.a
>   AR      drivers/net/wireless/rsi/built-in.a
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_main.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_core.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_mac80211.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_mgmt.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_hal.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_ps.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_coex.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_debugfs.o
>   LD [M]  drivers/net/wireless/rsi/rsi_91x.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_usb.o
>   CC [M]  drivers/net/wireless/rsi/rsi_91x_usb_ops.o
>   LD [M]  drivers/net/wireless/rsi/rsi_usb.o
>   AR      drivers/net/wireless/st/built-in.a
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_chip.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_mac.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_al2230.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_al7230b.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_rf.o
>   CC [M]  drivers/net/wireless/zydas/zd1211rw/zd_usb.o
>   LD [M]  drivers/net/wireless/zydas/zd1211rw/zd1211rw.o
>   AR      drivers/net/wireless/zydas/built-in.a
>   CC [M]  drivers/net/wireless/zydas/zd1201.o
>   AR      drivers/net/wireless/built-in.a
>   CC [M]  drivers/net/wireless/ray_cs.o
>   CC [M]  drivers/net/wireless/wl3501_cs.o
>   CC [M]  drivers/net/wireless/rndis_wlan.o
>   CC [M]  drivers/net/wireless/mac80211_hwsim.o
>   CC [M]  drivers/net/xen-netback/netback.o
>   CC [M]  drivers/net/xen-netback/xenbus.o
>   CC [M]  drivers/net/xen-netback/interface.o
>   CC [M]  drivers/net/xen-netback/hash.o
>   CC [M]  drivers/net/xen-netback/rx.o
>   LD [M]  drivers/net/xen-netback/xen-netback.o
>   CC      drivers/net/Space.o
>   CC      drivers/net/loopback.o
>   AR      drivers/net/built-in.a
>   CC [M]  drivers/net/dummy.o
>   CC [M]  drivers/net/eql.o
>   CC [M]  drivers/net/ifb.o
>   CC [M]  drivers/net/macsec.o
>   CC [M]  drivers/net/macvlan.o
>   CC [M]  drivers/net/macvtap.o
>   CC [M]  drivers/net/mii.o
>   CC [M]  drivers/net/mdio.o
>   CC [M]  drivers/net/netconsole.o
>   CC [M]  drivers/net/tun.o
>   CC [M]  drivers/net/tap.o
>   CC [M]  drivers/net/veth.o
>   CC [M]  drivers/net/virtio_net.o
>   CC [M]  drivers/net/vxlan.o
>   CC [M]  drivers/net/geneve.o
>   CC [M]  drivers/net/gtp.o
>   CC [M]  drivers/net/nlmon.o
>   CC [M]  drivers/net/vrf.o
>   CC [M]  drivers/net/vsockmon.o
>   CC [M]  drivers/net/sb1000.o
>   CC [M]  drivers/net/sungem_phy.o
>   CC [M]  drivers/net/xen-netfront.o
>   CC [M]  drivers/net/thunderbolt.o
>   LD [M]  drivers/net/thunderbolt-net.o
>   CC [M]  drivers/net/net_failover.o
>   CC [M]  drivers/nfc/pn533/pn533.o
>   CC [M]  drivers/nfc/pn533/usb.o
>   LD [M]  drivers/nfc/pn533/pn533_usb.o
>   CC [M]  drivers/nfc/pn544/pn544.o
>   CC [M]  drivers/nfc/pn544/mei.o
>   LD [M]  drivers/nfc/pn544/pn544_mei.o
>   AR      drivers/nfc/built-in.a
>   CC [M]  drivers/nfc/mei_phy.o
>   CC [M]  drivers/nfc/nfcsim.o
>   CC [M]  drivers/nfc/port100.o
>   CC [M]  drivers/nvdimm/core.o
>   CC [M]  drivers/nvdimm/bus.o
>   CC [M]  drivers/nvdimm/dimm_devs.o
>   CC [M]  drivers/nvdimm/dimm.o
>   CC [M]  drivers/nvdimm/region_devs.o
>   CC [M]  drivers/nvdimm/region.o
>   CC [M]  drivers/nvdimm/namespace_devs.o
>   CC [M]  drivers/nvdimm/label.o
>   CC [M]  drivers/nvdimm/badrange.o
>   CC [M]  drivers/nvdimm/claim.o
>   CC [M]  drivers/nvdimm/btt_devs.o
>   LD [M]  drivers/nvdimm/libnvdimm.o
>   CC [M]  drivers/nvdimm/pmem.o
>   LD [M]  drivers/nvdimm/nd_pmem.o
>   CC [M]  drivers/nvdimm/btt.o
>   LD [M]  drivers/nvdimm/nd_btt.o
>   CC [M]  drivers/nvdimm/blk.o
>   LD [M]  drivers/nvdimm/nd_blk.o
>   CC [M]  drivers/nvdimm/e820.o
>   LD [M]  drivers/nvdimm/nd_e820.o
>   AR      drivers/nvme/host/built-in.a
>   CC [M]  drivers/nvme/host/core.o
>   CC [M]  drivers/nvme/host/trace.o
>   CC [M]  drivers/nvme/host/multipath.o
>   LD [M]  drivers/nvme/host/nvme-core.o
>   CC [M]  drivers/nvme/host/pci.o
>   LD [M]  drivers/nvme/host/nvme.o
>   CC [M]  drivers/nvme/host/fabrics.o
>   LD [M]  drivers/nvme/host/nvme-fabrics.o
>   CC [M]  drivers/nvme/host/rdma.o
>   LD [M]  drivers/nvme/host/nvme-rdma.o
>   CC [M]  drivers/nvme/host/fc.o
>   LD [M]  drivers/nvme/host/nvme-fc.o
>   AR      drivers/nvme/target/built-in.a
>   CC [M]  drivers/nvme/target/core.o
>   CC [M]  drivers/nvme/target/configfs.o
>   CC [M]  drivers/nvme/target/admin-cmd.o
>   CC [M]  drivers/nvme/target/fabrics-cmd.o
>   CC [M]  drivers/nvme/target/discovery.o
>   CC [M]  drivers/nvme/target/io-cmd-file.o
>   CC [M]  drivers/nvme/target/io-cmd-bdev.o
>   LD [M]  drivers/nvme/target/nvmet.o
>   CC [M]  drivers/nvme/target/rdma.o
>   LD [M]  drivers/nvme/target/nvmet-rdma.o
>   CC [M]  drivers/nvme/target/fc.o
>   LD [M]  drivers/nvme/target/nvmet-fc.o
>   AR      drivers/nvme/built-in.a
>   CC      drivers/nvmem/core.o
>   AR      drivers/nvmem/built-in.a
>   CC      drivers/opp/core.o
>   CC      drivers/opp/cpu.o
>   CC      drivers/opp/debugfs.o
>   AR      drivers/opp/built-in.a
>   CC [M]  drivers/parport/share.o
>   CC [M]  drivers/parport/ieee1284.o
>   CC [M]  drivers/parport/ieee1284_ops.o
>   CC [M]  drivers/parport/procfs.o
>   CC [M]  drivers/parport/daisy.o
>   CC [M]  drivers/parport/probe.o
>   LD [M]  drivers/parport/parport.o
>   CC [M]  drivers/parport/parport_pc.o
>   CC [M]  drivers/parport/parport_serial.o
>   CC [M]  drivers/parport/parport_cs.o
>   AR      drivers/pci/controller/dwc/built-in.a
>   AR      drivers/pci/controller/built-in.a
>   CC      drivers/pci/hotplug/pci_hotplug_core.o
>   CC      drivers/pci/hotplug/cpci_hotplug_core.o
>   CC      drivers/pci/hotplug/cpci_hotplug_pci.o
>   CC      drivers/pci/hotplug/acpi_pcihp.o
>   CC      drivers/pci/hotplug/pciehp_core.o
>   CC      drivers/pci/hotplug/pciehp_ctrl.o
>   CC      drivers/pci/hotplug/pciehp_pci.o
>   CC      drivers/pci/hotplug/pciehp_hpc.o
>   CC      drivers/pci/hotplug/shpchp_core.o
>   CC      drivers/pci/hotplug/shpchp_ctrl.o
>   CC      drivers/pci/hotplug/shpchp_pci.o
>   CC      drivers/pci/hotplug/shpchp_sysfs.o
>   CC      drivers/pci/hotplug/shpchp_hpc.o
>   CC      drivers/pci/hotplug/acpiphp_core.o
>   CC      drivers/pci/hotplug/acpiphp_glue.o
>   AR      drivers/pci/hotplug/built-in.a
>   CC [M]  drivers/pci/hotplug/cpqphp_core.o
>   CC [M]  drivers/pci/hotplug/cpqphp_ctrl.o
>   CC [M]  drivers/pci/hotplug/cpqphp_sysfs.o
>   CC [M]  drivers/pci/hotplug/cpqphp_pci.o
>   LD [M]  drivers/pci/hotplug/cpqphp.o
>   CC [M]  drivers/pci/hotplug/ibmphp_core.o
>   CC [M]  drivers/pci/hotplug/ibmphp_ebda.o
>   CC [M]  drivers/pci/hotplug/ibmphp_pci.o
>   CC [M]  drivers/pci/hotplug/ibmphp_res.o
>   CC [M]  drivers/pci/hotplug/ibmphp_hpc.o
>   LD [M]  drivers/pci/hotplug/ibmphp.o
>   CC [M]  drivers/pci/hotplug/cpcihp_zt5550.o
>   CC [M]  drivers/pci/hotplug/cpcihp_generic.o
>   CC [M]  drivers/pci/hotplug/acpiphp_ibm.o
>   CC      drivers/pci/pcie/portdrv_core.o
>   CC      drivers/pci/pcie/portdrv_pci.o
>   CC      drivers/pci/pcie/err.o
>   CC      drivers/pci/pcie/aspm.o
>   CC      drivers/pci/pcie/aer.o
>   CC      drivers/pci/pcie/pme.o
>   CC      drivers/pci/pcie/dpc.o
>   CC      drivers/pci/pcie/ptm.o
>   AR      drivers/pci/pcie/built-in.a
>   CC [M]  drivers/pci/pcie/aer_inject.o
>   AR      drivers/pci/switch/built-in.a
>   CC      drivers/pci/access.o
>   CC      drivers/pci/bus.o
>   CC      drivers/pci/probe.o
>   CC      drivers/pci/host-bridge.o
>   CC      drivers/pci/remove.o
>   CC      drivers/pci/pci.o
>   CC      drivers/pci/pci-driver.o
>   CC      drivers/pci/search.o
>   CC      drivers/pci/pci-sysfs.o
>   CC      drivers/pci/rom.o
>   CC      drivers/pci/setup-res.o
>   CC      drivers/pci/irq.o
>   CC      drivers/pci/vpd.o
>   CC      drivers/pci/setup-bus.o
>   CC      drivers/pci/vc.o
>   CC      drivers/pci/mmap.o
>   CC      drivers/pci/setup-irq.o
>   CC      drivers/pci/proc.o
>   CC      drivers/pci/slot.o
>   CC      drivers/pci/quirks.o
> drivers/pci/quirks.c: In function ‘quirk_synopsys_haps’:
> drivers/pci/quirks.c:631:7: error: ‘PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3’
> undeclared (first use in this function); did you mean
> ‘PCI_DEVICE_ID_ESS_MAESTRO3’?
>   case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
>        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>        PCI_DEVICE_ID_ESS_MAESTRO3
> drivers/pci/quirks.c:631:7: note: each undeclared identifier is
> reported only once for each function it appears in
> drivers/pci/quirks.c:632:7: error:
> ‘PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI’ undeclared (first use in this
> function); did you mean ‘PCI_DEVICE_ID_SUN_CASSINI’?
>   case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
>        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>        PCI_DEVICE_ID_SUN_CASSINI
> drivers/pci/quirks.c:633:7: error: ‘PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31’
> undeclared (first use in this function); did you mean
> ‘PCI_DEVICE_ID_SUN_CASSINI’?
>   case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
>        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>        PCI_DEVICE_ID_SUN_CASSINI
> drivers/pci/quirks.c: In function ‘quirk_disable_aspm_l0s’:
> drivers/pci/quirks.c:2229:2: error: implicit declaration of function
> ‘pci_disable_link_state’; did you mean ‘pci_restore_iov_state’?
> [-Werror=implicit-function-declaration]
>   pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
>   ^~~~~~~~~~~~~~~~~~~~~~
>   pci_restore_iov_state
> drivers/pci/quirks.c:2229:30: error: ‘PCIE_LINK_STATE_L0S’ undeclared
> (first use in this function); did you mean ‘PCIE_LNK_WIDTH_RESRV’?
>   pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
>                               ^~~~~~~~~~~~~~~~~~~
>                               PCIE_LNK_WIDTH_RESRV
> drivers/pci/quirks.c: At top level:
> drivers/pci/quirks.c:4612:4: error: ‘PCI_VENDOR_ID_HXT’ undeclared
> here (not in a function); did you mean ‘PCI_VENDOR_ID_ATT’?
>   { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
>     ^~~~~~~~~~~~~~~~~
>     PCI_VENDOR_ID_ATT
> drivers/pci/quirks.c:4633:4: error:
> ‘PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS’ undeclared here (not in a
> function); did you mean ‘PCI_VENDOR_ID_AMAZON’?
>   { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
>     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>     PCI_VENDOR_ID_AMAZON
> drivers/pci/quirks.c: In function ‘quirk_nvidia_hda’:
> drivers/pci/quirks.c:5096:20: error:
> ‘PCI_DEVICE_ID_NVIDIA_GEFORCE_320M’ undeclared (first use in this
> function); did you mean ‘PCI_DEVICE_ID_NVIDIA_GEFORCE_6200’?
>   if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
>                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>                     PCI_DEVICE_ID_NVIDIA_GEFORCE_6200
> drivers/pci/quirks.c:5096:18: warning: comparison between pointer and
> integer
>   if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
>                   ^
> cc1: some warnings being treated as errors
> make[5]: *** [scripts/Makefile.build:304: drivers/pci/quirks.o] Error 1
> make[4]: *** [scripts/Makefile.build:544: drivers/pci] Error 2
> make[3]: *** [Makefile:1046: drivers] Error 2
> make[2]: *** [debian/rules:4: build] Error 2
> dpkg-buildpackage: error: debian/rules build subprocess returned exit status
> 2
> make[1]: *** [scripts/package/Makefile:75: deb-pkg] Error 2
> make: *** [Makefile:1359: deb-pkg] Error 2
> root@CF-29:/home/michael/kernel/linux-4.19.80#
>
> I will now try a compile of 5.4-rc1
> Cheers.
> Michael.
>
>
> On 25/10/2019, Dominik Brodowski <linux@dominikbrodowski.net> wrote:
>> The patch doesn't seem to have been applied correctly (using the patch(1)
>> utility). Attached is the file how it should look like.
>>
>> 	Dominik
>>
>> On Fri, Oct 25, 2019 at 01:38:46PM +1100, Michael . wrote:
>>> Here's the resulting output of the failed compilation of 5.4rc1 with
>>> the patch applied to quirks.c:
>>>  CC      drivers/pci/quirks.o
>>> drivers/pci/quirks.c:3039:1: error: expected identifier or ‘(’ before
>>> ‘-’
>>> token
>>>  3039 | -static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
>>>       | ^
>>> drivers/pci/quirks.c:3068:1: error: expected identifier or ‘(’ before
>>> ‘-’
>>> token
>>
>>
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Bjorn Helgaas]

[+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
thread, [2] for problem report and the patch Michael tested]

On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
> Bjorn and Dominik.
> I am happy to let you know the patch did the trick, it compiled well
> on 5.4-rc4 and my friends in the CC list have tested the modified
> kernel and confirmed that both slots are now working as they should.
> As a group of dedicated Toughbook users and Linux users please accept
> our thanks your efforts and assistance is greatly appreciated.
> 
> Now that we know this patch works what kernel do you think it will be
> released in? Will it make 5.4 or will it be put into 5.5 development
> for further testing?

That patch was not intended to be a fix; it was just to test my guess
that the quirk might be related.

Removing the quirk solved the problem *you're* seeing, but the quirk
was added in the first place to solve some other problem, and if we
simply remove the quirk, we may reintroduce the original problem.

So we have to look at the history and figure out some way to solve
both problems.  I cc'd some people who might have insight.  Here are
some commits that look relevant:

  5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
  03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")


[1] https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
[2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Bjorn Helgaas]

On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
> [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
> thread, [2] for problem report and the patch Michael tested]
> 
> On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
> > Bjorn and Dominik.
> > I am happy to let you know the patch did the trick, it compiled well
> > on 5.4-rc4 and my friends in the CC list have tested the modified
> > kernel and confirmed that both slots are now working as they should.
> > As a group of dedicated Toughbook users and Linux users please accept
> > our thanks your efforts and assistance is greatly appreciated.
> > 
> > Now that we know this patch works what kernel do you think it will be
> > released in? Will it make 5.4 or will it be put into 5.5 development
> > for further testing?
> 
> That patch was not intended to be a fix; it was just to test my guess
> that the quirk might be related.
> 
> Removing the quirk solved the problem *you're* seeing, but the quirk
> was added in the first place to solve some other problem, and if we
> simply remove the quirk, we may reintroduce the original problem.
> 
> So we have to look at the history and figure out some way to solve
> both problems.  I cc'd some people who might have insight.  Here are
> some commits that look relevant:
> 
>   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
>   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
> 
> 
> [1] https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
> [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/

I guess this problem is still unfixed?  I hate the fact that we broke
something that used to work.

Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
we skip it for Toughbooks?  Or maybe we limit the quirk to the
machines where it was originally needed?

Bjorn

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Hi Bjorn, yes this is still unfixed.
I'm sorry that I haven't been able to pursue this but the weather in
Australia has been horrendous since October last year. Your proposals
sound good but are way beyond my knowledge and skill level to
implement. I, and my friends, are happy to help in any way we can.
Cheers.
Michael.

P.S. I apologise for the double reply

On 23/02/2020, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
>> [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
>> thread, [2] for problem report and the patch Michael tested]
>>
>> On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
>> > Bjorn and Dominik.
>> > I am happy to let you know the patch did the trick, it compiled well
>> > on 5.4-rc4 and my friends in the CC list have tested the modified
>> > kernel and confirmed that both slots are now working as they should.
>> > As a group of dedicated Toughbook users and Linux users please accept
>> > our thanks your efforts and assistance is greatly appreciated.
>> >
>> > Now that we know this patch works what kernel do you think it will be
>> > released in? Will it make 5.4 or will it be put into 5.5 development
>> > for further testing?
>>
>> That patch was not intended to be a fix; it was just to test my guess
>> that the quirk might be related.
>>
>> Removing the quirk solved the problem *you're* seeing, but the quirk
>> was added in the first place to solve some other problem, and if we
>> simply remove the quirk, we may reintroduce the original problem.
>>
>> So we have to look at the history and figure out some way to solve
>> both problems.  I cc'd some people who might have insight.  Here are
>> some commits that look relevant:
>>
>>   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
>>   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
>>
>>
>> [1]
>> https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
>> [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
>
> I guess this problem is still unfixed?  I hate the fact that we broke
> something that used to work.
>
> Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
> we skip it for Toughbooks?  Or maybe we limit the quirk to the
> machines where it was originally needed?
>
> Bjorn
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Ulf Hansson]

On Sat, 22 Feb 2020 at 17:56, Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
> > [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
> > thread, [2] for problem report and the patch Michael tested]
> >
> > On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
> > > Bjorn and Dominik.
> > > I am happy to let you know the patch did the trick, it compiled well
> > > on 5.4-rc4 and my friends in the CC list have tested the modified
> > > kernel and confirmed that both slots are now working as they should.
> > > As a group of dedicated Toughbook users and Linux users please accept
> > > our thanks your efforts and assistance is greatly appreciated.
> > >
> > > Now that we know this patch works what kernel do you think it will be
> > > released in? Will it make 5.4 or will it be put into 5.5 development
> > > for further testing?
> >
> > That patch was not intended to be a fix; it was just to test my guess
> > that the quirk might be related.
> >
> > Removing the quirk solved the problem *you're* seeing, but the quirk
> > was added in the first place to solve some other problem, and if we
> > simply remove the quirk, we may reintroduce the original problem.
> >
> > So we have to look at the history and figure out some way to solve
> > both problems.  I cc'd some people who might have insight.  Here are
> > some commits that look relevant:
> >
> >   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
> >   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
> >
> >
> > [1] https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
> > [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
>
> I guess this problem is still unfixed?  I hate the fact that we broke
> something that used to work.
>
> Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
> we skip it for Toughbooks?  Or maybe we limit the quirk to the
> machines where it was originally needed?

Both options seems reasonable to me. Do you have time to put together a patch?

Kind regards
Uffe

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Bjorn Helgaas]

On Tue, Feb 25, 2020 at 04:03:32PM +0100, Ulf Hansson wrote:
> On Sat, 22 Feb 2020 at 17:56, Bjorn Helgaas <helgaas@kernel.org> wrote:
> >
> > On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
> > > [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
> > > thread, [2] for problem report and the patch Michael tested]
> > >
> > > On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
> > > > Bjorn and Dominik.
> > > > I am happy to let you know the patch did the trick, it compiled well
> > > > on 5.4-rc4 and my friends in the CC list have tested the modified
> > > > kernel and confirmed that both slots are now working as they should.
> > > > As a group of dedicated Toughbook users and Linux users please accept
> > > > our thanks your efforts and assistance is greatly appreciated.
> > > >
> > > > Now that we know this patch works what kernel do you think it will be
> > > > released in? Will it make 5.4 or will it be put into 5.5 development
> > > > for further testing?
> > >
> > > That patch was not intended to be a fix; it was just to test my guess
> > > that the quirk might be related.
> > >
> > > Removing the quirk solved the problem *you're* seeing, but the quirk
> > > was added in the first place to solve some other problem, and if we
> > > simply remove the quirk, we may reintroduce the original problem.
> > >
> > > So we have to look at the history and figure out some way to solve
> > > both problems.  I cc'd some people who might have insight.  Here are
> > > some commits that look relevant:
> > >
> > >   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
> > >   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
> > >
> > >
> > > [1] https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
> > > [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
> >
> > I guess this problem is still unfixed?  I hate the fact that we broke
> > something that used to work.
> >
> > Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
> > we skip it for Toughbooks?  Or maybe we limit the quirk to the
> > machines where it was originally needed?
> 
> Both options seems reasonable to me. Do you have time to put
> together a patch?

I don't really have time, and I'm not sure which way is best.  In
general I like to avoid quirks, so I would lean toward applying the
quirk only on the machines that we know need it.  But I'm not sure how
to identify those.

Bjorn

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[bluerocksaddles]

Bjorn,

If you folks need a test unit or five, let me know. I can donate any 
Mark CF-29 to the project. (MK 2 or 3 will duplicate the "problem".) 
They are non-pae 386.

Jeff

On 2020-02-25 07:03, Ulf Hansson wrote:
> On Sat, 22 Feb 2020 at 17:56, Bjorn Helgaas <helgaas@kernel.org> wrote:
>> 
>> On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
>> > [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
>> > thread, [2] for problem report and the patch Michael tested]
>> >
>> > On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
>> > > Bjorn and Dominik.
>> > > I am happy to let you know the patch did the trick, it compiled well
>> > > on 5.4-rc4 and my friends in the CC list have tested the modified
>> > > kernel and confirmed that both slots are now working as they should.
>> > > As a group of dedicated Toughbook users and Linux users please accept
>> > > our thanks your efforts and assistance is greatly appreciated.
>> > >
>> > > Now that we know this patch works what kernel do you think it will be
>> > > released in? Will it make 5.4 or will it be put into 5.5 development
>> > > for further testing?
>> >
>> > That patch was not intended to be a fix; it was just to test my guess
>> > that the quirk might be related.
>> >
>> > Removing the quirk solved the problem *you're* seeing, but the quirk
>> > was added in the first place to solve some other problem, and if we
>> > simply remove the quirk, we may reintroduce the original problem.
>> >
>> > So we have to look at the history and figure out some way to solve
>> > both problems.  I cc'd some people who might have insight.  Here are
>> > some commits that look relevant:
>> >
>> >   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
>> >   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
>> >
>> >
>> > [1] https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
>> > [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
>> 
>> I guess this problem is still unfixed?  I hate the fact that we broke
>> something that used to work.
>> 
>> Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
>> we skip it for Toughbooks?  Or maybe we limit the quirk to the
>> machines where it was originally needed?
> 
> Both options seems reasonable to me. Do you have time to put together a 
> patch?
> 
> Kind regards
> Uffe

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Arvind Sankar]

On Tue, Feb 25, 2020 at 04:03:32PM +0100, Ulf Hansson wrote:
> On Sat, 22 Feb 2020 at 17:56, Bjorn Helgaas <helgaas@kernel.org> wrote:
> >
> > On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
> > > [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
> > > thread, [2] for problem report and the patch Michael tested]
> > >
> > > On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
> > > > Bjorn and Dominik.
> > > > I am happy to let you know the patch did the trick, it compiled well
> > > > on 5.4-rc4 and my friends in the CC list have tested the modified
> > > > kernel and confirmed that both slots are now working as they should.
> > > > As a group of dedicated Toughbook users and Linux users please accept
> > > > our thanks your efforts and assistance is greatly appreciated.
> > > >
> > > > Now that we know this patch works what kernel do you think it will be
> > > > released in? Will it make 5.4 or will it be put into 5.5 development
> > > > for further testing?
> > >
> > > That patch was not intended to be a fix; it was just to test my guess
> > > that the quirk might be related.
> > >
> > > Removing the quirk solved the problem *you're* seeing, but the quirk
> > > was added in the first place to solve some other problem, and if we
> > > simply remove the quirk, we may reintroduce the original problem.
> > >
> > > So we have to look at the history and figure out some way to solve
> > > both problems.  I cc'd some people who might have insight.  Here are
> > > some commits that look relevant:
> > >
> > >   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
> > >   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
> > >
> > >
> > > [1] https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
> > > [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
> >
> > I guess this problem is still unfixed?  I hate the fact that we broke
> > something that used to work.
> >
> > Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
> > we skip it for Toughbooks?  Or maybe we limit the quirk to the
> > machines where it was originally needed?
> 
> Both options seems reasonable to me. Do you have time to put together a patch?
> 
> Kind regards
> Uffe

The quirk is controlled by MMC_RICOH_MMC configuration option. At least
as a short-term fix a bit better than patching the kernel, building one
with that config option disabled should have the same effect.

From the commit messages, the quirk was required to support MMC (as
opposed to SD) cards in the SD slot. I would assume this will be an
issue with the chip in any machine as the commit indicates that the
hardware in the chip detects MMC cards and doesn't expose them through
the SDHCI function.

It looks like the quirk was only enabled by default in 2015, at least
upstream [1], though in Debian it was enabled in May 2010 going by their
git repo, maybe in 2.6.32-16.

[1] commit ba2f73250e4a ("mmc: Enable Ricoh MMC quirk by default")

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Through our own testing it hasn't worked on any of the regular Linux
releases (both Deb and RPM varieties, and I think someone tested Arch
or Slackware as well) after 2.6.32 .

On 26/02/2020, Arvind Sankar <nivedita@alum.mit.edu> wrote:
> On Tue, Feb 25, 2020 at 04:03:32PM +0100, Ulf Hansson wrote:
>> On Sat, 22 Feb 2020 at 17:56, Bjorn Helgaas <helgaas@kernel.org> wrote:
>> >
>> > On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
>> > > [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
>> > > thread, [2] for problem report and the patch Michael tested]
>> > >
>> > > On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
>> > > > Bjorn and Dominik.
>> > > > I am happy to let you know the patch did the trick, it compiled
>> > > > well
>> > > > on 5.4-rc4 and my friends in the CC list have tested the modified
>> > > > kernel and confirmed that both slots are now working as they
>> > > > should.
>> > > > As a group of dedicated Toughbook users and Linux users please
>> > > > accept
>> > > > our thanks your efforts and assistance is greatly appreciated.
>> > > >
>> > > > Now that we know this patch works what kernel do you think it will
>> > > > be
>> > > > released in? Will it make 5.4 or will it be put into 5.5
>> > > > development
>> > > > for further testing?
>> > >
>> > > That patch was not intended to be a fix; it was just to test my guess
>> > > that the quirk might be related.
>> > >
>> > > Removing the quirk solved the problem *you're* seeing, but the quirk
>> > > was added in the first place to solve some other problem, and if we
>> > > simply remove the quirk, we may reintroduce the original problem.
>> > >
>> > > So we have to look at the history and figure out some way to solve
>> > > both problems.  I cc'd some people who might have insight.  Here are
>> > > some commits that look relevant:
>> > >
>> > >   5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
>> > >   03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
>> > >
>> > >
>> > > [1]
>> > > https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
>> > > [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
>> >
>> > I guess this problem is still unfixed?  I hate the fact that we broke
>> > something that used to work.
>> >
>> > Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
>> > we skip it for Toughbooks?  Or maybe we limit the quirk to the
>> > machines where it was originally needed?
>>
>> Both options seems reasonable to me. Do you have time to put together a
>> patch?
>>
>> Kind regards
>> Uffe
>
> The quirk is controlled by MMC_RICOH_MMC configuration option. At least
> as a short-term fix a bit better than patching the kernel, building one
> with that config option disabled should have the same effect.
>
> From the commit messages, the quirk was required to support MMC (as
> opposed to SD) cards in the SD slot. I would assume this will be an
> issue with the chip in any machine as the commit indicates that the
> hardware in the chip detects MMC cards and doesn't expose them through
> the SDHCI function.
>
> It looks like the quirk was only enabled by default in 2015, at least
> upstream [1], though in Debian it was enabled in May 2010 going by their
> git repo, maybe in 2.6.32-16.
>
> [1] commit ba2f73250e4a ("mmc: Enable Ricoh MMC quirk by default")
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Trevor Jacobs]

That's correct, I tested a bunch of the old distros including slackware, 
and 2.6.32 is where the problem began.

Also, the Panasonic Toughbook CF-29s effected that we tested are the 
later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just fine 
because it has different hardware supporting the PCMCIA slots. I have 
not tested a MK3 but suspect it would work ok as it also uses the older 
hardware.

Thanks for your help guys!
Trevor

On 2/25/20 7:50 PM, Michael . wrote:
> Through our own testing it hasn't worked on any of the regular Linux
> releases (both Deb and RPM varieties, and I think someone tested Arch
> or Slackware as well) after 2.6.32 .
>
> On 26/02/2020, Arvind Sankar <nivedita@alum.mit.edu> wrote:
>> On Tue, Feb 25, 2020 at 04:03:32PM +0100, Ulf Hansson wrote:
>>> On Sat, 22 Feb 2020 at 17:56, Bjorn Helgaas <helgaas@kernel.org> wrote:
>>>> On Tue, Oct 29, 2019 at 12:02:50PM -0500, Bjorn Helgaas wrote:
>>>>> [+cc Ulf, Philip, Pierre, Maxim, linux-mmc; see [1] for beginning of
>>>>> thread, [2] for problem report and the patch Michael tested]
>>>>>
>>>>> On Tue, Oct 29, 2019 at 07:58:27PM +1100, Michael . wrote:
>>>>>> Bjorn and Dominik.
>>>>>> I am happy to let you know the patch did the trick, it compiled
>>>>>> well
>>>>>> on 5.4-rc4 and my friends in the CC list have tested the modified
>>>>>> kernel and confirmed that both slots are now working as they
>>>>>> should.
>>>>>> As a group of dedicated Toughbook users and Linux users please
>>>>>> accept
>>>>>> our thanks your efforts and assistance is greatly appreciated.
>>>>>>
>>>>>> Now that we know this patch works what kernel do you think it will
>>>>>> be
>>>>>> released in? Will it make 5.4 or will it be put into 5.5
>>>>>> development
>>>>>> for further testing?
>>>>> That patch was not intended to be a fix; it was just to test my guess
>>>>> that the quirk might be related.
>>>>>
>>>>> Removing the quirk solved the problem *you're* seeing, but the quirk
>>>>> was added in the first place to solve some other problem, and if we
>>>>> simply remove the quirk, we may reintroduce the original problem.
>>>>>
>>>>> So we have to look at the history and figure out some way to solve
>>>>> both problems.  I cc'd some people who might have insight.  Here are
>>>>> some commits that look relevant:
>>>>>
>>>>>    5ae70296c85f ("mmc: Disabler for Ricoh MMC controller")
>>>>>    03cd8f7ebe0c ("ricoh_mmc: port from driver to pci quirk")
>>>>>
>>>>>
>>>>> [1]
>>>>> https://lore.kernel.org/r/CAFjuqNi+knSb9WVQOahCVFyxsiqoGgwoM7Z1aqDBebNzp_-jYw@mail.gmail.com/
>>>>> [2] https://lore.kernel.org/r/20191021160952.GA229204@google.com/
>>>> I guess this problem is still unfixed?  I hate the fact that we broke
>>>> something that used to work.
>>>>
>>>> Maybe we need some sort of DMI check in ricoh_mmc_fixup_rl5c476() so
>>>> we skip it for Toughbooks?  Or maybe we limit the quirk to the
>>>> machines where it was originally needed?
>>> Both options seems reasonable to me. Do you have time to put together a
>>> patch?
>>>
>>> Kind regards
>>> Uffe
>> The quirk is controlled by MMC_RICOH_MMC configuration option. At least
>> as a short-term fix a bit better than patching the kernel, building one
>> with that config option disabled should have the same effect.
>>
>>  From the commit messages, the quirk was required to support MMC (as
>> opposed to SD) cards in the SD slot. I would assume this will be an
>> issue with the chip in any machine as the commit indicates that the
>> hardware in the chip detects MMC cards and doesn't expose them through
>> the SDHCI function.
>>
>> It looks like the quirk was only enabled by default in 2015, at least
>> upstream [1], though in Debian it was enabled in May 2010 going by their
>> git repo, maybe in 2.6.32-16.
>>
>> [1] commit ba2f73250e4a ("mmc: Enable Ricoh MMC quirk by default")
>>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Arvind Sankar]

On Tue, Feb 25, 2020 at 09:12:48PM -0600, Trevor Jacobs wrote:
> That's correct, I tested a bunch of the old distros including slackware, 
> and 2.6.32 is where the problem began.
> 
> Also, the Panasonic Toughbook CF-29s effected that we tested are the 
> later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just fine 
> because it has different hardware supporting the PCMCIA slots. I have 
> not tested a MK3 but suspect it would work ok as it also uses the older 
> hardware.
> 
> Thanks for your help guys!
> Trevor
> 

Right, the distros probably all enabled MMC_RICOH_MMC earlier than
upstream. Can you test a custom kernel based off your distro kernel but
just disabling that config option? That's probably the easiest fix
currently, even though not ideal. Perhaps there should be a command line
option to disable specific pci quirks to make this easier.

An ideal fix is I feel hard, given this quirk is based on undocumented
config registers -- it worked on Dell machines (that's where the
original authors seem to have gotten their info from), perhaps they had
only one Cardbus slot, but the code ends up disabling your second
Cardbus slot instead of disabling the MMC controller.

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Philip Langdale]

On Tue, 25 Feb 2020 23:51:05 -0500
Arvind Sankar <nivedita@alum.mit.edu> wrote:

> On Tue, Feb 25, 2020 at 09:12:48PM -0600, Trevor Jacobs wrote:
> > That's correct, I tested a bunch of the old distros including
> > slackware, and 2.6.32 is where the problem began.
> > 
> > Also, the Panasonic Toughbook CF-29s effected that we tested are
> > the later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just
> > fine because it has different hardware supporting the PCMCIA slots.
> > I have not tested a MK3 but suspect it would work ok as it also
> > uses the older hardware.
> > 
> > Thanks for your help guys!
> > Trevor
> > 
> 
> Right, the distros probably all enabled MMC_RICOH_MMC earlier than
> upstream. Can you test a custom kernel based off your distro kernel
> but just disabling that config option? That's probably the easiest fix
> currently, even though not ideal. Perhaps there should be a command
> line option to disable specific pci quirks to make this easier.
> 
> An ideal fix is I feel hard, given this quirk is based on undocumented
> config registers -- it worked on Dell machines (that's where the
> original authors seem to have gotten their info from), perhaps they
> had only one Cardbus slot, but the code ends up disabling your second
> Cardbus slot instead of disabling the MMC controller.

Keeping in mind that this was 12+ years ago, you can at least still
read the original discussion in the archives. My original Dell laptop
(XPS m1330) had no cardbus slots at all, and used the r5c832
controller. There was a subsequent change that I was not involved with
which added support for the rl5c476, which is the problematic device in
this thread.

As a hypothesis, based on the observed behaviour, the quirk (keeping in
mind that these are magic configuration register values that are not
documented) probably disabled function 1, regardless of what it is, and
the original example that motivated adding the rl5c476 quirk probably
had one cardbus slot and the card reader functions were all moved up
one, or something along those lines.

Truly making this smart would then involve having the code enumerate
the pci functions and identify the one that is the unwanted mmc
controller, based on function ID or class or whatever, and then
disabling that (assuming the magic can be reverse engineered: eg, the
current magic ORs the disable flag with 0x02 - chances are, that's the
index of the function: 0x01 would be the 0th function, 0x04 would be
the 2nd function, etc). Someone with access to real hardware could
easily experiment with changing that magic value and seeing if it
changes which function is disabled.

Good luck.

--phil

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

>Someone with access to real hardware could
>easily experiment with changing that magic value and seeing if it
>changes which function is disabled.

One of our members has offered to supply a machine to a dev that can
use it to test any theory.

It is nearly beyond the scope of the majority of us to do much more
than just testing. We appreciate all the effort the devs put in and
are willing to help in anyway we can but we aren't kernel devs.

I, personally, use Debian. Others use Debian based distros such as MX
and Mint. We have been able to test many different distros such as
those listed in other comments but don't have the skills or expertise
to do much more. It is our hope that this discussion and subsequent
effort may enable others who prefer distros other than Debian based
distros can use a CF-29 (and possibly earlier) Toughbook with the
distro of their choice without having to rebuild a kernel so they can
use hardware that worked back in 2010. To do this the fix needs to be
at the kernel dev level not a local enthusiast level because while I
can rebuild a Debian kernel I can't rebuild a Fedora or Arch or
Slackware kernel.

I did a search about this issue before I made initial contact late
last year and the issue was discovered on more than Toughbooks and
posted about on various sites not long after distros moved from
2.6.32. It seems back then people just got new machines that didn't
have a 2nd slot so the search for an answer stopped. Us Toughbook
users are a loyal group we use our machines because they are exactly
what we need and they take alot of "punishment" taht other machines
simply cannot handle. Our machines are used rather than recycled or
worse still just left to sit in waste management facilities in a
country that the western world dumps its rubbish in, we are Linux and
Toughbook enthusiasts and hope to be able to keep our machines running
for many years to come with all their native capabilities working as
they were designed to but using a modern Linux instead of Windows XP
or Windows 7. (that wasn't a pep talk, its just an explanation of why
we are passionate about this).

Let us know what you need us to do, we will let you know if we are
capable of it and give you any feedback you ask for. Over the weekend
I will try to rebuild a Debian kernel with the relevant option
disabled, provide it to my peers for testing and report back here what
the outcome is.

Thank you all for all your time and effort, it is truly appreciated.
Cheers.
Michael.

On 26/02/2020, Philip Langdale <philipl@overt.org> wrote:
> On Tue, 25 Feb 2020 23:51:05 -0500
> Arvind Sankar <nivedita@alum.mit.edu> wrote:
>
>> On Tue, Feb 25, 2020 at 09:12:48PM -0600, Trevor Jacobs wrote:
>> > That's correct, I tested a bunch of the old distros including
>> > slackware, and 2.6.32 is where the problem began.
>> >
>> > Also, the Panasonic Toughbook CF-29s effected that we tested are
>> > the later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just
>> > fine because it has different hardware supporting the PCMCIA slots.
>> > I have not tested a MK3 but suspect it would work ok as it also
>> > uses the older hardware.
>> >
>> > Thanks for your help guys!
>> > Trevor
>> >
>>
>> Right, the distros probably all enabled MMC_RICOH_MMC earlier than
>> upstream. Can you test a custom kernel based off your distro kernel
>> but just disabling that config option? That's probably the easiest fix
>> currently, even though not ideal. Perhaps there should be a command
>> line option to disable specific pci quirks to make this easier.
>>
>> An ideal fix is I feel hard, given this quirk is based on undocumented
>> config registers -- it worked on Dell machines (that's where the
>> original authors seem to have gotten their info from), perhaps they
>> had only one Cardbus slot, but the code ends up disabling your second
>> Cardbus slot instead of disabling the MMC controller.
>
> Keeping in mind that this was 12+ years ago, you can at least still
> read the original discussion in the archives. My original Dell laptop
> (XPS m1330) had no cardbus slots at all, and used the r5c832
> controller. There was a subsequent change that I was not involved with
> which added support for the rl5c476, which is the problematic device in
> this thread.
>
> As a hypothesis, based on the observed behaviour, the quirk (keeping in
> mind that these are magic configuration register values that are not
> documented) probably disabled function 1, regardless of what it is, and
> the original example that motivated adding the rl5c476 quirk probably
> had one cardbus slot and the card reader functions were all moved up
> one, or something along those lines.
>
> Truly making this smart would then involve having the code enumerate
> the pci functions and identify the one that is the unwanted mmc
> controller, based on function ID or class or whatever, and then
> disabling that (assuming the magic can be reverse engineered: eg, the
> current magic ORs the disable flag with 0x02 - chances are, that's the
> index of the function: 0x01 would be the 0th function, 0x04 would be
> the 2nd function, etc). Someone with access to real hardware could
> easily experiment with changing that magic value and seeing if it
> changes which function is disabled.
>
> Good luck.
>
> --phil
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[bluerocksaddles]

Somewhere in these messages is a clue....in that SD reader was involved.

MK 4 and 5 have SD whilst MK 1, 2 and three do not.



On 2020-02-25 22:10, Michael . wrote:
>> Someone with access to real hardware could
>> easily experiment with changing that magic value and seeing if it
>> changes which function is disabled.
> 
> One of our members has offered to supply a machine to a dev that can
> use it to test any theory.
> 
> It is nearly beyond the scope of the majority of us to do much more
> than just testing. We appreciate all the effort the devs put in and
> are willing to help in anyway we can but we aren't kernel devs.
> 
> I, personally, use Debian. Others use Debian based distros such as MX
> and Mint. We have been able to test many different distros such as
> those listed in other comments but don't have the skills or expertise
> to do much more. It is our hope that this discussion and subsequent
> effort may enable others who prefer distros other than Debian based
> distros can use a CF-29 (and possibly earlier) Toughbook with the
> distro of their choice without having to rebuild a kernel so they can
> use hardware that worked back in 2010. To do this the fix needs to be
> at the kernel dev level not a local enthusiast level because while I
> can rebuild a Debian kernel I can't rebuild a Fedora or Arch or
> Slackware kernel.
> 
> I did a search about this issue before I made initial contact late
> last year and the issue was discovered on more than Toughbooks and
> posted about on various sites not long after distros moved from
> 2.6.32. It seems back then people just got new machines that didn't
> have a 2nd slot so the search for an answer stopped. Us Toughbook
> users are a loyal group we use our machines because they are exactly
> what we need and they take alot of "punishment" taht other machines
> simply cannot handle. Our machines are used rather than recycled or
> worse still just left to sit in waste management facilities in a
> country that the western world dumps its rubbish in, we are Linux and
> Toughbook enthusiasts and hope to be able to keep our machines running
> for many years to come with all their native capabilities working as
> they were designed to but using a modern Linux instead of Windows XP
> or Windows 7. (that wasn't a pep talk, its just an explanation of why
> we are passionate about this).
> 
> Let us know what you need us to do, we will let you know if we are
> capable of it and give you any feedback you ask for. Over the weekend
> I will try to rebuild a Debian kernel with the relevant option
> disabled, provide it to my peers for testing and report back here what
> the outcome is.
> 
> Thank you all for all your time and effort, it is truly appreciated.
> Cheers.
> Michael.
> 
> On 26/02/2020, Philip Langdale <philipl@overt.org> wrote:
>> On Tue, 25 Feb 2020 23:51:05 -0500
>> Arvind Sankar <nivedita@alum.mit.edu> wrote:
>> 
>>> On Tue, Feb 25, 2020 at 09:12:48PM -0600, Trevor Jacobs wrote:
>>> > That's correct, I tested a bunch of the old distros including
>>> > slackware, and 2.6.32 is where the problem began.
>>> >
>>> > Also, the Panasonic Toughbook CF-29s effected that we tested are
>>> > the later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just
>>> > fine because it has different hardware supporting the PCMCIA slots.
>>> > I have not tested a MK3 but suspect it would work ok as it also
>>> > uses the older hardware.
>>> >
>>> > Thanks for your help guys!
>>> > Trevor
>>> >
>>> 
>>> Right, the distros probably all enabled MMC_RICOH_MMC earlier than
>>> upstream. Can you test a custom kernel based off your distro kernel
>>> but just disabling that config option? That's probably the easiest 
>>> fix
>>> currently, even though not ideal. Perhaps there should be a command
>>> line option to disable specific pci quirks to make this easier.
>>> 
>>> An ideal fix is I feel hard, given this quirk is based on 
>>> undocumented
>>> config registers -- it worked on Dell machines (that's where the
>>> original authors seem to have gotten their info from), perhaps they
>>> had only one Cardbus slot, but the code ends up disabling your second
>>> Cardbus slot instead of disabling the MMC controller.
>> 
>> Keeping in mind that this was 12+ years ago, you can at least still
>> read the original discussion in the archives. My original Dell laptop
>> (XPS m1330) had no cardbus slots at all, and used the r5c832
>> controller. There was a subsequent change that I was not involved with
>> which added support for the rl5c476, which is the problematic device 
>> in
>> this thread.
>> 
>> As a hypothesis, based on the observed behaviour, the quirk (keeping 
>> in
>> mind that these are magic configuration register values that are not
>> documented) probably disabled function 1, regardless of what it is, 
>> and
>> the original example that motivated adding the rl5c476 quirk probably
>> had one cardbus slot and the card reader functions were all moved up
>> one, or something along those lines.
>> 
>> Truly making this smart would then involve having the code enumerate
>> the pci functions and identify the one that is the unwanted mmc
>> controller, based on function ID or class or whatever, and then
>> disabling that (assuming the magic can be reverse engineered: eg, the
>> current magic ORs the disable flag with 0x02 - chances are, that's the
>> index of the function: 0x01 would be the 0th function, 0x04 would be
>> the 2nd function, etc). Someone with access to real hardware could
>> easily experiment with changing that magic value and seeing if it
>> changes which function is disabled.
>> 
>> Good luck.
>> 
>> --phil
>> 

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

I have just compiled and uploaded a kernel to test for this issue,
members of the Toughbook community have been provided with the link,
though a forum discussion, to download the kernel and test it.
Hopefully we will get positive results and can confirm the
MMC_RICOH_MMC flag is the culprit.
Regards.
Stay safe.
Michael.

On 27/02/2020, bluerocksaddles@willitsonline.com
<bluerocksaddles@willitsonline.com> wrote:
> Somewhere in these messages is a clue....in that SD reader was involved.
>
> MK 4 and 5 have SD whilst MK 1, 2 and three do not.
>
>
>
> On 2020-02-25 22:10, Michael . wrote:
>>> Someone with access to real hardware could
>>> easily experiment with changing that magic value and seeing if it
>>> changes which function is disabled.
>>
>> One of our members has offered to supply a machine to a dev that can
>> use it to test any theory.
>>
>> It is nearly beyond the scope of the majority of us to do much more
>> than just testing. We appreciate all the effort the devs put in and
>> are willing to help in anyway we can but we aren't kernel devs.
>>
>> I, personally, use Debian. Others use Debian based distros such as MX
>> and Mint. We have been able to test many different distros such as
>> those listed in other comments but don't have the skills or expertise
>> to do much more. It is our hope that this discussion and subsequent
>> effort may enable others who prefer distros other than Debian based
>> distros can use a CF-29 (and possibly earlier) Toughbook with the
>> distro of their choice without having to rebuild a kernel so they can
>> use hardware that worked back in 2010. To do this the fix needs to be
>> at the kernel dev level not a local enthusiast level because while I
>> can rebuild a Debian kernel I can't rebuild a Fedora or Arch or
>> Slackware kernel.
>>
>> I did a search about this issue before I made initial contact late
>> last year and the issue was discovered on more than Toughbooks and
>> posted about on various sites not long after distros moved from
>> 2.6.32. It seems back then people just got new machines that didn't
>> have a 2nd slot so the search for an answer stopped. Us Toughbook
>> users are a loyal group we use our machines because they are exactly
>> what we need and they take alot of "punishment" taht other machines
>> simply cannot handle. Our machines are used rather than recycled or
>> worse still just left to sit in waste management facilities in a
>> country that the western world dumps its rubbish in, we are Linux and
>> Toughbook enthusiasts and hope to be able to keep our machines running
>> for many years to come with all their native capabilities working as
>> they were designed to but using a modern Linux instead of Windows XP
>> or Windows 7. (that wasn't a pep talk, its just an explanation of why
>> we are passionate about this).
>>
>> Let us know what you need us to do, we will let you know if we are
>> capable of it and give you any feedback you ask for. Over the weekend
>> I will try to rebuild a Debian kernel with the relevant option
>> disabled, provide it to my peers for testing and report back here what
>> the outcome is.
>>
>> Thank you all for all your time and effort, it is truly appreciated.
>> Cheers.
>> Michael.
>>
>> On 26/02/2020, Philip Langdale <philipl@overt.org> wrote:
>>> On Tue, 25 Feb 2020 23:51:05 -0500
>>> Arvind Sankar <nivedita@alum.mit.edu> wrote:
>>>
>>>> On Tue, Feb 25, 2020 at 09:12:48PM -0600, Trevor Jacobs wrote:
>>>> > That's correct, I tested a bunch of the old distros including
>>>> > slackware, and 2.6.32 is where the problem began.
>>>> >
>>>> > Also, the Panasonic Toughbook CF-29s effected that we tested are
>>>> > the later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just
>>>> > fine because it has different hardware supporting the PCMCIA slots.
>>>> > I have not tested a MK3 but suspect it would work ok as it also
>>>> > uses the older hardware.
>>>> >
>>>> > Thanks for your help guys!
>>>> > Trevor
>>>> >
>>>>
>>>> Right, the distros probably all enabled MMC_RICOH_MMC earlier than
>>>> upstream. Can you test a custom kernel based off your distro kernel
>>>> but just disabling that config option? That's probably the easiest
>>>> fix
>>>> currently, even though not ideal. Perhaps there should be a command
>>>> line option to disable specific pci quirks to make this easier.
>>>>
>>>> An ideal fix is I feel hard, given this quirk is based on
>>>> undocumented
>>>> config registers -- it worked on Dell machines (that's where the
>>>> original authors seem to have gotten their info from), perhaps they
>>>> had only one Cardbus slot, but the code ends up disabling your second
>>>> Cardbus slot instead of disabling the MMC controller.
>>>
>>> Keeping in mind that this was 12+ years ago, you can at least still
>>> read the original discussion in the archives. My original Dell laptop
>>> (XPS m1330) had no cardbus slots at all, and used the r5c832
>>> controller. There was a subsequent change that I was not involved with
>>> which added support for the rl5c476, which is the problematic device
>>> in
>>> this thread.
>>>
>>> As a hypothesis, based on the observed behaviour, the quirk (keeping
>>> in
>>> mind that these are magic configuration register values that are not
>>> documented) probably disabled function 1, regardless of what it is,
>>> and
>>> the original example that motivated adding the rl5c476 quirk probably
>>> had one cardbus slot and the card reader functions were all moved up
>>> one, or something along those lines.
>>>
>>> Truly making this smart would then involve having the code enumerate
>>> the pci functions and identify the one that is the unwanted mmc
>>> controller, based on function ID or class or whatever, and then
>>> disabling that (assuming the magic can be reverse engineered: eg, the
>>> current magic ORs the disable flag with 0x02 - chances are, that's the
>>> index of the function: 0x01 would be the 0th function, 0x04 would be
>>> the 2nd function, etc). Someone with access to real hardware could
>>> easily experiment with changing that magic value and seeing if it
>>> changes which function is disabled.
>>>
>>> Good luck.
>>>
>>> --phil
>>>
>

Re: PCI device function not being enumerated [Was: PCMCIA not working on Panasonic Toughbook CF-29]

[Michael .]

Have just had confirmation that the mmc_ricoh_mmc change works and
both PCMCIA slots now work as intended on Panasonic Toughbook CF-29 Mk
4 and 5.

Thank you to all who have made suggestions for this, your dedication
to Linux is amazing and your help with this is appreciated.

Stay safe.
Michael.

On 28/07/2020, Michael . <keltoiboy@gmail.com> wrote:
> I have just compiled and uploaded a kernel to test for this issue,
> members of the Toughbook community have been provided with the link,
> though a forum discussion, to download the kernel and test it.
> Hopefully we will get positive results and can confirm the
> MMC_RICOH_MMC flag is the culprit.
> Regards.
> Stay safe.
> Michael.
>
> On 27/02/2020, bluerocksaddles@willitsonline.com
> <bluerocksaddles@willitsonline.com> wrote:
>> Somewhere in these messages is a clue....in that SD reader was involved.
>>
>> MK 4 and 5 have SD whilst MK 1, 2 and three do not.
>>
>>
>>
>> On 2020-02-25 22:10, Michael . wrote:
>>>> Someone with access to real hardware could
>>>> easily experiment with changing that magic value and seeing if it
>>>> changes which function is disabled.
>>>
>>> One of our members has offered to supply a machine to a dev that can
>>> use it to test any theory.
>>>
>>> It is nearly beyond the scope of the majority of us to do much more
>>> than just testing. We appreciate all the effort the devs put in and
>>> are willing to help in anyway we can but we aren't kernel devs.
>>>
>>> I, personally, use Debian. Others use Debian based distros such as MX
>>> and Mint. We have been able to test many different distros such as
>>> those listed in other comments but don't have the skills or expertise
>>> to do much more. It is our hope that this discussion and subsequent
>>> effort may enable others who prefer distros other than Debian based
>>> distros can use a CF-29 (and possibly earlier) Toughbook with the
>>> distro of their choice without having to rebuild a kernel so they can
>>> use hardware that worked back in 2010. To do this the fix needs to be
>>> at the kernel dev level not a local enthusiast level because while I
>>> can rebuild a Debian kernel I can't rebuild a Fedora or Arch or
>>> Slackware kernel.
>>>
>>> I did a search about this issue before I made initial contact late
>>> last year and the issue was discovered on more than Toughbooks and
>>> posted about on various sites not long after distros moved from
>>> 2.6.32. It seems back then people just got new machines that didn't
>>> have a 2nd slot so the search for an answer stopped. Us Toughbook
>>> users are a loyal group we use our machines because they are exactly
>>> what we need and they take alot of "punishment" taht other machines
>>> simply cannot handle. Our machines are used rather than recycled or
>>> worse still just left to sit in waste management facilities in a
>>> country that the western world dumps its rubbish in, we are Linux and
>>> Toughbook enthusiasts and hope to be able to keep our machines running
>>> for many years to come with all their native capabilities working as
>>> they were designed to but using a modern Linux instead of Windows XP
>>> or Windows 7. (that wasn't a pep talk, its just an explanation of why
>>> we are passionate about this).
>>>
>>> Let us know what you need us to do, we will let you know if we are
>>> capable of it and give you any feedback you ask for. Over the weekend
>>> I will try to rebuild a Debian kernel with the relevant option
>>> disabled, provide it to my peers for testing and report back here what
>>> the outcome is.
>>>
>>> Thank you all for all your time and effort, it is truly appreciated.
>>> Cheers.
>>> Michael.
>>>
>>> On 26/02/2020, Philip Langdale <philipl@overt.org> wrote:
>>>> On Tue, 25 Feb 2020 23:51:05 -0500
>>>> Arvind Sankar <nivedita@alum.mit.edu> wrote:
>>>>
>>>>> On Tue, Feb 25, 2020 at 09:12:48PM -0600, Trevor Jacobs wrote:
>>>>> > That's correct, I tested a bunch of the old distros including
>>>>> > slackware, and 2.6.32 is where the problem began.
>>>>> >
>>>>> > Also, the Panasonic Toughbook CF-29s effected that we tested are
>>>>> > the later marks, MK4 and MK5 for certain. The MK2 CF-29 worked just
>>>>> > fine because it has different hardware supporting the PCMCIA slots.
>>>>> > I have not tested a MK3 but suspect it would work ok as it also
>>>>> > uses the older hardware.
>>>>> >
>>>>> > Thanks for your help guys!
>>>>> > Trevor
>>>>> >
>>>>>
>>>>> Right, the distros probably all enabled MMC_RICOH_MMC earlier than
>>>>> upstream. Can you test a custom kernel based off your distro kernel
>>>>> but just disabling that config option? That's probably the easiest
>>>>> fix
>>>>> currently, even though not ideal. Perhaps there should be a command
>>>>> line option to disable specific pci quirks to make this easier.
>>>>>
>>>>> An ideal fix is I feel hard, given this quirk is based on
>>>>> undocumented
>>>>> config registers -- it worked on Dell machines (that's where the
>>>>> original authors seem to have gotten their info from), perhaps they
>>>>> had only one Cardbus slot, but the code ends up disabling your second
>>>>> Cardbus slot instead of disabling the MMC controller.
>>>>
>>>> Keeping in mind that this was 12+ years ago, you can at least still
>>>> read the original discussion in the archives. My original Dell laptop
>>>> (XPS m1330) had no cardbus slots at all, and used the r5c832
>>>> controller. There was a subsequent change that I was not involved with
>>>> which added support for the rl5c476, which is the problematic device
>>>> in
>>>> this thread.
>>>>
>>>> As a hypothesis, based on the observed behaviour, the quirk (keeping
>>>> in
>>>> mind that these are magic configuration register values that are not
>>>> documented) probably disabled function 1, regardless of what it is,
>>>> and
>>>> the original example that motivated adding the rl5c476 quirk probably
>>>> had one cardbus slot and the card reader functions were all moved up
>>>> one, or something along those lines.
>>>>
>>>> Truly making this smart would then involve having the code enumerate
>>>> the pci functions and identify the one that is the unwanted mmc
>>>> controller, based on function ID or class or whatever, and then
>>>> disabling that (assuming the magic can be reverse engineered: eg, the
>>>> current magic ORs the disable flag with 0x02 - chances are, that's the
>>>> index of the function: 0x01 would be the 0th function, 0x04 would be
>>>> the 2nd function, etc). Someone with access to real hardware could
>>>> easily experiment with changing that magic value and seeing if it
>>>> changes which function is disabled.
>>>>
>>>> Good luck.
>>>>
>>>> --phil
>>>>
>>
>

PCMCIA not working on Panasonic Toughbook CF-29

[Michael .]

[-- Attachment #1: Type: text/plain, Size: 3752 bytes --]

Due to filtering at the kernel email address it appears some emails
are being dropped by the kernel.org email address. I am sending this
for Trevor whose email bounced.

Hi Dominik,
Please see attached the outputs that you asked for in 2 files.
CF-29_MK5_2.6.32.txt is the requested outputs while running Antix
Linux M8.5 with Kernel 2.6.32. CF-29_MK5_4.9.160.txt is the requested
outputs running Antix Linux 17.4.1 with kernel 4.9.160.

Thank you in advance for your help!
Kind regards,Trevor Jacobs



-----Original Message-----
From: Dominik Brodowski <linux@dominikbrodowski.net>
To: Michael . <keltoiboy@gmail.com>
Cc: linux-kernel <linux-kernel@vger.kernel.org>; Morgan Klym
<moklym@gmail.com>; Trevor Jacobs <trevor_jacobs@aol.com>; Kris
Cleveland <tridentperfusion@yahoo.com>; Jeff
<bluerocksaddles@willitsonline.com>
Sent: Tue, Oct 15, 2019 1:48 am
Subject: Re: PCMCIA not working on Panasonic Toughbook CF-29

On Tue, Oct 15, 2019 at 05:04:28PM +1100, Michael . wrote:
> Good afternoon kernel developers
> Please accept my apology for contacting you directly about this. A
> small group of friends, some of whom are CCed here, have come together
> to try and find a solution to a problem that originated with the
> demise of kernel 2.6:32. First some background to the issue. We are
> all users of Panasonic Toughbook CF-29 models (ranging from Mark 1
> through to Mark 5). These Toughbooks have 2 PCMCIA card slots which
> are used by a variety of people for different purposes. On the CF-29
> Mark 1 through to Mark 3 these slots work without problem. On the
> CF-29 Mark 4 and Mark 5 the last known kernel the top slot worked with
> was 2.6:32. This has been confirmed all all major distros by most of
> the small group of friends I mentioned earlier.
>
> Thinking it was just a kernel config issue I did some comparisons
> between Debian 6 (Squeeze), Debian 7 (Wheezy), Ubuntu 10.04, and
> Ubuntu 10.10. On all machines both slots functioned as they should
> with Debian 6 and Ubuntu 10.04 but the top slot stopped working on
> Mark 4 and Mark 5 machines on the next release with the next kernel. I
> also tested Ubuntu 10.04 and 10.10 with the 2.6:32 and 2.6:35 kernel
> and both slots worked with the 2.6:32 kernel but not the 2.6:35
> kernel.With my comparisons I merged the config from 2.6:32 into the
> current kernel for Debian 4.19 and rebuilt the kernel, no matter what
> configuration changes I made the top slot still doesn't function on
> Mark 4 and Mark 5 machines.
>
> This issue, and its apparent start, has been confirmed on all major
> distro family groups. So this brings me, actually the small group of
> dedicated Linux users who own Panasonic Toughbook CF-29s, to contact
> you to ask for help in resolving this issue. I have some questions,
> and I realise the 2.6:32 kernel is long gone now but I'm hoping this
> is not a lost cause, what changes would have occurred between 2.6:32
> and 2.6:33 that would have stopped the hardware working on Mark 4 and
> Mark 5 CF-29 Toughbooks but not Mark 1 through to Mark 3? Would it be
> possible to correct the problem so that the hardware on our machines
> works as it should. While we are not kernel devs or even programmers
> we are enthusiasts who love Linux and our machines and we are hoping
> that together with you and the kernel dev group we can fix this issue
> together.
>
> I have attached various tar.gz files with ls* outputs so you can see
> the information we have so far. Thank you for taking the time to read
> this.

Is this with 16-bit PCMCIA cards, or with 32-bit CardBus cards? Either case,
please provide the output of

    dmesg

    lspci -vvv

and

    lspcmcia -v -v

(ideally all for a working and non-working configuration).

Thanks,
    Dominik

[-- Attachment #2: CF-29_MK5_2.6.32.txt --]
[-- Type: text/plain, Size: 57085 bytes --]

Panasonic CF-29 MK5 - Top PCMCIA (CardBUS) slot does work perfectly.
Top slot contains a Ubiquity SuperRange Cardbus WiFi card.
Bottom slot contains an Adaptec USB2connect 2 port USB card.

uname -a
Linux antiX1 2.6.32-1-mepis-smp #1 SMP PREEMPT Wed Apr 7 22:08:34 EDT 2010 i686 GNU/Linux

dmesg
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Linux version 2.6.32-1-mepis-smp (MEPIS 2.6.32-11mepis1) (waldi@debian.org) (gcc version 4.3.2 (Debian 4.3.2-1.1) ) #1 SMP PREEMPT Wed Apr 7 22:08:34 EDT 2010
KERNEL supported cpus:
  Intel GenuineIntel
  AMD AuthenticAMD
  NSC Geode by NSC
  Cyrix CyrixInstead
  Centaur CentaurHauls
  Transmeta GenuineTMx86
  Transmeta TransmetaCPU
  UMC UMC UMC UMC
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009f800 (usable)
 BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 000000007f6e0000 (usable)
 BIOS-e820: 000000007f6e0000 - 000000007f6ee000 (ACPI data)
 BIOS-e820: 000000007f6ee000 - 000000007f700000 (ACPI NVS)
 BIOS-e820: 000000007f700000 - 0000000080000000 (reserved)
 BIOS-e820: 00000000e0000000 - 00000000f0006000 (reserved)
 BIOS-e820: 00000000fed1c000 - 00000000fed90000 (reserved)
 BIOS-e820: 00000000ff000000 - 0000000100000000 (reserved)
DMI 2.3 present.
Phoenix BIOS detected: BIOS may corrupt low RAM, working around it.
e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
last_pfn = 0x7f6e0 max_arch_pfn = 0x100000
MTRR default type: uncachable
MTRR fixed ranges enabled:
  00000-9FFFF write-back
  A0000-BFFFF uncachable
  C0000-CFFFF write-protect
  D0000-DFFFF uncachable
  E0000-E3FFF write-back
  E4000-FFFFF write-protect
MTRR variable ranges enabled:
  0 base 000000000 mask F80000000 write-back
  1 base 07F700000 mask FFFF00000 uncachable
  2 base 07F800000 mask FFF800000 uncachable
  3 disabled
  4 disabled
  5 disabled
  6 disabled
  7 disabled
PAT not supported by CPU.
initial memory mapped : 0 - 01800000
init_memory_mapping: 0000000000000000-00000000373fe000
 0000000000 - 0000400000 page 4k
 0000400000 - 0037000000 page 2M
 0037000000 - 00373fe000 page 4k
kernel direct mapping tables up to 373fe000 @ 10000-16000
RAMDISK: 37a00000 - 37fef213
Allocated new RAMDISK: 00100000 - 006ef213
Move RAMDISK from 0000000037a00000 - 0000000037fef212 to 00100000 - 006ef212
ACPI: RSDP 000f6840 00014 (v00 PTLTD )
ACPI: RSDT 7f6e604a 00040 (v01 PTLTD    RSDT   06040000  LTP 00000000)
ACPI: FACP 7f6ede78 00084 (v02 MATBIO CF29-5   06040000 MEI  00000001)
ACPI: DSDT 7f6e68d0 075A8 (v01 MATBIO   CF29-5 06040000 MSFT 0100000E)
ACPI: FACS 7f6eefc0 00040
ACPI: APIC 7f6edefc 00062 (v01 MATBIO CF29-5   06040000 MEI  00000001)
ACPI: BOOT 7f6edfd8 00028 (v01 PTLTD  $SBFTBL$ 06040000  LTP 00000001)
ACPI: MCFG 7f6edf9c 0003C (v01 MATBIO CF29-5   06040000 MEI  00000001)
ACPI: SSDT 7f6e6487 002B9 (v01  PmRef  Cpu0Ist 00003000 INTL 20030224)
ACPI: SSDT 7f6e62a9 001DE (v01  PmRef  Cpu0Cst 00003001 INTL 20030224)
ACPI: SSDT 7f6e608a 0021F (v01  PmRef    CpuPm 00003000 INTL 20030224)
ACPI: Local APIC address 0xfee00000
1154MB HIGHMEM available.
883MB LOWMEM available.
  mapped low ram: 0 - 373fe000
  low ram: 0 - 373fe000
  node 0 low ram: 00000000 - 373fe000
  node 0 bootmap 00012000 - 00018e80
(9 early reservations) ==> bootmem [0000000000 - 00373fe000]
  #0 [0000000000 - 0000001000]   BIOS data page ==> [0000000000 - 0000001000]
  #1 [0000001000 - 0000002000]    EX TRAMPOLINE ==> [0000001000 - 0000002000]
  #2 [0000006000 - 0000007000]       TRAMPOLINE ==> [0000006000 - 0000007000]
  #3 [0001000000 - 00015d0728]    TEXT DATA BSS ==> [0001000000 - 00015d0728]
  #4 [000009f800 - 0000100000]    BIOS reserved ==> [000009f800 - 0000100000]
  #5 [00015d1000 - 00015d71b4]              BRK ==> [00015d1000 - 00015d71b4]
  #6 [0000010000 - 0000012000]          PGTABLE ==> [0000010000 - 0000012000]
  #7 [0000100000 - 00006ef213]      NEW RAMDISK ==> [0000100000 - 00006ef213]
  #8 [0000012000 - 0000019000]          BOOTMAP ==> [0000012000 - 0000019000]
Zone PFN ranges:
  DMA      0x00000010 -> 0x00001000
  Normal   0x00001000 -> 0x000373fe
  HighMem  0x000373fe -> 0x0007f6e0
Movable zone start PFN for each node
early_node_map[2] active PFN ranges
    0: 0x00000010 -> 0x0000009f
    0: 0x00000100 -> 0x0007f6e0
On node 0 totalpages: 521839
free_area_init_node: node 0, pgdat c14e69a0, node_mem_map c15d9200
  DMA zone: 32 pages used for memmap
  DMA zone: 0 pages reserved
  DMA zone: 3951 pages, LIFO batch:0
  Normal zone: 1736 pages used for memmap
  Normal zone: 220470 pages, LIFO batch:31
  HighMem zone: 2310 pages used for memmap
  HighMem zone: 293340 pages, LIFO batch:31
Using APIC driver default
ACPI: PM-Timer IO Port: 0x1008
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] disabled)
ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
ACPI: IRQ0 used by override.
ACPI: IRQ2 used by override.
ACPI: IRQ9 used by override.
Using ACPI (MADT) for SMP configuration information
SMP: Allowing 2 CPUs, 1 hotplug CPUs
nr_irqs_gsi: 24
PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
PM: Registered nosave memory: 00000000000a0000 - 00000000000e0000
PM: Registered nosave memory: 00000000000e0000 - 0000000000100000
Allocating PCI resources starting at 80000000 (gap: 80000000:60000000)
Booting paravirtualized kernel on bare hardware
NR_CPUS:32 nr_cpumask_bits:32 nr_cpu_ids:2 nr_node_ids:1
PERCPU: Embedded 13 pages/cpu @c2800000 s29624 r0 d23624 u2097152
pcpu-alloc: s29624 r0 d23624 u2097152 alloc=1*4194304
pcpu-alloc: [0] 0 1 
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 517761
Kernel command line: root=/dev/sda2 nomce quiet nosplash vga=791
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Initializing CPU#0
Initializing HighMem for node 0 (000373fe:0007f6e0)
Memory: 2057076k/2087808k available (3420k kernel code, 29352k reserved, 1623k data, 376k init, 1182600k highmem)
virtual kernel memory layout:
    fixmap  : 0xffd56000 - 0xfffff000   (2724 kB)
    pkmap   : 0xff400000 - 0xff800000   (4096 kB)
    vmalloc : 0xf7bfe000 - 0xff3fe000   ( 120 MB)
    lowmem  : 0xc0000000 - 0xf73fe000   ( 883 MB)
      .init : 0xc14ed000 - 0xc154b000   ( 376 kB)
      .data : 0xc1357031 - 0xc14ece18   (1623 kB)
      .text : 0xc1000000 - 0xc1357031   (3420 kB)
Checking if this processor honours the WP bit even in supervisor mode...Ok.
SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:1280
Console: colour dummy device 80x25
console [tty0] enabled
Fast TSC calibration using PIT
Detected 1595.807 MHz processor.
Calibrating delay loop (skipped), value calculated using timer frequency.. 3192.59 BogoMIPS (lpj=5319356)
Security Framework initialized
SELinux:  Disabled at boot.
Mount-cache hash table entries: 512
Initializing cgroup subsys ns
Initializing cgroup subsys cpuacct
Initializing cgroup subsys devices
Initializing cgroup subsys freezer
Initializing cgroup subsys net_cls
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 2048K
Performance Events: p6 PMU driver.
... version:                0
... bit width:              32
... generic registers:      2
... value mask:             00000000ffffffff
... max period:             000000007fffffff
... fixed-purpose events:   0
... event mask:             0000000000000003
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
ACPI: Core revision 20090903
Enabling APIC mode:  Flat.  Using 1 I/O APICs
..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
CPU0: Intel(R) Pentium(R) M processor 1.60GHz stepping 08
Brought up 1 CPUs
Total of 1 processors activated (3192.59 BogoMIPS).
regulator: core version 0.5
NET: Registered protocol family 16
ACPI: bus type pci registered
PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 255
PCI: MCFG area at e0000000 reserved in E820
PCI: Using MMCONFIG for extended config space
PCI: Using configuration type 1 for base access
bio: create slab <bio-0> at 0
ACPI: EC: Look up EC in DSDT
ACPI: Interpreter enabled
ACPI: (supports S0 S3 S4 S5)
ACPI: Using IOAPIC for interrupt routing
ACPI: EC: GPE = 0x1d, I/O: command/status = 0x66, data = 0x62
ACPI: ACPI Dock Station Driver: 1 docks/bays found
ACPI: PCI Root Bridge [PCI0] (0000:00)
pci 0000:00:02.0: reg 10 32bit mmio: [0xb0080000-0xb00fffff]
pci 0000:00:02.0: reg 14 io port: [0x1800-0x1807]
pci 0000:00:02.0: reg 18 32bit mmio pref: [0xc0000000-0xcfffffff]
pci 0000:00:02.0: reg 1c 32bit mmio: [0xb0000000-0xb003ffff]
pci 0000:00:02.1: reg 10 32bit mmio: [0x000000-0x07ffff]
pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
pci 0000:00:1c.0: PME# disabled
pci 0000:00:1d.0: reg 20 io port: [0x1820-0x183f]
pci 0000:00:1d.1: reg 20 io port: [0x1840-0x185f]
pci 0000:00:1d.2: reg 20 io port: [0x1860-0x187f]
pci 0000:00:1d.7: reg 10 32bit mmio: [0xb0040000-0xb00403ff]
pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
pci 0000:00:1d.7: PME# disabled
pci 0000:00:1e.2: reg 10 io port: [0x1c00-0x1cff]
pci 0000:00:1e.2: reg 14 io port: [0x18c0-0x18ff]
pci 0000:00:1e.2: reg 18 32bit mmio: [0xb0040800-0xb00409ff]
pci 0000:00:1e.2: reg 1c 32bit mmio: [0xb0040400-0xb00404ff]
pci 0000:00:1e.2: PME# supported from D0 D3hot D3cold
pci 0000:00:1e.2: PME# disabled
pci 0000:00:1e.3: reg 10 io port: [0x2400-0x24ff]
pci 0000:00:1e.3: reg 14 io port: [0x2000-0x207f]
pci 0000:00:1e.3: PME# supported from D0 D3hot D3cold
pci 0000:00:1e.3: PME# disabled
pci 0000:00:1f.0: Force enabled HPET at 0xfed00000
pci 0000:00:1f.0: quirk: region 1000-107f claimed by ICH6 ACPI/GPIO/TCO
pci 0000:00:1f.0: quirk: region 1180-11bf claimed by ICH6 GPIO
pci 0000:00:1f.0: LPC Generic IO decode 1 PIO at 0900-097f
pci 0000:00:1f.2: reg 10 io port: [0x00-0x07]
pci 0000:00:1f.2: reg 14 io port: [0x00-0x03]
pci 0000:00:1f.2: reg 18 io port: [0x00-0x07]
pci 0000:00:1f.2: reg 1c io port: [0x00-0x03]
pci 0000:00:1f.2: reg 20 io port: [0x1890-0x189f]
pci 0000:00:1f.2: PME# supported from D3hot
pci 0000:00:1f.2: PME# disabled
pci 0000:00:1f.3: reg 20 io port: [0x18a0-0x18bf]
pci 0000:02:00.0: reg 10 64bit mmio: [0xb4000000-0xb4003fff]
pci 0000:02:00.0: reg 18 io port: [0x3000-0x30ff]
pci 0000:02:00.0: reg 30 32bit mmio pref: [0x000000-0x01ffff]
pci 0000:02:00.0: supports D1 D2
pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:02:00.0: PME# disabled
pci 0000:00:1c.0: bridge io port: [0x3000-0x3fff]
pci 0000:00:1c.0: bridge 32bit mmio: [0xb4000000-0xb7ffffff]
pci 0000:00:1c.0: bridge 64bit mmio pref: [0xd0000000-0xd3ffffff]
pci 0000:06:01.0: reg 10 32bit mmio: [0x000000-0x000fff]
pci 0000:06:01.0: supports D1 D2
pci 0000:06:01.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:06:01.0: PME# disabled
pci 0000:06:01.1: reg 10 32bit mmio: [0x000000-0x000fff]
pci 0000:06:01.1: supports D1 D2
pci 0000:06:01.1: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:06:01.1: PME# disabled
pci 0000:06:01.2: reg 10 32bit mmio: [0xb8000000-0xb80000ff]
pci 0000:06:01.2: supports D1 D2
pci 0000:06:01.2: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:06:01.2: PME# disabled
pci 0000:06:02.0: reg 10 32bit mmio: [0xb8001000-0xb8001fff]
pci 0000:06:02.0: PME# supported from D0 D3hot D3cold
pci 0000:06:02.0: PME# disabled
pci 0000:00:1e.0: transparent bridge
pci 0000:00:1e.0: bridge 32bit mmio: [0xb8000000-0xb80fffff]
pci_bus 0000:00: on NUMA node 0
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP01._PRT]
ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCIB._PRT]
ACPI: PCI Interrupt Link [LNKA] (IRQs *9)
ACPI: PCI Interrupt Link [LNKB] (IRQs *9)
ACPI: PCI Interrupt Link [LNKC] (IRQs *9)
ACPI: PCI Interrupt Link [LNKD] (IRQs *9)
ACPI: PCI Interrupt Link [LNKE] (IRQs *9)
ACPI: PCI Interrupt Link [LNKF] (IRQs *9)
ACPI: PCI Interrupt Link [LNKG] (IRQs 9) *0, disabled.
ACPI: PCI Interrupt Link [LNKH] (IRQs *9)
vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
vgaarb: loaded
SCSI subsystem initialized
libata version 3.00 loaded.
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
PCI: Using ACPI for IRQ routing
hpet clockevent registered
HPET: 3 timers in total, 0 timers will be used for per-cpu timer
hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
hpet0: 3 comparators, 64-bit 14.318180 MHz counter
Switching to clocksource tsc
pnp: PnP ACPI init
ACPI: bus type pnp registered
pnp: PnP ACPI: found 14 devices
ACPI: ACPI bus type pnp unregistered
PnPBIOS: Disabled by ACPI PNP
system 00:01: iomem range 0xcf200-0xcf7ff has been reserved
system 00:01: iomem range 0xd0800-0xd3fff has been reserved
system 00:02: ioport range 0x900-0x91f has been reserved
system 00:02: ioport range 0x92c-0x97f has been reserved
system 00:02: ioport range 0xfe00-0xfe01 has been reserved
system 00:02: ioport range 0x920-0x92b has been reserved
system 00:02: iomem range 0xfed40000-0xfed44fff has been reserved
system 00:03: ioport range 0x2e0-0x2e7 has been reserved
system 00:03: ioport range 0x330-0x337 has been reserved
system 00:07: ioport range 0x800-0x80f has been reserved
system 00:07: ioport range 0x1000-0x107f has been reserved
system 00:07: ioport range 0x1180-0x11bf has been reserved
system 00:07: iomem range 0xe0000000-0xefffffff has been reserved
system 00:07: iomem range 0xf0000000-0xf0003fff has been reserved
system 00:07: iomem range 0xf0004000-0xf0004fff has been reserved
system 00:07: iomem range 0xf0005000-0xf0005fff has been reserved
system 00:07: iomem range 0xf0008000-0xf000bfff has been reserved
system 00:07: iomem range 0xfed20000-0xfed3ffff has been reserved
system 00:07: iomem range 0xfed45000-0xfed8ffff has been reserved
pci 0000:00:1c.0: PCI bridge, secondary bus 0000:02
pci 0000:00:1c.0:   IO window: 0x3000-0x3fff
pci 0000:00:1c.0:   MEM window: 0xb4000000-0xb7ffffff
pci 0000:00:1c.0:   PREFETCH window: 0x000000d0000000-0x000000d3ffffff
pci 0000:06:01.0: CardBus bridge, secondary bus 0000:07
pci 0000:06:01.0:   IO window: 0x004000-0x0040ff
pci 0000:06:01.0:   IO window: 0x004400-0x0044ff
pci 0000:06:01.0:   PREFETCH window: 0x80000000-0x83ffffff
pci 0000:06:01.0:   MEM window: 0x8c000000-0x8fffffff
pci 0000:06:01.1: CardBus bridge, secondary bus 0000:08
pci 0000:06:01.1:   IO window: 0x004800-0x0048ff
pci 0000:06:01.1:   IO window: 0x004c00-0x004cff
pci 0000:06:01.1:   PREFETCH window: 0x84000000-0x87ffffff
pci 0000:06:01.1:   MEM window: 0x90000000-0x93ffffff
pci 0000:00:1e.0: PCI bridge, secondary bus 0000:06
pci 0000:00:1e.0:   IO window: 0x4000-0x4fff
pci 0000:00:1e.0:   MEM window: 0xb8000000-0xb80fffff
pci 0000:00:1e.0:   PREFETCH window: 0x80000000-0x87ffffff
pci 0000:00:1c.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17
pci 0000:00:1c.0: setting latency timer to 64
pci 0000:00:1e.0: setting latency timer to 64
pci 0000:06:01.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
pci 0000:06:01.1: PCI INT B -> GSI 21 (level, low) -> IRQ 21
pci_bus 0000:00: resource 0 io:  [0x00-0xffff]
pci_bus 0000:00: resource 1 mem: [0x000000-0xffffffff]
pci_bus 0000:02: resource 0 io:  [0x3000-0x3fff]
pci_bus 0000:02: resource 1 mem: [0xb4000000-0xb7ffffff]
pci_bus 0000:02: resource 2 pref mem [0xd0000000-0xd3ffffff]
pci_bus 0000:06: resource 0 io:  [0x4000-0x4fff]
pci_bus 0000:06: resource 1 mem: [0xb8000000-0xb80fffff]
pci_bus 0000:06: resource 2 pref mem [0x80000000-0x87ffffff]
pci_bus 0000:06: resource 3 io:  [0x00-0xffff]
pci_bus 0000:06: resource 4 mem: [0x000000-0xffffffff]
pci_bus 0000:07: resource 0 io:  [0x4000-0x40ff]
pci_bus 0000:07: resource 1 io:  [0x4400-0x44ff]
pci_bus 0000:07: resource 2 pref mem [0x80000000-0x83ffffff]
pci_bus 0000:07: resource 3 mem: [0x8c000000-0x8fffffff]
pci_bus 0000:08: resource 0 io:  [0x4800-0x48ff]
pci_bus 0000:08: resource 1 io:  [0x4c00-0x4cff]
pci_bus 0000:08: resource 2 pref mem [0x84000000-0x87ffffff]
pci_bus 0000:08: resource 3 mem: [0x90000000-0x93ffffff]
NET: Registered protocol family 2
IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
TCP bind hash table entries: 65536 (order: 7, 524288 bytes)
TCP: Hash tables configured (established 131072 bind 65536)
TCP reno registered
NET: Registered protocol family 1
pci 0000:00:02.0: Boot video device
Trying to unpack rootfs image as initramfs...
Freeing initrd memory: 6076k freed
Simple Boot Flag at 0x41 set to 0x1
audit: initializing netlink socket (disabled)
type=2000 audit(1571245481.633:1): initialized
highmem bounce pool size: 64 pages
VFS: Disk quotas dquot_6.5.2
Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
squashfs: version 4.0 (2009/01/31) Phillip Lougher
NTFS driver 2.1.29 [Flags: R/W].
msgmni has been set to 1721
alg: No test for stdrng (krng)
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
pcieport 0000:00:1c.0: irq 24 for MSI/MSI-X
pcieport 0000:00:1c.0: setting latency timer to 64
vesafb: framebuffer at 0xc0000000, mapped to 0xf7c80000, using 3072k, total 7872k
vesafb: mode is 1024x768x16, linelength=2048, pages=4
vesafb: scrolling: redraw
vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
Console: switching to colour frame buffer device 128x48
fb0: VESA VGA frame buffer device
isapnp: Scanning for PnP cards...
isapnp: No Plug & Play device found
Linux agpgart interface v0.103
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
00:0c: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
serial 0000:00:1e.3: PCI INT B -> GSI 17 (level, low) -> IRQ 17
serial 0000:00:1e.3: PCI INT B disabled
brd: module loaded
loop: module loaded
input: Macintosh mouse button emulation as /devices/virtual/input/input0
Uniform Multi-Platform E-IDE driver
ide-cd driver 5.00
ahci 0000:00:1f.2: version 3.0
ahci 0000:00:1f.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
ahci 0000:00:1f.2: PCI INT B disabled
ahci: probe of 0000:00:1f.2 failed with error -22
ata_piix 0000:00:1f.2: version 2.13
ata_piix 0000:00:1f.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19
ata_piix 0000:00:1f.2: MAP [ P0 P2 IDE IDE ]
ata_piix 0000:00:1f.2: setting latency timer to 64
scsi0 : ata_piix
scsi1 : ata_piix
ata1: SATA max UDMA/133 cmd 0x1f0 ctl 0x3f6 bmdma 0x1890 irq 14
ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x1898 irq 15
ieee1394: raw1394: /dev/raw1394 device initialized
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci_hcd 0000:00:1d.7: PCI INT A -> GSI 23 (level, low) -> IRQ 23
ehci_hcd 0000:00:1d.7: setting latency timer to 64
ehci_hcd 0000:00:1d.7: EHCI Host Controller
ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 1
ehci_hcd 0000:00:1d.7: debug port 1
ehci_hcd 0000:00:1d.7: cache line size of 32 is not supported
ehci_hcd 0000:00:1d.7: irq 23, io mem 0xb0040000
ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
usb usb1: Manufacturer: Linux 2.6.32-1-mepis-smp ehci_hcd
usb usb1: SerialNumber: 0000:00:1d.7
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 6 ports detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver ums-alauda
usbcore: registered new interface driver ums-cypress
usbcore: registered new interface driver ums-datafab
usbcore: registered new interface driver ums-freecom
usbcore: registered new interface driver ums-isd200
usbcore: registered new interface driver ums-jumpshot
usbcore: registered new interface driver ums-karma
usbcore: registered new interface driver ums-onetouch
usbcore: registered new interface driver ums-sddr09
usbcore: registered new interface driver ums-sddr55
usbcore: registered new interface driver ums-usbat
PNP: PS/2 Controller [PNP0303:K101,FJC6001:MOU1] at 0x60,0x64 irq 1,12
serio: i8042 KBD port at 0x60,0x64 irq 1
serio: i8042 AUX port at 0x60,0x64 irq 12
mice: PS/2 mouse device common for all mice
rtc_cmos 00:08: RTC can wake from S4
rtc_cmos 00:08: rtc core: registered rtc_cmos as rtc0
rtc0: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
cpuidle: using governor ladder
cpuidle: using governor menu
No iBFT detected.
TCP cubic registered
NET: Registered protocol family 10
lo: Disabled Privacy Extensions
Mobile IPv6
NET: Registered protocol family 17
Using IPI No-Shortcut mode
rtc_cmos 00:08: setting system clock to 2019-10-16 17:04:42 UTC (1571245482)
input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input1
ata2.00: ATAPI: UJDA760 DVD/CDRW, 1.00, max UDMA/33
ata1.00: ATA-8: SAMSUNG SSD PM830 mSATA 32GB, CXM12D1Q, max UDMA/133
ata1.00: 62533296 sectors, multi 16: LBA48 
ata2.00: configured for UDMA/33
ata1.00: configured for UDMA/133
scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SSD PM83 CXM1 PQ: 0 ANSI: 5
sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
 sda: sda1 sda2 sda3
sd 0:0:0:0: [sda] Attached SCSI disk
scsi 1:0:0:0: CD-ROM            MATSHITA UJDA760 DVD/CDRW 1.00 PQ: 0 ANSI: 5
sr0: scsi3-mmc drive: 24x/24x writer cd/rw xa/form2 cdda tray
Uniform CD-ROM driver Revision: 3.20
sr 1:0:0:0: Attached scsi CD-ROM sr0
sr 1:0:0:0: Attached scsi generic sg1 type 5
Freeing unused kernel memory: 376k freed
thermal LNXTHERM:01: registered as thermal_zone0
ACPI: Thermal Zone [TZC] (55 C)
agpgart-intel 0000:00:00.0: Intel 915GM Chipset
agpgart-intel 0000:00:00.0: detected 7932K stolen memory
sky2 driver version 1.25
sky2 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
sky2 0000:02:00.0: setting latency timer to 64
sky2 0000:02:00.0: Yukon-2 EC chip revision 1
sky2 0000:02:00.0: irq 25 for MSI/MSI-X
input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input2
uhci_hcd: USB Universal Host Controller Interface driver
ACPI: Lid Switch [LID]
input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input3
ACPI: Power Button [PWRB]
input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4
ACPI: Power Button [PWRF]
sky2 eth0: addr 00:0b:97:96:26:50
agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xc0000000
uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23
uhci_hcd 0000:00:1d.0: setting latency timer to 64
uhci_hcd 0000:00:1d.0: UHCI Host Controller
uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
uhci_hcd 0000:00:1d.0: irq 23, io base 0x00001820
usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb2: Product: UHCI Host Controller
usb usb2: Manufacturer: Linux 2.6.32-1-mepis-smp uhci_hcd
usb usb2: SerialNumber: 0000:00:1d.0
usb usb2: configuration #1 chosen from 1 choice
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19
uhci_hcd 0000:00:1d.1: setting latency timer to 64
uhci_hcd 0000:00:1d.1: UHCI Host Controller
uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3
uhci_hcd 0000:00:1d.1: irq 19, io base 0x00001840
usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb3: Product: UHCI Host Controller
usb usb3: Manufacturer: Linux 2.6.32-1-mepis-smp uhci_hcd
usb usb3: SerialNumber: 0000:00:1d.1
usb usb3: configuration #1 chosen from 1 choice
hub 3-0:1.0: USB hub found
hub 3-0:1.0: 2 ports detected
uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
uhci_hcd 0000:00:1d.2: setting latency timer to 64
uhci_hcd 0000:00:1d.2: UHCI Host Controller
uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4
uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001860
usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb4: Product: UHCI Host Controller
usb usb4: Manufacturer: Linux 2.6.32-1-mepis-smp uhci_hcd
usb usb4: SerialNumber: 0000:00:1d.2
usb usb4: configuration #1 chosen from 1 choice
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 2 ports detected
input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input5
ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pci 0000:06:01.2: SDHCI controller found [1180:0822] (rev 11)
sdhci-pci 0000:06:01.2: PCI INT C -> GSI 19 (level, low) -> IRQ 19
Registered led device: mmc0::
mmc0: SDHCI controller on PCI [0000:06:01.2] using PIO
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting.  Commit interval 5 seconds
udev: starting version 151
intel_rng: FWH not detected
lib80211: common routines for IEEE802.11 drivers
lib80211_crypt: registered algorithm 'NULL'
ACPI: AC Adapter [AC] (on-line)
Marking TSC unstable due to TSC halts in idle
processor LNXCPU:00: registered as cooling_device0
Switching to clocksource hpet
ieee80211: 802.11 data/management/control stack, git-1.1.13
ieee80211: Copyright (C) 2004-2005 Intel Corporation <jketreno@linux.intel.com>
ACPI: Battery Slot [BATA] (battery present)
input: Panasonic Laptop Support as /devices/virtual/input/input6
ACPI: Battery Slot [BATB] (battery absent)
yenta_cardbus 0000:06:01.0: CardBus bridge found [10f7:8338]
parport_pc 00:0d: reported by Plug and Play ACPI
parport0: PC-style at 0x378 (0x778), irq 5 [PCSPP,TRISTATE]
ipw2200: Intel(R) PRO/Wireless 2200/2915 Network Driver, 1.2.2kmprq
ipw2200: Copyright(c) 2003-2006 Intel Corporation
input: PS/2 Touchpad as /devices/platform/i8042/serio1/input/input7
Intel ICH Modem 0000:00:1e.3: PCI INT B -> GSI 17 (level, low) -> IRQ 17
Intel ICH Modem 0000:00:1e.3: setting latency timer to 64
yenta_cardbus 0000:06:01.0: ISA IRQ mask 0x0c98, PCI irq 20
yenta_cardbus 0000:06:01.0: Socket status: 30000820
yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge I/O window: 0x4000 - 0x4fff
pcmcia_socket pcmcia_socket0: cs: IO port probe 0x4000-0x4fff: clean.
yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge Memory window: 0xb8000000 - 0xb80fffff
yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge Memory window: 0x80000000 - 0x87ffffff
ipw2200 0000:06:02.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18
ipw2200: Detected Intel PRO/Wireless 2915ABG Network Connection
ipw2200 0000:06:02.0: firmware: requesting ipw2200-bss.fw
Intel ICH 0000:00:1e.2: PCI INT A -> GSI 17 (level, low) -> IRQ 17
Intel ICH 0000:00:1e.2: setting latency timer to 64
input: LBPS/2 Fujitsu Lifebook TouchScreen as /devices/platform/i8042/serio1/input/input8
ipw2200: Detected geography ZZA (11 802.11bg channels, 13 802.11a channels)
yenta_cardbus 0000:06:01.1: CardBus bridge found [10f7:8338]
yenta_cardbus 0000:06:01.1: ISA IRQ mask 0x0c98, PCI irq 21
yenta_cardbus 0000:06:01.1: Socket status: 30000820
pci_bus 0000:06: Raising subordinate bus# of parent bus (#06) from #08 to #0b
yenta_cardbus 0000:06:01.1: pcmcia: parent PCI bridge I/O window: 0x4000 - 0x4fff
pcmcia_socket pcmcia_socket1: cs: IO port probe 0x4000-0x4fff: clean.
yenta_cardbus 0000:06:01.1: pcmcia: parent PCI bridge Memory window: 0xb8000000 - 0xb80fffff
yenta_cardbus 0000:06:01.1: pcmcia: parent PCI bridge Memory window: 0x80000000 - 0x87ffffff
pcmcia_socket pcmcia_socket0: pccard: CardBus card inserted into slot 0
pci 0000:07:00.0: reg 10 32bit mmio: [0x000000-0x000fff]
pci 0000:07:00.0: supports D1 D2
pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot
pci 0000:07:00.0: PME# disabled
pci 0000:07:00.1: reg 10 32bit mmio: [0x000000-0x000fff]
pci 0000:07:00.1: supports D1 D2
pci 0000:07:00.1: PME# supported from D0 D1 D2 D3hot
pci 0000:07:00.1: PME# disabled
pci 0000:07:00.2: reg 10 32bit mmio: [0x000000-0x0000ff]
pci 0000:07:00.2: supports D1 D2
pci 0000:07:00.2: PME# supported from D0 D1 D2 D3hot
pci 0000:07:00.2: PME# disabled
ehci_hcd 0000:07:00.2: enabling device (0000 -> 0002)
ehci_hcd 0000:07:00.2: PCI INT C -> GSI 20 (level, low) -> IRQ 20
ehci_hcd 0000:07:00.2: EHCI Host Controller
ehci_hcd 0000:07:00.2: new USB bus registered, assigned bus number 5
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ohci_hcd 0000:07:00.0: enabling device (0000 -> 0002)
ohci_hcd 0000:07:00.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
ohci_hcd 0000:07:00.0: setting latency timer to 64
ohci_hcd 0000:07:00.0: OHCI Host Controller
ohci_hcd 0000:07:00.0: new USB bus registered, assigned bus number 6
ohci_hcd 0000:07:00.0: irq 20, io mem 0x8c000000
ehci_hcd 0000:07:00.2: irq 20, io mem 0x8c002000
ehci_hcd 0000:07:00.2: USB 2.0 started, EHCI 1.00
usb usb5: New USB device found, idVendor=1d6b, idProduct=0002
usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb5: Product: EHCI Host Controller
usb usb5: Manufacturer: Linux 2.6.32-1-mepis-smp ehci_hcd
usb usb5: SerialNumber: 0000:07:00.2
usb usb5: configuration #1 chosen from 1 choice
hub 5-0:1.0: USB hub found
hub 5-0:1.0: 5 ports detected
usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb6: Product: OHCI Host Controller
usb usb6: Manufacturer: Linux 2.6.32-1-mepis-smp ohci_hcd
usb usb6: SerialNumber: 0000:07:00.0
usb usb6: configuration #1 chosen from 1 choice
hub 6-0:1.0: USB hub found
hub 6-0:1.0: 3 ports detected
ohci_hcd 0000:07:00.1: enabling device (0000 -> 0002)
ohci_hcd 0000:07:00.1: PCI INT B -> GSI 20 (level, low) -> IRQ 20
ohci_hcd 0000:07:00.1: setting latency timer to 64
ohci_hcd 0000:07:00.1: OHCI Host Controller
ohci_hcd 0000:07:00.1: new USB bus registered, assigned bus number 7
ohci_hcd 0000:07:00.1: irq 20, io mem 0x8c001000
usb usb7: New USB device found, idVendor=1d6b, idProduct=0001
usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb7: Product: OHCI Host Controller
usb usb7: Manufacturer: Linux 2.6.32-1-mepis-smp ohci_hcd
usb usb7: SerialNumber: 0000:07:00.1
usb usb7: configuration #1 chosen from 1 choice
hub 7-0:1.0: USB hub found
hub 7-0:1.0: 2 ports detected
intel8x0_measure_ac97_clock: measured 52774 usecs (2543 samples)
intel8x0: clocking to 48000
pcmcia_socket pcmcia_socket1: pccard: CardBus card inserted into slot 1
pci 0000:08:00.0: reg 10 32bit mmio: [0x000000-0x00ffff]
pcmcia_socket pcmcia_socket1: cs: IO port probe 0x100-0x3af: clean.
pcmcia_socket pcmcia_socket1: cs: IO port probe 0x3e0-0x4ff: excluding 0x4d0-0x4d7
pcmcia_socket pcmcia_socket1: cs: IO port probe 0x820-0x8ff: clean.
pcmcia_socket pcmcia_socket1: cs: IO port probe 0xc00-0xcf7: clean.
pcmcia_socket pcmcia_socket1: cs: IO port probe 0xa00-0xaff: clean.
pcmcia_socket pcmcia_socket0: cs: IO port probe 0x100-0x3af: clean.
pcmcia_socket pcmcia_socket0: cs: IO port probe 0x3e0-0x4ff: excluding 0x4d0-0x4d7
pcmcia_socket pcmcia_socket0: cs: IO port probe 0x820-0x8ff: clean.
pcmcia_socket pcmcia_socket0: cs: IO port probe 0xc00-0xcf7: clean.
pcmcia_socket pcmcia_socket0: cs: IO port probe 0xa00-0xaff: clean.
cfg80211: Using static regulatory domain info
cfg80211: Regulatory domain: US
	(start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
	(2402000 KHz - 2472000 KHz @ 40000 KHz), (600 mBi, 2700 mBm)
	(5170000 KHz - 5190000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
	(5190000 KHz - 5210000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
	(5210000 KHz - 5230000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
	(5230000 KHz - 5330000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
	(5735000 KHz - 5835000 KHz @ 40000 KHz), (600 mBi, 3000 mBm)
cfg80211: Calling CRDA for country: US
ath5k 0000:08:00.0: enabling device (0000 -> 0002)
ath5k 0000:08:00.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21
ath5k 0000:08:00.0: registered as 'phy0'
usb 7-1: new full speed USB device using ohci_hcd and address 2
usb 7-1: New USB device found, idVendor=046d, idProduct=c52f
usb 7-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 7-1: Product: USB Receiver
usb 7-1: Manufacturer: Logitech
usb 7-1: configuration #1 chosen from 1 choice
usbcore: registered new interface driver hiddev
input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb7/7-1/7-1:1.0/input/input9
generic-usb 0003:046D:C52F.0001: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:07:00.1-1/input0
input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb7/7-1/7-1:1.1/input/input10
generic-usb 0003:046D:C52F.0002: input,hiddev96,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:07:00.1-1/input1
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
ath: EEPROM regdomain: 0x0
ath: EEPROM indicates default country code should be used
ath: doing EEPROM country->regdmn map search
ath: country maps to regdmn code: 0x3a
ath: Country alpha2 being used: US
ath: Regpair used: 0x3a
phy0: Selected rate control algorithm 'minstrel'
ath5k phy0: Atheros AR5213A chip found (MAC: 0x59, PHY: 0x43)
ath5k phy0: RF5112B multiband radio found (0x36)
cfg80211: Calling CRDA for country: US
EXT3 FS on sda2, internal journal
Adding 2882552k swap on /dev/sda3.  Priority:1 extents:1 across:2882552k SS
fuse init (API version 7.13)
sky2 eth0: enabling interface
ADDRCONF(NETDEV_UP): eth0: link is not ready
lp0: using parport0 (interrupt-driven).
ppdev: user-space parallel port driver
[drm] Initialized drm 1.1.0 20060810
pci 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
pci 0000:00:02.0: setting latency timer to 64
[drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
usb 1-1: new high speed USB device using ehci_hcd and address 2
usb 1-1: New USB device found, idVendor=1aa6, idProduct=0201
usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-1: Product: Pen Drive
usb 1-1: Manufacturer: eFortune
usb 1-1: SerialNumber:   5940314711321
usb 1-1: configuration #1 chosen from 1 choice
scsi2 : SCSI emulation for USB Mass Storage devices
usb-storage: device found at 2
usb-storage: waiting for device to settle before scanning
usb-storage: device scan complete
scsi 2:0:0:0: Direct-Access     eFortune Pen Drive        1.00 PQ: 0 ANSI: 0 CCS
sd 2:0:0:0: Attached scsi generic sg2 type 0
sd 2:0:0:0: [sdb] 1990656 512-byte logical blocks: (1.01 GB/972 MiB)
sd 2:0:0:0: [sdb] Write Protect is off
sd 2:0:0:0: [sdb] Mode Sense: 03 00 00 00
sd 2:0:0:0: [sdb] Assuming drive cache: write through
sd 2:0:0:0: [sdb] Assuming drive cache: write through
 sdb: sdb1
sd 2:0:0:0: [sdb] Assuming drive cache: write through
sd 2:0:0:0: [sdb] Attached SCSI removable disk

lspci -vvv
00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information: Len=09 <?>
	Kernel driver in use: agpgart-intel

00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04) (prog-if 00 [VGA controller])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at b0080000 (32-bit, non-prefetchable) [size=512K]
	Region 1: I/O ports at 1800 [size=8]
	Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M]
	Region 3: Memory at b0000000 (32-bit, non-prefetchable) [size=256K]
	Expansion ROM at <unassigned> [disabled]
	Capabilities: [d0] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Region 0: Memory at 88000000 (32-bit, non-prefetchable) [disabled] [size=512K]
	Capabilities: [d0] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

00:1c.0 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1 (rev 04) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 32 bytes
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: b4000000-b7ffffff
	Prefetchable memory behind bridge: 00000000d0000000-00000000d3ffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag+ RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
			Slot #2, PowerLimit 6.500W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
	Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
		Address: fee0100c  Data: 4161
	Capabilities: [90] Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed+ WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
		VC1:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable- ID=0 ArbSelect=Fixed TC/VC=00
			Status:	NegoPending- InProgress-
	Capabilities: [180 v1] Root Complex Link
		Desc:	PortNumber=01 ComponentID=02 EltType=Config
		Link0:	Desc:	TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
			Addr:	00000000fed1c001
	Kernel driver in use: pcieport

00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 4: I/O ports at 1820 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at 1840 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 18
	Region 4: I/O ports at 1860 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 0: Memory at b0040000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+
	Capabilities: [58] Debug port: BAR=1 offset=00a0
	Kernel driver in use: ehci_hcd

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4) (prog-if 01 [Subtractive decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=06, subordinate=0b, sec-latency=32
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: b8000000-b80fffff
	Prefetchable memory behind bridge: 0000000080000000-0000000087ffffff
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338

00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 834c
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 17
	Region 0: I/O ports at 1c00 [size=256]
	Region 1: I/O ports at 18c0 [size=64]
	Region 2: Memory at b0040800 (32-bit, non-prefetchable) [size=512]
	Region 3: Memory at b0040400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: Intel ICH

00:1e.3 Modem: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller (rev 04) (prog-if 00 [Generic])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 17
	Region 0: I/O ports at 2400 [size=256]
	Region 1: I/O ports at 2000 [size=128]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: Intel ICH Modem

00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0

00:1f.2 IDE interface: Intel Corporation 82801FBM (ICH6M) SATA Controller (rev 04) (prog-if 80 [Master])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 0: I/O ports at 01f0 [size=8]
	Region 1: I/O ports at 03f4 [size=1]
	Region 2: I/O ports at 0170 [size=8]
	Region 3: I/O ports at 0374 [size=1]
	Region 4: I/O ports at 1890 [size=16]
	Capabilities: [70] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ata_piix

00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Device 8338
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 9
	Region 4: I/O ports at 18a0 [size=32]

02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8053 PCI-E Gigabit Ethernet Controller (rev 19)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 25
	Region 0: Memory at b4000000 (64-bit, non-prefetchable) [size=16K]
	Region 2: I/O ports at 3000 [size=256]
	[virtual] Expansion ROM at d0000000 [disabled] [size=128K]
	Capabilities: [48] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
	Capabilities: [50] Vital Product Data
		Product Name: Marvell Yukon 88E8053 Gigabit Ethernet Controller
		Read-only fields:
			[PN] Part number: Yukon 88E8053
			[EC] Engineering changes: Rev. 1.9
			[MN] Manufacture ID: 4d 61 72 76 65 6c 6c
			[SN] Serial number: AbCdEfG962650
			[CP] Extended capability: 01 10 cc 03
			[RV] Reserved: checksum good, 9 byte(s) reserved
		Read/write fields:
			[RW] Read-write area: 121 byte(s) free
		End
	Capabilities: [5c] MSI: Enable+ Count=1/2 Maskable- 64bit+
		Address: 00000000fee0100c  Data: 4181
	Capabilities: [e0] Express (v1) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr+ NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 <256ns, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot-
		LnkCtl:	ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Capabilities: [100 v1] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		AERCap:	First Error Pointer: 1f, GenCap- CGenEn- ChkCap- ChkEn-
	Kernel driver in use: sky2

06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Panasonic CF-Y5 laptop
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 168
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at b8002000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=06, secondary=07, subordinate=07, sec-latency=176
	Memory window 0: 80000000-83fff000 (prefetchable)
	Memory window 1: 8c000000-8ffff000
	I/O window 0: 00004000-000040ff
	I/O window 1: 00004400-000044ff
	BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt- PostWrite+
	16-bit legacy interface ports at 0001
	Kernel driver in use: yenta_cardbus

06:01.1 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Panasonic CF-Y5 laptop
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 168
	Interrupt: pin B routed to IRQ 21
	Region 0: Memory at b8003000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=06, secondary=08, subordinate=0b, sec-latency=176
	Memory window 0: 84000000-87fff000 (prefetchable)
	Memory window 1: 90000000-93fff000
	I/O window 0: 00004800-000048ff
	I/O window 1: 00004c00-00004cff
	BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt- PostWrite+
	16-bit legacy interface ports at 0001
	Kernel driver in use: yenta_cardbus

06:01.2 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 11)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Panasonic CF-Y5 laptop
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32
	Interrupt: pin C routed to IRQ 19
	Region 0: Memory at b8000000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [80] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
	Kernel driver in use: sdhci-pci

06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection (rev 05)
	Subsystem: Intel Corporation Device 1000
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32 (750ns min, 6000ns max), Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at b8001000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
	Kernel driver in use: ipw2200

07:00.0 USB Controller: NEC Corporation USB (rev 43) (prog-if 10 [OHCI])
	Subsystem: Adaptec Device 1235
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64 (250ns min, 10500ns max)
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at 8c000000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ohci_hcd

07:00.1 USB Controller: NEC Corporation USB (rev 43) (prog-if 10 [OHCI])
	Subsystem: Adaptec Device 1235
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64 (250ns min, 10500ns max)
	Interrupt: pin B routed to IRQ 20
	Region 0: Memory at 8c001000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ohci_hcd

07:00.2 USB Controller: NEC Corporation USB 2.0 (rev 04) (prog-if 20 [EHCI])
	Subsystem: Adaptec Device 12e0
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 68 (4000ns min, 8500ns max), Cache Line Size: 32 bytes
	Interrupt: pin C routed to IRQ 20
	Region 0: Memory at 8c002000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ehci_hcd

08:00.0 Ethernet controller: Atheros Communications Inc. Atheros AR5001X+ Wireless Network Adapter (rev 01)
	Subsystem: Atheros Communications Inc. Ubiquiti Networks SuperRange a/b/g Cardbus Adapter
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 168 (2500ns min, 7000ns max), Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 21
	Region 0: Memory at 90000000 (32-bit, non-prefetchable) [size=64K]
	Capabilities: [44] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
	Kernel driver in use: ath5k

lspcmcia -v -v
Socket 0 Bridge:   	[yenta_cardbus] 	(bus ID: 0000:06:01.0)
	Configuration:	state: on	ready: yes
			Voltage: 3.3V Vcc: 3.3V Vpp: 3.3V
			Available IRQs: 3, 4, 7, 10, 11
			Available ioports:	0x00000100 - 0x000003af
						0x000003e0 - 0x000004cf
						0x000004d8 - 0x000004ff
						0x00000820 - 0x000008ff
						0x00000a00 - 0x00000aff
						0x00000c00 - 0x00000cf7
						0x00004000 - 0x00004fff
			Available iomem:	0x000c0000 - 0x000fffff
						0x60000000 - 0x60ffffff
						0x80000000 - 0x87ffffff
						0xa0000000 - 0xa0ffffff
						0xb8000000 - 0xb80fffff
  CardBus card -- see "lspci" for more information
Socket 1 Bridge:   	[yenta_cardbus] 	(bus ID: 0000:06:01.1)
	Configuration:	state: on	ready: yes
			Voltage: 3.3V Vcc: 3.3V Vpp: 3.3V
			Available IRQs: 3, 4, 7, 10, 11
			Available ioports:	0x00000100 - 0x000003af
						0x000003e0 - 0x000004cf
						0x000004d8 - 0x000004ff
						0x00000820 - 0x000008ff
						0x00000a00 - 0x00000aff
						0x00000c00 - 0x00000cf7
						0x00004000 - 0x00004fff
			Available iomem:	0x000c0000 - 0x000fffff
						0x60000000 - 0x60ffffff
						0x80000000 - 0x87ffffff
						0xa0000000 - 0xa0ffffff
						0xb8000000 - 0xb80fffff
  CardBus card -- see "lspci" for more information

[-- Attachment #3: CF-29_MK5_4.9.160.txt --]
[-- Type: text/plain, Size: 133996 bytes --]

Panasonic CF-29 MK5 - Top PCMCIA (CardBUS) slot does not work.
Top slot contains a Ubiquity SuperRange Cardbus WiFi card.
Bottom slot contains an Adaptec USB2connect 2 port USB card.

uname -a
Linux antix1 4.9.160-antix.2-486-smp #1 SMP Wed Feb 27 14:42:39 EET 2019 i686 GNU/Linux

dmesg
[    0.216496] pci 0000:00:1e.2: reg 0x18: [mem 0xb0040800-0xb00409ff]
[    0.216506] pci 0000:00:1e.2: reg 0x1c: [mem 0xb0040400-0xb00404ff]
[    0.216556] pci 0000:00:1e.2: PME# supported from D0 D3hot D3cold
[    0.216675] pci 0000:00:1e.3: [8086:266d] type 00 class 0x070300
[    0.216690] pci 0000:00:1e.3: reg 0x10: [io  0x2400-0x24ff]
[    0.216700] pci 0000:00:1e.3: reg 0x14: [io  0x2000-0x207f]
[    0.216764] pci 0000:00:1e.3: PME# supported from D0 D3hot D3cold
[    0.216877] pci 0000:00:1e.3: System wakeup disabled by ACPI
[    0.216957] pci 0000:00:1f.0: [8086:2641] type 00 class 0x060100
[    0.217048] pci 0000:00:1f.0: Force enabled HPET at 0xfed00000
[    0.217057] pci 0000:00:1f.0: quirk: [io  0x1000-0x107f] claimed by ICH6 ACPI/GPIO/TCO
[    0.217062] pci 0000:00:1f.0: quirk: [io  0x1180-0x11bf] claimed by ICH6 GPIO
[    0.217067] pci 0000:00:1f.0: LPC Generic IO decode 1 PIO at 0900-097f
[    0.217186] pci 0000:00:1f.2: [8086:2653] type 00 class 0x010180
[    0.217202] pci 0000:00:1f.2: reg 0x10: [io  0x0000-0x0007]
[    0.217211] pci 0000:00:1f.2: reg 0x14: [io  0x0000-0x0003]
[    0.217221] pci 0000:00:1f.2: reg 0x18: [io  0x0000-0x0007]
[    0.217230] pci 0000:00:1f.2: reg 0x1c: [io  0x0000-0x0003]
[    0.217239] pci 0000:00:1f.2: reg 0x20: [io  0x1890-0x189f]
[    0.217259] pci 0000:00:1f.2: legacy IDE quirk: reg 0x10: [io  0x01f0-0x01f7]
[    0.217261] pci 0000:00:1f.2: legacy IDE quirk: reg 0x14: [io  0x03f6]
[    0.217263] pci 0000:00:1f.2: legacy IDE quirk: reg 0x18: [io  0x0170-0x0177]
[    0.217266] pci 0000:00:1f.2: legacy IDE quirk: reg 0x1c: [io  0x0376]
[    0.217292] pci 0000:00:1f.2: PME# supported from D3hot
[    0.217411] pci 0000:00:1f.3: [8086:266a] type 00 class 0x0c0500
[    0.217467] pci 0000:00:1f.3: reg 0x20: [io  0x18a0-0x18bf]
[    0.217702] pci 0000:02:00.0: [11ab:4362] type 00 class 0x020000
[    0.217732] pci 0000:02:00.0: reg 0x10: [mem 0xb4000000-0xb4003fff 64bit]
[    0.217745] pci 0000:02:00.0: reg 0x18: [io  0x3000-0x30ff]
[    0.217793] pci 0000:02:00.0: reg 0x30: [mem 0x00000000-0x0001ffff pref]
[    0.217868] pci 0000:02:00.0: supports D1 D2
[    0.217871] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.217971] pci 0000:02:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
[    0.217983] pci 0000:00:1c.0: PCI bridge to [bus 02]
[    0.217988] pci 0000:00:1c.0:   bridge window [io  0x3000-0x3fff]
[    0.217993] pci 0000:00:1c.0:   bridge window [mem 0xb4000000-0xb7ffffff]
[    0.218005] pci 0000:00:1c.0:   bridge window [mem 0xd0000000-0xd3ffffff 64bit pref]
[    0.218080] pci 0000:06:01.0: [1180:0476] type 02 class 0x060700
[    0.218097] pci 0000:06:01.0: proprietary Ricoh MMC controller disabled (via cardbus function)
[    0.218099] pci 0000:06:01.0: MMC cards are now supported by standard SDHCI controller
[    0.218113] pci 0000:06:01.0: reg 0x10: [mem 0xb8000000-0xb8000fff]
[    0.218149] pci 0000:06:01.0: supports D1 D2
[    0.218151] pci 0000:06:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.218248] pci 0000:06:01.1: [1180:0822] type 00 class 0x080500
[    0.218267] pci 0000:06:01.1: reg 0x10: [mem 0xb8002000-0xb80020ff]
[    0.218355] pci 0000:06:01.1: supports D1 D2
[    0.218357] pci 0000:06:01.1: PME# supported from D0 D1 D2 D3hot D3cold
[    0.218455] pci 0000:06:02.0: [8086:4223] type 00 class 0x028000
[    0.218474] pci 0000:06:02.0: reg 0x10: [mem 0xb8003000-0xb8003fff]
[    0.218567] pci 0000:06:02.0: PME# supported from D0 D3hot D3cold
[    0.218680] pci 0000:00:1e.0: PCI bridge to [bus 06-08] (subtractive decode)
[    0.218687] pci 0000:00:1e.0:   bridge window [mem 0xb8000000-0xb80fffff]
[    0.218693] pci 0000:00:1e.0:   bridge window [io  0x0000-0xffff] (subtractive decode)
[    0.218696] pci 0000:00:1e.0:   bridge window [mem 0x00000000-0xffffffff] (subtractive decode)
[    0.218759] pci_bus 0000:07: busn_res: [bus 07-08] end is updated to 07
[    0.218776] pci_bus 0000:00: on NUMA node 0
[    0.222118] ACPI: PCI Interrupt Link [LNKA] (IRQs *9)
[    0.222207] ACPI: PCI Interrupt Link [LNKB] (IRQs *9)
[    0.222294] ACPI: PCI Interrupt Link [LNKC] (IRQs *9)
[    0.222380] ACPI: PCI Interrupt Link [LNKD] (IRQs *9)
[    0.222466] ACPI: PCI Interrupt Link [LNKE] (IRQs *9)
[    0.222552] ACPI: PCI Interrupt Link [LNKF] (IRQs *9)
[    0.222638] ACPI: PCI Interrupt Link [LNKG] (IRQs 9) *0, disabled.
[    0.222726] ACPI: PCI Interrupt Link [LNKH] (IRQs *9)
[    0.238131] ACPI: Enabled 2 GPEs in block 00 to 1F
[    0.238227] ACPI : EC: interrupt unblocked
[    0.238235] ACPI : EC: event unblocked
[    0.238242] ACPI: \_SB_.PCI0.LPCB.EC0_: GPE=0x1d, EC_CMD/EC_SC=0x66, EC_DATA=0x62
[    0.238244] ACPI: \_SB_.PCI0.LPCB.EC0_: Used as boot DSDT EC to handle transactions and events
[    0.238340] vgaarb: setting as boot device: PCI:0000:00:02.0
[    0.238343] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[    0.238347] vgaarb: loaded
[    0.238349] vgaarb: bridge control possible 0000:00:02.0
[    0.238496] SCSI subsystem initialized
[    0.238548] libata version 3.00 loaded.
[    0.238590] ACPI: bus type USB registered
[    0.238628] usbcore: registered new interface driver usbfs
[    0.238646] usbcore: registered new interface driver hub
[    0.238666] usbcore: registered new device driver usb
[    0.238790] PCI: Using ACPI for IRQ routing
[    0.245937] PCI: pci_cache_line_size set to 64 bytes
[    0.245989] e820: reserve RAM buffer [mem 0x0009f800-0x0009ffff]
[    0.245991] e820: reserve RAM buffer [mem 0x7f6e0000-0x7fffffff]
[    0.246186] NetLabel: Initializing
[    0.246188] NetLabel:  domain hash size = 128
[    0.246189] NetLabel:  protocols = UNLABELED CIPSOv4
[    0.246213] NetLabel:  unlabeled traffic allowed by default
[    0.246490] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484882848 ns
[    0.246497] hpet clockevent registered
[    0.246502] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
[    0.246507] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
[    0.246513] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
[    0.248064] clocksource: Switched to clocksource hpet
[    0.254603] VFS: Disk quotas dquot_6.6.0
[    0.254638] VFS: Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[    0.257645] pnp: PnP ACPI init
[    0.264407] system 00:00: [mem 0x000cf200-0x000cf7ff] has been reserved
[    0.264410] system 00:00: [mem 0x000d0800-0x000d3fff] has been reserved
[    0.264417] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.266049] system 00:01: [io  0x0900-0x091f] has been reserved
[    0.266052] system 00:01: [io  0x092c-0x097f] has been reserved
[    0.266055] system 00:01: [io  0xfe00-0xfe01] has been reserved
[    0.266058] system 00:01: [io  0x0920-0x092b] has been reserved
[    0.266062] system 00:01: [mem 0xfed40000-0xfed44fff] has been reserved
[    0.266066] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.275394] system 00:02: [io  0x02e0-0x02e7] has been reserved
[    0.275397] system 00:02: [io  0x0330-0x0337] has been reserved
[    0.275401] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.275617] system 00:03: [io  0x0800-0x080f] has been reserved
[    0.275620] system 00:03: [io  0x1000-0x107f] has been reserved
[    0.275623] system 00:03: [io  0x1180-0x11bf] has been reserved
[    0.275627] system 00:03: [mem 0xe0000000-0xefffffff] has been reserved
[    0.275630] system 00:03: [mem 0xf0000000-0xf0003fff] has been reserved
[    0.275633] system 00:03: [mem 0xf0004000-0xf0004fff] has been reserved
[    0.275636] system 00:03: [mem 0xf0005000-0xf0005fff] has been reserved
[    0.275639] system 00:03: [mem 0xf0008000-0xf000bfff] has been reserved
[    0.275642] system 00:03: [mem 0xfed20000-0xfed3ffff] has been reserved
[    0.275645] system 00:03: [mem 0xfed45000-0xfed8ffff] has been reserved
[    0.275650] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.275760] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.276668] pnp 00:05: Plug and Play ACPI device, IDs PNP0303 (active)
[    0.278125] pnp 00:06: Plug and Play ACPI device, IDs FJC6001 PNP0f13 (active)
[    0.287579] pnp 00:07: Plug and Play ACPI device, IDs PNP0501 (active)
[    0.320615] pnp 00:08: [dma 1]
[    0.320650] pnp 00:08: Plug and Play ACPI device, IDs PNP0401 (active)
[    0.325057] pnp: PnP ACPI: found 9 devices
[    0.359630] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[    0.359667] pci 0000:06:01.0: res[13]=[io  0x0100-0x00ff] res_to_dev_res add_size 100 min_align 100
[    0.359671] pci 0000:06:01.0: res[14]=[io  0x0100-0x00ff] res_to_dev_res add_size 100 min_align 100
[    0.359675] pci 0000:00:1e.0: bridge window [io  0x1000-0x0fff] to [bus 06-08] add_size 1000
[    0.359684] pci 0000:00:1e.0: res[13]=[io  0x1000-0x0fff] res_to_dev_res add_size 1000 min_align 1000
[    0.359687] pci 0000:00:1e.0: res[13]=[io  0x1000-0x1fff] res_to_dev_res add_size 1000 min_align 1000
[    0.359696] pci 0000:00:02.1: BAR 0: assigned [mem 0x80000000-0x8007ffff]
[    0.359703] pci 0000:00:1e.0: BAR 13: assigned [io  0x4000-0x4fff]
[    0.359708] pci 0000:02:00.0: BAR 6: assigned [mem 0xb4020000-0xb403ffff pref]
[    0.359712] pci 0000:00:1c.0: PCI bridge to [bus 02]
[    0.359716] pci 0000:00:1c.0:   bridge window [io  0x3000-0x3fff]
[    0.359722] pci 0000:00:1c.0:   bridge window [mem 0xb4000000-0xb7ffffff]
[    0.359727] pci 0000:00:1c.0:   bridge window [mem 0xd0000000-0xd3ffffff 64bit pref]
[    0.359737] pci 0000:06:01.0: res[15]=[mem 0x04000000-0x03ffffff pref] res_to_dev_res add_size 4000000 min_align 4000000
[    0.359741] pci 0000:06:01.0: res[15]=[mem 0x04000000-0x07ffffff pref] res_to_dev_res add_size 4000000 min_align 4000000
[    0.359744] pci 0000:06:01.0: res[16]=[mem 0x04000000-0x03ffffff] res_to_dev_res add_size 4000000 min_align 4000000
[    0.359747] pci 0000:06:01.0: res[16]=[mem 0x04000000-0x07ffffff] res_to_dev_res add_size 4000000 min_align 4000000
[    0.359750] pci 0000:06:01.0: res[13]=[io  0x0100-0x00ff] res_to_dev_res add_size 100 min_align 100
[    0.359753] pci 0000:06:01.0: res[13]=[io  0x0100-0x01ff] res_to_dev_res add_size 100 min_align 100
[    0.359756] pci 0000:06:01.0: res[14]=[io  0x0100-0x00ff] res_to_dev_res add_size 100 min_align 100
[    0.359760] pci 0000:06:01.0: res[14]=[io  0x0100-0x01ff] res_to_dev_res add_size 100 min_align 100
[    0.359764] pci 0000:06:01.0: BAR 15: assigned [mem 0x84000000-0x87ffffff pref]
[    0.359768] pci 0000:06:01.0: BAR 16: assigned [mem 0x88000000-0x8bffffff]
[    0.359771] pci 0000:06:01.0: BAR 13: assigned [io  0x4000-0x40ff]
[    0.359774] pci 0000:06:01.0: BAR 14: assigned [io  0x4400-0x44ff]
[    0.359777] pci 0000:06:01.0: CardBus bridge to [bus 07]
[    0.359780] pci 0000:06:01.0:   bridge window [io  0x4000-0x40ff]
[    0.359785] pci 0000:06:01.0:   bridge window [io  0x4400-0x44ff]
[    0.359790] pci 0000:06:01.0:   bridge window [mem 0x84000000-0x87ffffff pref]
[    0.359795] pci 0000:06:01.0:   bridge window [mem 0x88000000-0x8bffffff]
[    0.359800] pci 0000:00:1e.0: PCI bridge to [bus 06-08]
[    0.359803] pci 0000:00:1e.0:   bridge window [io  0x4000-0x4fff]
[    0.359809] pci 0000:00:1e.0:   bridge window [mem 0xb8000000-0xb80fffff]
[    0.359819] pci_bus 0000:00: resource 4 [io  0x0000-0xffff]
[    0.359821] pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
[    0.359824] pci_bus 0000:02: resource 0 [io  0x3000-0x3fff]
[    0.359827] pci_bus 0000:02: resource 1 [mem 0xb4000000-0xb7ffffff]
[    0.359829] pci_bus 0000:02: resource 2 [mem 0xd0000000-0xd3ffffff 64bit pref]
[    0.359832] pci_bus 0000:06: resource 0 [io  0x4000-0x4fff]
[    0.359835] pci_bus 0000:06: resource 1 [mem 0xb8000000-0xb80fffff]
[    0.359837] pci_bus 0000:06: resource 4 [io  0x0000-0xffff]
[    0.359840] pci_bus 0000:06: resource 5 [mem 0x00000000-0xffffffff]
[    0.359843] pci_bus 0000:07: resource 0 [io  0x4000-0x40ff]
[    0.359845] pci_bus 0000:07: resource 1 [io  0x4400-0x44ff]
[    0.359848] pci_bus 0000:07: resource 2 [mem 0x84000000-0x87ffffff pref]
[    0.359850] pci_bus 0000:07: resource 3 [mem 0x88000000-0x8bffffff]
[    0.359972] NET: Registered protocol family 2
[    0.360333] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.360368] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.360433] TCP: Hash tables configured (established 8192 bind 8192)
[    0.360506] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.360524] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.360602] NET: Registered protocol family 1
[    0.360628] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[    0.361398] PCI: CLS 32 bytes, default 64
[    0.361499] Trying to unpack rootfs image as initramfs...
[    1.057157] Freeing initrd memory: 23092K
[    1.057615] simple-framebuffer simple-framebuffer.0: framebuffer at 0xc0000000, 0x180000 bytes, mapped to 0xf8200000
[    1.057621] simple-framebuffer simple-framebuffer.0: format=r5g6b5, mode=1024x768x16, linelength=2048
[    1.078097] Console: switching to colour frame buffer device 128x48
[    1.098368] simple-framebuffer simple-framebuffer.0: fb0: simplefb registered!
[    1.098766] audit: initializing netlink subsys (disabled)
[    1.098804] audit: type=2000 audit(1571240824.097:1): initialized
[    1.099170] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    1.102973] zbud: loaded
[    1.103659] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.103815] ntfs: driver 2.1.32 [Flags: R/W].
[    1.103932] fuse init (API version 7.26)
[    1.104720] bounce: pool size: 64 pages
[    1.104798] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[    1.104847] io scheduler noop registered
[    1.104849] io scheduler deadline registered
[    1.104913] io scheduler cfq registered (default)
[    1.105591] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[    1.105601] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[    1.105748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    1.126461] 00:07: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
[    1.127428] Linux agpgart interface v0.103
[    1.127456] intel_idle: does not run on family 6 model 13
[    1.127581] tsc: Marking TSC unstable due to TSC halts in idle
[    1.127752] GHES: HEST is not enabled!
[    1.133308] brd: module loaded
[    1.135904] loop: module loaded
[    1.136129] ahci 0000:00:1f.2: version 3.0
[    1.136291] ahci 0000:00:1f.2: controller is in combined mode, can't enable AHCI mode
[    1.136559] ata_piix 0000:00:1f.2: version 2.13
[    1.136652] ata_piix 0000:00:1f.2: MAP [ P0 P2 IDE IDE ]
[    1.138172] scsi host0: ata_piix
[    1.138328] scsi host1: ata_piix
[    1.138405] ata1: SATA max UDMA/133 cmd 0x1f0 ctl 0x3f6 bmdma 0x1890 irq 14
[    1.138407] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x1898 irq 15
[    1.139052] libphy: Fixed MDIO Bus: probed
[    1.139097] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    1.139098] ehci-pci: EHCI PCI platform driver
[    1.139255] ehci-pci 0000:00:1d.7: EHCI Host Controller
[    1.139266] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 1
[    1.139282] ehci-pci 0000:00:1d.7: debug port 1
[    1.143204] ehci-pci 0000:00:1d.7: cache line size of 32 is not supported
[    1.143475] ehci-pci 0000:00:1d.7: irq 23, io mem 0xb0040000
[    1.150018] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00
[    1.150080] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    1.150083] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.150086] usb usb1: Product: EHCI Host Controller
[    1.150088] usb usb1: Manufacturer: Linux 4.9.160-antix.2-486-smp ehci_hcd
[    1.150091] usb usb1: SerialNumber: 0000:00:1d.7
[    1.150313] hub 1-0:1.0: USB hub found
[    1.150324] hub 1-0:1.0: 6 ports detected
[    1.150583] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    1.150590] ohci-pci: OHCI PCI platform driver
[    1.150609] ohci-platform: OHCI generic platform driver
[    1.150623] uhci_hcd: USB Universal Host Controller Interface driver
[    1.150737] uhci_hcd 0000:00:1d.0: UHCI Host Controller
[    1.150750] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
[    1.150776] uhci_hcd 0000:00:1d.0: irq 23, io base 0x00001820
[    1.150845] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
[    1.150848] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.150850] usb usb2: Product: UHCI Host Controller
[    1.150853] usb usb2: Manufacturer: Linux 4.9.160-antix.2-486-smp uhci_hcd
[    1.150855] usb usb2: SerialNumber: 0000:00:1d.0
[    1.151058] hub 2-0:1.0: USB hub found
[    1.151069] hub 2-0:1.0: 2 ports detected
[    1.151284] uhci_hcd 0000:00:1d.1: UHCI Host Controller
[    1.151291] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3
[    1.151326] uhci_hcd 0000:00:1d.1: irq 19, io base 0x00001840
[    1.151390] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
[    1.151393] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.151396] usb usb3: Product: UHCI Host Controller
[    1.151398] usb usb3: Manufacturer: Linux 4.9.160-antix.2-486-smp uhci_hcd
[    1.151400] usb usb3: SerialNumber: 0000:00:1d.1
[    1.151567] hub 3-0:1.0: USB hub found
[    1.151576] hub 3-0:1.0: 2 ports detected
[    1.151808] uhci_hcd 0000:00:1d.2: UHCI Host Controller
[    1.151815] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4
[    1.151848] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001860
[    1.151913] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
[    1.151916] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.151918] usb usb4: Product: UHCI Host Controller
[    1.151920] usb usb4: Manufacturer: Linux 4.9.160-antix.2-486-smp uhci_hcd
[    1.151922] usb usb4: SerialNumber: 0000:00:1d.2
[    1.152111] hub 4-0:1.0: USB hub found
[    1.152120] hub 4-0:1.0: 2 ports detected
[    1.152367] i8042: PNP: PS/2 Controller [PNP0303:K101,FJC6001:MOU1] at 0x60,0x64 irq 1,12
[    1.154249] serio: i8042 KBD port at 0x60,0x64 irq 1
[    1.154256] serio: i8042 AUX port at 0x60,0x64 irq 12
[    1.154469] mousedev: PS/2 mouse device common for all mice
[    1.154550] ledtrig-cpu: registered to indicate activity on CPUs
[    1.154576] hidraw: raw HID events driver (C) Jiri Kosina
[    1.154774] usbcore: registered new interface driver usbhid
[    1.154775] usbhid: USB HID core driver
[    1.154995] Key type dns_resolver registered
[    1.155278] microcode: sig=0x6d8, pf=0x20, revision=0x20
[    1.155323] microcode: Microcode Update Driver: v2.01 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[    1.155328] Using IPI No-Shortcut mode
[    1.155509] registered taskstats version 1
[    1.155531] zswap: loaded using pool lzo/zbud
[    1.159922] Key type encrypted registered
[    1.159927] evm: HMAC attrs: 0x1
[    1.160412] hd: no drives specified - use hd=cyl,head,sectors on kernel command line
[    1.185718] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0
[    1.299089] ata2.00: ATAPI: UJDA760 DVD/CDRW, 1.00, max UDMA/33
[    1.299180] ata1.00: ATA-8: SAMSUNG SSD PM830 mSATA 32GB, CXM12D1Q, max UDMA/133
[    1.299183] ata1.00: 62533296 sectors, multi 16: LBA48 
[    1.302195] ata2.00: configured for UDMA/33
[    1.302255] ata1.00: configured for UDMA/133
[    1.302469] scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SSD PM83 2D1Q PQ: 0 ANSI: 5
[    1.302783] sd 0:0:0:0: Attached scsi generic sg0 type 0
[    1.302914] sd 0:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
[    1.303022] sd 0:0:0:0: [sda] Write Protect is off
[    1.303026] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[    1.303058] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[    1.304112]  sda: sda1 sda2 sda3
[    1.304746] sd 0:0:0:0: [sda] Attached SCSI disk
[    1.305046] scsi 1:0:0:0: CD-ROM            MATSHITA UJDA760 DVD/CDRW 1.00 PQ: 0 ANSI: 5
[    1.328224] sr 1:0:0:0: [sr0] scsi3-mmc drive: 24x/24x writer cd/rw xa/form2 cdda tray
[    1.328226] cdrom: Uniform CD-ROM driver Revision: 3.20
[    1.328417] sr 1:0:0:0: Attached scsi CD-ROM sr0
[    1.328575] sr 1:0:0:0: Attached scsi generic sg1 type 5
[    1.328993] Freeing unused kernel memory: 644K
[    1.329098] Write protecting the kernel text: 6808k
[    1.329159] Write protecting the kernel read-only data: 2032k
[    1.485972] udevd[107]: starting version 3.2.7
[    1.486474] random: udevd: uninitialized urandom read (16 bytes read)
[    1.486526] random: udevd: uninitialized urandom read (16 bytes read)
[    1.488147] udevd[108]: starting eudev-3.2.7
[    1.509833] FUJITSU Extended Socket Network Device Driver - version 1.1 - Copyright (c) 2015 FUJITSU LIMITED
[    1.521429] rtc_cmos 00:04: RTC can wake from S4
[    1.521629] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0
[    1.521665] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
[    1.533442] sky2: driver version 1.30
[    1.533639] sky2 0000:02:00.0: Yukon-2 EC chip revision 1
[    1.534101] sky2 0000:02:00.0 eth0: addr 00:0b:97:96:26:50
[    1.542975] sdhci: Secure Digital Host Controller Interface driver
[    1.542977] sdhci: Copyright(c) Pierre Ossman
[    1.543652] sdhci-pci 0000:06:01.1: SDHCI controller found [1180:0822] (rev 11)
[    1.545554] sdhci-pci 0000:06:01.1: Will use DMA mode even though HW doesn't fully claim to support it.
[    1.546565] sdhci-pci 0000:06:01.1: Will use DMA mode even though HW doesn't fully claim to support it.
[    1.549198] thermal LNXTHERM:00: registered as thermal_zone0
[    1.549200] ACPI: Thermal Zone [TZC] (36 C)
[    1.555005] sdhci-pci 0000:06:01.1: Will use DMA mode even though HW doesn't fully claim to support it.
[    1.558485] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt
[    1.558698] mmc0: SDHCI controller on PCI [0000:06:01.1] using DMA
[    1.612032] random: fast init done
[    1.706009] raid6: mmxx1    gen()  1777 MB/s
[    1.723009] raid6: mmxx2    gen()  1980 MB/s
[    1.740056] raid6: sse1x1   gen()  1210 MB/s
[    1.757012] raid6: sse1x2   gen()  1984 MB/s
[    1.774032] raid6: sse2x1   gen()  2171 MB/s
[    1.791010] raid6: sse2x1   xor()  1412 MB/s
[    1.808009] raid6: sse2x2   gen()  2406 MB/s
[    1.825027] raid6: sse2x2   xor()  1500 MB/s
[    1.825028] raid6: using algorithm sse2x2 gen() 2406 MB/s
[    1.825029] raid6: .... xor() 1500 MB/s, rmw enabled
[    1.825031] raid6: using intx1 recovery algorithm
[    1.825411] xor: measuring software checksum speed
[    1.835007]    pIII_sse  :  4180.000 MB/sec
[    1.845006]    prefetch64-sse:  4552.000 MB/sec
[    1.845008] xor: using function: prefetch64-sse (4552.000 MB/sec)
[    1.855720] Btrfs loaded, crc32c=crc32c-generic, assert=on
[    1.970335] input: LBPS/2 Fujitsu Lifebook Touchpad as /devices/platform/i8042/serio1/input/input3
[    1.977510] PM: Starting manual resume from disk
[    2.080029] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x1701ea41ceb, max_idle_ns: 440795212314 ns
[    2.132754] EXT4-fs (sda2): mounting ext3 file system using the ext4 subsystem
[    2.144970] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[    2.185315] input: LBPS/2 Fujitsu Lifebook TouchScreen as /devices/platform/i8042/serio1/input/input2
[    2.527163] udevd[337]: starting version 3.2.7
[    2.541053] ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6
[    2.541306] ata1.00: BMDMA stat 0x24
[    2.541448] ata1.00: failed command: READ DMA
[    2.541623] ata1.00: cmd c8/00:80:48:71:71/00:00:00:00:00/e0 tag 0 dma 65536 in
                        res 51/84:00:c7:71:71/00:00:00:00:00/e0 Emask 0x10 (ATA bus error)
[    2.542210] ata1.00: status: { DRDY ERR }
[    2.542365] ata1.00: error: { ICRC ABRT }
[    2.542531] ata1: soft resetting link
[    2.701229] ata1.00: configured for UDMA/133
[    2.701246] ata1: EH complete
[    2.717034] random: udevd: uninitialized urandom read (16 bytes read)
[    2.717397] random: udevd: uninitialized urandom read (16 bytes read)
[    2.717805] random: udevd: uninitialized urandom read (16 bytes read)
[    2.722996] udevd[337]: specified group 'kvm' unknown
[    2.761614] udevd[337]: starting eudev-3.2.7
[    2.799360] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input4
[    2.809445] ACPI: Lid Switch [LID]
[    2.812344] ACPI: AC Adapter [AC] (on-line)
[    2.812540] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input5
[    2.812546] ACPI: Power Button [PWRB]
[    2.812679] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input6
[    2.812682] ACPI: Power Button [PWRF]
[    2.825652] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
[    2.826687] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input7
[    2.827514] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[    2.876172] parport_pc 00:08: reported by Plug and Play ACPI
[    2.876249] parport0: PC-style at 0x378 (0x778), irq 5, dma 1 [PCSPP,TRISTATE,COMPAT,EPP,ECP,DMA]
[    2.879525] [drm] Initialized
[    2.906465] ACPI: Battery Slot [BATA] (battery present)
[    2.909822] ACPI: Battery Slot [BATB] (battery absent)
[    2.910142] input: Panasonic Laptop Support as /devices/virtual/input/input8
[    2.953934] yenta_cardbus 0000:06:01.0: CardBus bridge found [10f7:8338]
[    3.003276] intel_rng: FWH not detected
[    3.050868] lib80211: common routines for IEEE802.11 drivers
[    3.050872] lib80211_crypt: registered algorithm 'NULL'
[    3.052571] libipw: 802.11 data/management/control stack, git-1.1.13
[    3.052572] libipw: Copyright (C) 2004-2005 Intel Corporation <jketreno@linux.intel.com>
[    3.057368] ipw2200: Intel(R) PRO/Wireless 2200/2915 Network Driver, 1.2.2kmprq
[    3.057369] ipw2200: Copyright(c) 2003-2006 Intel Corporation
[    3.080717] yenta_cardbus 0000:06:01.0: ISA IRQ mask 0x0c98, PCI irq 20
[    3.080722] yenta_cardbus 0000:06:01.0: Socket status: 30000820
[    3.080731] yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge window: [io  0x4000-0x4fff]
[    3.080734] yenta_cardbus 0000:06:01.0: pcmcia: parent PCI bridge window: [mem 0xb8000000-0xb80fffff]
[    3.080738] pcmcia_socket pcmcia_socket0: cs: memory probe 0xb8000000-0xb80fffff:
[    3.080743]  excluding 0xb8000000-0xb800ffff
[    3.089786] ipw2200: Detected Intel PRO/Wireless 2915ABG Network Connection
[    3.431515] ipw2200: Detected geography ZZA (11 802.11bg channels, 13 802.11a channels)
[    3.465049] ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6
[    3.465316] ata1.00: BMDMA stat 0x24
[    3.465458] ata1.00: failed command: READ DMA
[    3.465656] ata1.00: cmd c8/00:00:00:63:6d/00:00:00:00:00/e0 tag 0 dma 131072 in
                        res 51/84:00:ff:63:6d/00:00:00:00:00/e0 Emask 0x10 (ATA bus error)
[    3.466247] ata1.00: status: { DRDY ERR }
[    3.466403] ata1.00: error: { ICRC ABRT }
[    3.466569] ata1: soft resetting link
[    3.629226] ata1.00: configured for UDMA/133
[    3.629247] ata1: EH complete
[    3.641050] ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6
[    3.641314] ata1.00: BMDMA stat 0x24
[    3.641456] ata1.00: failed command: READ DMA
[    3.641631] ata1.00: cmd c8/00:00:00:63:6d/00:00:00:00:00/e0 tag 0 dma 131072 in
                        res 51/84:00:ff:63:6d/00:00:00:00:00/e0 Emask 0x10 (ATA bus error)
[    3.642222] ata1.00: status: { DRDY ERR }
[    3.642399] ata1.00: error: { ICRC ABRT }
[    3.642566] ata1: soft resetting link
[    3.805269] ata1.00: configured for UDMA/133
[    3.805288] ata1: EH complete
[    3.810038] snd_intel8x0 0000:00:1e.2: intel8x0_measure_ac97_clock: measured 51252 usecs (2470 samples)
[    3.810042] snd_intel8x0 0000:00:1e.2: clocking to 48000
[    3.815167] pci 0000:00:00.0: Intel 915GM Chipset
[    3.815226] pci 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable
[    3.815929] pci 0000:00:00.0: detected 8192K stolen memory
[    3.816238] [drm] Memory usable by graphics device = 256M
[    3.816247] checking generic (c0000000 180000) vs hw (c0000000 10000000)
[    3.816249] fb: switching to inteldrmfb from simple
[    3.816352] Console: switching to colour dummy device 80x25
[    3.816766] [drm] Replacing VGA console driver
[    3.817606] ata1.00: limiting speed to UDMA/100:PIO4
[    3.817615] ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6
[    3.817638] ata1.00: BMDMA stat 0x24
[    3.817655] ata1.00: failed command: READ DMA
[    3.817683] ata1.00: cmd c8/00:00:00:63:6d/00:00:00:00:00/e0 tag 0 dma 131072 in
                        res 51/84:00:ff:63:6d/00:00:00:00:00/e0 Emask 0x10 (ATA bus error)
[    3.817723] ata1.00: status: { DRDY ERR }
[    3.817737] ata1.00: error: { ICRC ABRT }
[    3.817764] ata1: soft resetting link
[    3.817893] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.817896] [drm] Driver supports precise vblank timestamp query.
[    3.818685] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    3.854502] [drm] RC6 disabled, disabling runtime PM support
[    3.854547] [drm] initialized overlay support
[    3.856669] [drm] Initialized i915 1.6.0 20160919 for 0000:00:02.0 on minor 0
[    3.860647] ------------[ cut here ]------------
[    3.860778] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:12927 intel_atomic_check+0xcaa/0x1130 [i915]
[    3.860780] WARN_ON(!connector_state->crtc)
[    3.860782] Modules linked in:
[    3.860784]  evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    3.860852] CPU: 0 PID: 6 Comm: kworker/u4:0 Not tainted 4.9.160-antix.2-486-smp #1
[    3.860854] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    3.860862] Workqueue: events_unbound async_run_entry_fn
[    3.860865]  0000327f c1360ff2 f48c9c38 00000000 c1052c52 f8be1828 f48c9c50 00000006
[    3.860873]  f8bcfb24 0000327f f8b6daea f8b6daea 00000009 00000000 f49f7d80 f4a5b800
[    3.860881]  f6123c00 c1052cab 00000009 00000000 f48c9c38 f8be1828 f48c9c50 f8b6daea
[    3.860889] Call Trace:
[    3.860899]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    3.860903]  [<c1052c52>] ? __warn+0xe2/0x100
[    3.860980]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    3.861031]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    3.861031]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    3.861031]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    3.861031]  [<f87b4f44>] ? drm_atomic_check_only+0x324/0x6b0 [drm]
[    3.861031]  [<c113ea93>] ? kmemdup+0x23/0x30
[    3.861031]  [<f87b52de>] ? drm_atomic_commit+0xe/0x50 [drm]
[    3.861031]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    3.861031]  [<f8b8ba54>] ? intel_crt_detect+0x234/0x940 [i915]
[    3.861031]  [<f87ab194>] ? drm_mode_debug_printmodeline+0x84/0x90 [drm]
[    3.861031]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    3.861031]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    3.861031]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    3.861031]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.861031]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.861031]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.861031]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.861031]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.861031]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.861031]  [<c101866f>] ? __switch_to+0xef/0x380
[    3.861031]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    3.861031]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    3.861031]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    3.861031]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    3.861031]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    3.861031]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    3.861031]  [<c106e644>] ? kthread+0xa4/0xc0
[    3.861031]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.861031]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    3.861031]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    3.861595] ---[ end trace e96a1a7a1ce213df ]---
[    3.864512] ------------[ cut here ]------------
[    3.864598] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13556 intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    3.864600] encoder's enabled state mismatch (expected 0, found 1)
[    3.864602] Modules linked in: evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    3.864659] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    3.864661] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    3.864666] Workqueue: events_unbound async_run_entry_fn
[    3.864669]  000034f4 c1360ff2 f48c9c20 00000000 c1052c52 f8bd314c f48c9c38 00000006
[    3.864675]  f8bcfb24 000034f4 f8b6c380 f8b6c380 00000009 00000001 f49f7d80 f6140224
[    3.864682]  f6140000 c1052cab 00000009 00000000 f48c9c20 f8bd314c f48c9c38 f8b6c380
[    3.864689] Call Trace:
[    3.864696]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    3.864699]  [<c1052c52>] ? __warn+0xe2/0x100
[    3.864764]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    3.864828]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    3.864831]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    3.864895]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    3.864904]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    3.864912]  [<f885e324>] ? drm_atomic_helper_prepare_planes+0x54/0x110 [drm_kms_helper]
[    3.864976]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    3.865041]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    3.865056]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    3.865121]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    3.865187]  [<f8b8ba54>] ? intel_crt_detect+0x234/0x940 [i915]
[    3.865201]  [<f87ab194>] ? drm_mode_debug_printmodeline+0x84/0x90 [drm]
[    3.865208]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    3.865215]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    3.865221]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    3.865225]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.865227]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.865230]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.865232]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.865235]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.865237]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.865242]  [<c101866f>] ? __switch_to+0xef/0x380
[    3.865306]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    3.865369]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    3.865372]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    3.865375]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    3.865378]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    3.865381]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    3.865385]  [<c106e644>] ? kthread+0xa4/0xc0
[    3.865387]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.865391]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    3.865393]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    3.865420] ---[ end trace e96a1a7a1ce213e0 ]---
[    3.865423] ------------[ cut here ]------------
[    3.865488] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13564 intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    3.865490] encoder detached but still enabled on pipe B.
[    3.865490] Modules linked in: evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    3.865538] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    3.865540] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    3.865543] Workqueue: events_unbound async_run_entry_fn
[    3.865544]  000034fc c1360ff2 f48c9c20 00000000 c1052c52 f8bd3188 f48c9c38 00000006
[    3.865551]  f8bcfb24 000034fc f8b6c474 f8b6c474 00000009 00000001 f49f7d80 f6140224
[    3.865558]  f6140000 c1052cab 00000009 00000000 f48c9c20 f8bd3188 f48c9c38 f8b6c474
[    3.865564] Call Trace:
[    3.865568]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    3.865571]  [<c1052c52>] ? __warn+0xe2/0x100
[    3.865636]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    3.865699]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    3.865702]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    3.865766]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    3.865774]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    3.865838]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    3.865903]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    3.865917]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    3.865981]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    3.866047]  [<f8b8ba54>] ? intel_crt_detect+0x234/0x940 [i915]
[    3.866061]  [<f87ab194>] ? drm_mode_debug_printmodeline+0x84/0x90 [drm]
[    3.866068]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    3.866075]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    3.866081]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    3.866084]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.866087]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.866089]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.866092]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.866094]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.866097]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.866100]  [<c101866f>] ? __switch_to+0xef/0x380
[    3.866164]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    3.866227]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    3.866230]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    3.866233]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    3.866236]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    3.866239]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    3.866242]  [<c106e644>] ? kthread+0xa4/0xc0
[    3.866245]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.866248]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    3.866251]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    3.866260] ---[ end trace e96a1a7a1ce213e1 ]---
[    3.866264] ------------[ cut here ]------------
[    3.866329] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:6952 verify_connector_state+0x269/0x320 [i915]
[    3.866330] connector enabled without attached crtc
[    3.866331] Modules linked in: evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    3.866379] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    3.866380] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    3.866383] Workqueue: events_unbound async_run_entry_fn
[    3.866385]  00001b28 c1360ff2 f48c9bec 00000000 c1052c52 f8bd2000 f48c9c04 00000006
[    3.866391]  f8bcfb24 00001b28 f8b62819 f8b62819 00000009 f6123c00 f66c3c00 f6140224
[    3.866398]  00000000 c1052cab 00000009 00000000 f48c9bec f8bd2000 f48c9c04 f8b62819
[    3.866405] Call Trace:
[    3.866409]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    3.866411]  [<c1052c52>] ? __warn+0xe2/0x100
[    3.866475]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    3.866539]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    3.866542]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    3.866606]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    3.866668]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    3.866732]  [<f8b6c119>] ? intel_atomic_commit_tail+0xbb9/0xf60 [i915]
[    3.866740]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    3.866805]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    3.866869]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    3.866883]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    3.866947]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    3.867013]  [<f8b8ba54>] ? intel_crt_detect+0x234/0x940 [i915]
[    3.867027]  [<f87ab194>] ? drm_mode_debug_printmodeline+0x84/0x90 [drm]
[    3.867035]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    3.867042]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    3.867048]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    3.867050]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.867053]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.867055]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.867058]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.867061]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.867063]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.867066]  [<c101866f>] ? __switch_to+0xef/0x380
[    3.867130]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    3.867193]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    3.867196]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    3.867199]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    3.867202]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    3.867205]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    3.867208]  [<c106e644>] ? kthread+0xa4/0xc0
[    3.867211]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.867214]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    3.867217]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    3.867226] ---[ end trace e96a1a7a1ce213e2 ]---
[    3.964113] ------------[ cut here ]------------
[    3.964269] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:12927 intel_atomic_check+0xcaa/0x1130 [i915]
[    3.964272] WARN_ON(!connector_state->crtc)
[    3.964275] Modules linked in:
[    3.964277]  evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    3.964388] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    3.964391] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    3.964398] Workqueue: events_unbound async_run_entry_fn
[    3.964403]  0000327f c1360ff2 f48c9cdc 00000000 c1052c52 f8be1828 f48c9cf4 00000006
[    3.964419]  f8bcfb24 0000327f f8b6daea f8b6daea 00000009 00000000 f49f7d80 f4a5c000
[    3.964435]  f6123c00 c1052cab 00000009 00000000 f48c9cdc f8be1828 f48c9cf4 f8b6daea
[    3.964450] Call Trace:
[    3.964460]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    3.964466]  [<c1052c52>] ? __warn+0xe2/0x100
[    3.964618]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    3.964767]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    3.964775]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    3.964925]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    3.964936]  [<c10b5059>] ? del_timer_sync+0x39/0x40
[    3.964945]  [<c16a1c8a>] ? schedule_timeout+0x1aa/0x4a0
[    3.964978]  [<f87b4f44>] ? drm_atomic_check_only+0x324/0x6b0 [drm]
[    3.965009]  [<f87b52de>] ? drm_atomic_commit+0xe/0x50 [drm]
[    3.965061]  [<f8b8b686>] ? intel_crt_get_edid+0x66/0x70 [i915]
[    3.965061]  [<f8b45470>] ? gen2_write16+0x120/0x120 [i915]
[    3.965061]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    3.965061]  [<f8b8bc9f>] ? intel_crt_detect+0x47f/0x940 [i915]
[    3.965061]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    3.965061]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    3.965061]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    3.965061]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.965061]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.965061]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.965061]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.965061]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.965061]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    3.965061]  [<c101866f>] ? __switch_to+0xef/0x380
[    3.965061]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    3.965061]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    3.965061]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    3.965061]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    3.965061]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    3.965061]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    3.965061]  [<c106e644>] ? kthread+0xa4/0xc0
[    3.965061]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    3.965061]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    3.965061]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    3.966077] ---[ end trace e96a1a7a1ce213e3 ]---
[    3.976054] pcmcia_socket pcmcia_socket0: pccard: CardBus card inserted into slot 0
[    3.976092] pci 0000:07:00.0: [1033:0035] type 00 class 0x0c0310
[    3.976126] pci 0000:07:00.0: reg 0x10: [mem 0x00000000-0x00000fff]
[    3.976279] pci 0000:07:00.0: supports D1 D2
[    3.976286] pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot
[    3.976586] pci 0000:07:00.1: [1033:0035] type 00 class 0x0c0310
[    3.976616] pci 0000:07:00.1: reg 0x10: [mem 0x00000000-0x00000fff]
[    3.976748] pci 0000:07:00.1: supports D1 D2
[    3.976755] pci 0000:07:00.1: PME# supported from D0 D1 D2 D3hot
[    3.976997] pci 0000:07:00.2: [1033:00e0] type 00 class 0x0c0320
[    3.977045] pci 0000:07:00.2: reg 0x10: [mem 0x00000000-0x000000ff]
[    3.977177] pci 0000:07:00.2: supports D1 D2
[    3.977184] pci 0000:07:00.2: PME# supported from D0 D1 D2 D3hot
[    3.977422] pci 0000:07:00.0: BAR 0: assigned [mem 0x88000000-0x88000fff]
[    3.977435] pci 0000:07:00.1: BAR 0: assigned [mem 0x88001000-0x88001fff]
[    3.977447] pci 0000:07:00.2: BAR 0: assigned [mem 0x88002000-0x880020ff]
[    3.977506] pci 0000:07:00.0: enabling device (0000 -> 0002)
[    3.979617] ohci-pci 0000:07:00.0: OHCI PCI host controller
[    3.979636] ohci-pci 0000:07:00.0: new USB bus registered, assigned bus number 5
[    3.979688] ohci-pci 0000:07:00.0: irq 20, io mem 0x88000000
[    3.981961] ata1.00: configured for UDMA/100
[    3.981986] ata1: EH complete
[    3.991648] ppdev: user-space parallel port driver
[    4.004059] ------------[ cut here ]------------
[    4.004194] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13556 intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.004196] encoder's enabled state mismatch (expected 0, found 1)
[    4.004198] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.004263] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.004265] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.004273] Workqueue: events_unbound async_run_entry_fn
[    4.004276]  000034f4 c1360ff2 f48c9cc4 00000000 c1052c52 f8bd314c f48c9cdc 00000006
[    4.004283]  f8bcfb24 000034f4 f8b6c380 f8b6c380 00000009 00000001 f49f7d80 f6140224
[    4.004290]  f6140000 c1052cab 00000009 00000000 f48c9cc4 f8bd314c f48c9cdc f8b6c380
[    4.004297] Call Trace:
[    4.004306]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.004310]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.004376]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.004440]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.004443]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.004508]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.004519]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.004527]  [<f885e324>] ? drm_atomic_helper_prepare_planes+0x54/0x110 [drm_kms_helper]
[    4.004592]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.004657]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.004678]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.004742]  [<f8b45470>] ? gen2_write16+0x120/0x120 [i915]
[    4.004806]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.004871]  [<f8b8bc9f>] ? intel_crt_detect+0x47f/0x940 [i915]
[    4.004879]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.004886]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.004892]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.004897]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.004899]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.004902]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.004904]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.004907]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.004910]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.004915]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.004978]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.005014]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.005014]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.005014]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.005014]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.005014]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.005014]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.005014]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.005014]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.005014]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.005183] ---[ end trace e96a1a7a1ce213e4 ]---
[    4.005204] ------------[ cut here ]------------
[    4.005270] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13564 intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.005271] encoder detached but still enabled on pipe B.
[    4.005272] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.005321] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.005323] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.005326] Workqueue: events_unbound async_run_entry_fn
[    4.005328]  000034fc c1360ff2 f48c9cc4 00000000 c1052c52 f8bd3188 f48c9cdc 00000006
[    4.005335]  f8bcfb24 000034fc f8b6c474 f8b6c474 00000009 00000001 f49f7d80 f6140224
[    4.005341]  f6140000 c1052cab 00000009 00000000 f48c9cc4 f8bd3188 f48c9cdc f8b6c474
[    4.005348] Call Trace:
[    4.005352]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.005355]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.005419]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.005483]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.005486]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.005550]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.005558]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.005623]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.005687]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.005701]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.005765]  [<f8b45470>] ? gen2_write16+0x120/0x120 [i915]
[    4.005829]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.005893]  [<f8b8bc9f>] ? intel_crt_detect+0x47f/0x940 [i915]
[    4.005901]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.005909]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.005915]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.005917]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.005920]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.005922]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.005925]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.005928]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.005930]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.005934]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.005997]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.006060]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.006063]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.006066]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.006069]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.006072]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.006074]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.006074]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.006074]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.006074]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.006109] ---[ end trace e96a1a7a1ce213e5 ]---
[    4.006214] ------------[ cut here ]------------
[    4.006281] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:6952 verify_connector_state+0x269/0x320 [i915]
[    4.006282] connector enabled without attached crtc
[    4.006283] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.006332] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.006333] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.006336] Workqueue: events_unbound async_run_entry_fn
[    4.006338]  00001b28 c1360ff2 f48c9c90 00000000 c1052c52 f8bd2000 f48c9ca8 00000006
[    4.006345]  f8bcfb24 00001b28 f8b62819 f8b62819 00000009 f6123c00 f66c3c00 f6140224
[    4.006351]  00000000 c1052cab 00000009 00000000 f48c9c90 f8bd2000 f48c9ca8 f8b62819
[    4.006358] Call Trace:
[    4.006362]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.006365]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.006429]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.006493]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.006496]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.006559]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.006622]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    4.006687]  [<f8b6c119>] ? intel_atomic_commit_tail+0xbb9/0xf60 [i915]
[    4.006695]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.006760]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.006824]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.006838]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.006901]  [<f8b45470>] ? gen2_write16+0x120/0x120 [i915]
[    4.006965]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.007030]  [<f8b8bc9f>] ? intel_crt_detect+0x47f/0x940 [i915]
[    4.007038]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.007045]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.007051]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.007054]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.007057]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.007059]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.007062]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.007064]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.007067]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.007070]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.007090]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.007090]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.007090]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.007090]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.007090]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.007090]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.007090]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.007090]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.007090]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.007090]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.007247] ---[ end trace e96a1a7a1ce213e6 ]---
[    4.007925] ------------[ cut here ]------------
[    4.007990] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:12927 intel_atomic_check+0xcaa/0x1130 [i915]
[    4.007991] WARN_ON(!connector_state->crtc)
[    4.007993] Modules linked in:
[    4.007994]  ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.008065] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.008066] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.008069] Workqueue: events_unbound async_run_entry_fn
[    4.008072]  0000327f c1360ff2 f48c9b88 00000000 c1052c52 f8be1828 f48c9ba0 00000006
[    4.008078]  f8bcfb24 0000327f f8b6daea f8b6daea 00000009 00000000 f49f7d80 f4a5c000
[    4.008084]  f6123c00 c1052cab 00000009 00000000 f48c9b88 f8be1828 f48c9ba0 f8b6daea
[    4.008089] Call Trace:
[    4.008094]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.008096]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.008153]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    4.008209]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    4.008212]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.008268]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    4.008282]  [<f87b4f44>] ? drm_atomic_check_only+0x324/0x6b0 [drm]
[    4.008285]  [<c113ea93>] ? kmemdup+0x23/0x30
[    4.008297]  [<f87b52de>] ? drm_atomic_commit+0xe/0x50 [drm]
[    4.008354]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    4.008411]  [<f8baee42>] ? intel_tv_detect+0x142/0x5b0 [i915]
[    4.008421]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.008427]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.008432]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.008435]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.008437]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.008439]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.008442]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.008444]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.008446]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.008450]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.008506]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.008562]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.008564]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.008567]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.008570]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.008572]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.008575]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.008577]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.008580]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.008583]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.008584] ---[ end trace e96a1a7a1ce213e7 ]---
[    4.065039] ------------[ cut here ]------------
[    4.065179] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13556 intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.065181] encoder's enabled state mismatch (expected 0, found 1)
[    4.065183] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.065242] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.065243] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.065251] Workqueue: events_unbound async_run_entry_fn
[    4.065254]  000034f4 c1360ff2 f48c9b70 00000000 c1052c52 f8bd314c f48c9b88 00000006
[    4.065260]  f8bcfb24 000034f4 f8b6c380 f8b6c380 00000009 00000001 f49f7d80 f6140224
[    4.065266]  f6140000 c1052cab 00000009 00000000 f48c9b70 f8bd314c f48c9b88 f8b6c380
[    4.065272] Call Trace:
[    4.065281]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.065284]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.065342]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.065398]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.065401]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.065457]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.065468]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.065474]  [<f885e324>] ? drm_atomic_helper_prepare_planes+0x54/0x110 [drm_kms_helper]
[    4.065531]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.065588]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.065609]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.065666]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    4.065724]  [<f8baee42>] ? intel_tv_detect+0x142/0x5b0 [i915]
[    4.065732]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.065738]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.065743]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.065747]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.065749]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.065751]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.065754]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.065756]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.065758]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.065763]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.065819]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.065875]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.065878]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.065881]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.065884]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.065887]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.065890]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.065892]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.065896]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.065898]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.065998] ---[ end trace e96a1a7a1ce213e8 ]---
[    4.067025] ------------[ cut here ]------------
[    4.067103] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13564 intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.067104] encoder detached but still enabled on pipe B.
[    4.067105] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.067155] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.067156] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.067161] Workqueue: events_unbound async_run_entry_fn
[    4.067163]  000034fc c1360ff2 f48c9b70 00000000 c1052c52 f8bd3188 f48c9b88 00000006
[    4.067170]  f8bcfb24 000034fc f8b6c474 f8b6c474 00000009 00000001 f49f7d80 f6140224
[    4.067176]  f6140000 c1052cab 00000009 00000000 f48c9b70 f8bd3188 f48c9b88 f8b6c474
[    4.067181] Call Trace:
[    4.067188]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.067191]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.067248]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.067304]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.067307]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.067363]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.067373]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.067430]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.067487]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.067502]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.067559]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    4.067617]  [<f8baee42>] ? intel_tv_detect+0x142/0x5b0 [i915]
[    4.067626]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.067632]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.067637]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.067640]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.067642]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.067645]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.067647]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.067649]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.067651]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.067656]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.067712]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.067767]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.067770]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.067773]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.067776]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.067778]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.067781]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.067783]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.067786]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.067789]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.067791] ---[ end trace e96a1a7a1ce213e9 ]---
[    4.067796] ------------[ cut here ]------------
[    4.067853] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:6952 verify_connector_state+0x269/0x320 [i915]
[    4.067854] connector enabled without attached crtc
[    4.067855] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.067897] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: G        W       4.9.160-antix.2-486-smp #1
[    4.067899] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.067901] Workqueue: events_unbound async_run_entry_fn
[    4.067902]  00001b28 c1360ff2 f48c9b3c 00000000 c1052c52 f8bd2000 f48c9b54 00000006
[    4.067909]  f8bcfb24 00001b28 f8b62819 f8b62819 00000009 f6123c00 f66c3c00 f6140224
[    4.067914]  00000000 c1052cab 00000009 00000000 f48c9b3c f8bd2000 f48c9b54 f8b62819
[    4.067920] Call Trace:
[    4.067924]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.067926]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.067982]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.068006]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.068006]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.068006]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.068006]  [<f8b8b497>] ? intel_crt_get_hw_state+0x57/0x90 [i915]
[    4.068006]  [<f8b6c119>] ? intel_atomic_commit_tail+0xbb9/0xf60 [i915]
[    4.068006]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.068006]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.068006]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.068006]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.068006]  [<f8b7154e>] ? intel_get_load_detect_pipe+0x44e/0x660 [i915]
[    4.068006]  [<f8baee42>] ? intel_tv_detect+0x142/0x5b0 [i915]
[    4.068006]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.068006]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.068006]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.068006]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.068006]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.068006]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.068006]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.068006]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.068006]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.068006]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.068006]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.068006]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.068006]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.068006]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.068006]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.068006]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.068006]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.068006]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.068006]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.068006]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.068647] ---[ end trace e96a1a7a1ce213ea ]---
[    4.076164] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[    4.076170] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.076173] usb usb5: Product: OHCI PCI host controller
[    4.076175] usb usb5: Manufacturer: Linux 4.9.160-antix.2-486-smp ohci_hcd
[    4.076177] usb usb5: SerialNumber: 0000:07:00.0
[    4.077069] hub 5-0:1.0: USB hub found
[    4.077094] hub 5-0:1.0: 3 ports detected
[    4.077304] pci 0000:07:00.1: enabling device (0000 -> 0002)
[    4.077637] ohci-pci 0000:07:00.1: OHCI PCI host controller
[    4.077647] ohci-pci 0000:07:00.1: new USB bus registered, assigned bus number 6
[    4.077681] ohci-pci 0000:07:00.1: irq 20, io mem 0x88001000
[    4.170836] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
[    4.170859] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.170861] usb usb6: Product: OHCI PCI host controller
[    4.170864] usb usb6: Manufacturer: Linux 4.9.160-antix.2-486-smp ohci_hcd
[    4.170866] usb usb6: SerialNumber: 0000:07:00.1
[    4.172822] hub 6-0:1.0: USB hub found
[    4.172838] hub 6-0:1.0: 2 ports detected
[    4.174027] pci 0000:07:00.2: enabling device (0000 -> 0002)
[    4.174144] wl: loading out-of-tree module taints kernel.
[    4.174151] wl: module license 'MIXED/Proprietary' taints kernel.
[    4.174152] Disabling lock debugging due to kernel taint
[    4.181338] ehci-pci 0000:07:00.2: EHCI Host Controller
[    4.181354] ehci-pci 0000:07:00.2: new USB bus registered, assigned bus number 7
[    4.181417] ehci-pci 0000:07:00.2: irq 20, io mem 0x88002000
[    4.188039] ehci-pci 0000:07:00.2: USB 2.0 started, EHCI 1.00
[    4.188215] usb usb7: New USB device found, idVendor=1d6b, idProduct=0002
[    4.188218] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    4.188221] usb usb7: Product: EHCI Host Controller
[    4.188223] usb usb7: Manufacturer: Linux 4.9.160-antix.2-486-smp ehci_hcd
[    4.188226] usb usb7: SerialNumber: 0000:07:00.2
[    4.188485] hub 7-0:1.0: USB hub found
[    4.188498] hub 7-0:1.0: 5 ports detected
[    4.203731] ------------[ cut here ]------------
[    4.203922] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:12927 intel_atomic_check+0xcaa/0x1130 [i915]
[    4.203925] WARN_ON(!connector_state->crtc)
[    4.203927] Modules linked in:
[    4.203929]  ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.204071] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: P        W  O    4.9.160-antix.2-486-smp #1
[    4.204073] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.204084] Workqueue: events_unbound async_run_entry_fn
[    4.204087]  0000327f c1360ff2 f48c9c2c 00000000 c1052c52 f8be1828 f48c9c44 00000006
[    4.204093]  f8bcfb24 0000327f f8b6daea f8b6daea 00000009 00000000 f49f7d80 f4a5d800
[    4.204099]  f6123c00 c1052cab 00000009 00000000 f48c9c2c f8be1828 f48c9c44 f8b6daea
[    4.204105] Call Trace:
[    4.204116]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.204120]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.204190]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    4.204247]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    4.204250]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.204306]  [<f8b6daea>] ? intel_atomic_check+0xcaa/0x1130 [i915]
[    4.204312]  [<c10b5059>] ? del_timer_sync+0x39/0x40
[    4.204319]  [<c16a1c8a>] ? schedule_timeout+0x1aa/0x4a0
[    4.204344]  [<f87b4f44>] ? drm_atomic_check_only+0x324/0x6b0 [drm]
[    4.204408]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    4.204421]  [<f87b52de>] ? drm_atomic_commit+0xe/0x50 [drm]
[    4.204478]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.204535]  [<f8baf085>] ? intel_tv_detect+0x385/0x5b0 [i915]
[    4.204550]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.204556]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.204561]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.204565]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.204568]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.204570]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.204572]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.204574]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.204576]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.204582]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.204640]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.204695]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.204698]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.204702]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.204704]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.204707]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.204711]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.204713]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.204716]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.204718]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.204721] ---[ end trace e96a1a7a1ce213eb ]---
[    4.240202] hub 5-0:1.0: USB hub found
[    4.240219] hub 5-0:1.0: 3 ports detected
[    4.253048] ------------[ cut here ]------------
[    4.253184] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13556 intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.253185] encoder's enabled state mismatch (expected 0, found 1)
[    4.253187] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.253246] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: P        W  O    4.9.160-antix.2-486-smp #1
[    4.253248] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.253255] Workqueue: events_unbound async_run_entry_fn
[    4.253258]  000034f4 c1360ff2 f48c9c14 00000000 c1052c52 f8bd314c f48c9c2c 00000006
[    4.253264]  f8bcfb24 000034f4 f8b6c380 f8b6c380 00000009 00000001 f49f7d80 f6140224
[    4.253270]  f6140000 c1052cab 00000009 00000000 f48c9c14 f8bd314c f48c9c2c f8b6c380
[    4.253276] Call Trace:
[    4.253284]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.253288]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.253345]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.253401]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.253404]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.253460]  [<f8b6c380>] ? intel_atomic_commit_tail+0xe20/0xf60 [i915]
[    4.253471]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.253478]  [<f885e324>] ? drm_atomic_helper_prepare_planes+0x54/0x110 [drm_kms_helper]
[    4.253534]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.253592]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.253646]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    4.253668]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.253725]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.253782]  [<f8baf085>] ? intel_tv_detect+0x385/0x5b0 [i915]
[    4.253790]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.253797]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.253802]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.253805]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.253808]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.253810]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.253812]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.253814]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.253816]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.253821]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.253878]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.253933]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.253936]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.253940]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.253942]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.253945]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.253948]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.253951]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.253954]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.253956]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.253958] ---[ end trace e96a1a7a1ce213ec ]---
[    4.253961] ------------[ cut here ]------------
[    4.254007] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:13564 intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.254030] encoder detached but still enabled on pipe B.
[    4.254031] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.254073] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: P        W  O    4.9.160-antix.2-486-smp #1
[    4.254075] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.254077] Workqueue: events_unbound async_run_entry_fn
[    4.254079]  000034fc c1360ff2 f48c9c14 00000000 c1052c52 f8bd3188 f48c9c2c 00000006
[    4.254085]  f8bcfb24 000034fc f8b6c474 f8b6c474 00000009 00000001 f49f7d80 f6140224
[    4.254091]  f6140000 c1052cab 00000009 00000000 f48c9c14 f8bd3188 f48c9c2c f8b6c474
[    4.254097] Call Trace:
[    4.254100]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.254102]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.254159]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.254215]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.254217]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.254273]  [<f8b6c474>] ? intel_atomic_commit_tail+0xf14/0xf60 [i915]
[    4.254280]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.254336]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.254393]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.254447]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    4.254460]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.254516]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.254573]  [<f8baf085>] ? intel_tv_detect+0x385/0x5b0 [i915]
[    4.254582]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.254588]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.254593]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.254596]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.254598]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.254600]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.254602]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.254605]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.254607]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.254610]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.254666]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.254721]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.254724]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.254726]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.254729]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.254732]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.254734]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.254737]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.254740]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.254742]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.254744] ---[ end trace e96a1a7a1ce213ed ]---
[    4.254748] ------------[ cut here ]------------
[    4.254805] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_display.c:6952 verify_connector_state+0x269/0x320 [i915]
[    4.254806] connector enabled without attached crtc
[    4.254807] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.254849] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: P        W  O    4.9.160-antix.2-486-smp #1
[    4.254851] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.254853] Workqueue: events_unbound async_run_entry_fn
[    4.254854]  00001b28 c1360ff2 f48c9be0 00000000 c1052c52 f8bd2000 f48c9bf8 00000006
[    4.254860]  f8bcfb24 00001b28 f8b62819 f8b62819 00000009 f6123c00 f66c3c00 f6140224
[    4.254866]  00000000 c1052cab 00000009 00000000 f48c9be0 f8bd2000 f48c9bf8 f8b62819
[    4.254872] Call Trace:
[    4.254875]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.254878]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.254934]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.254990]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.254992]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.255025]  [<f8b62819>] ? verify_connector_state+0x269/0x320 [i915]
[    4.255025]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    4.255025]  [<f8b6c119>] ? intel_atomic_commit_tail+0xbb9/0xf60 [i915]
[    4.255025]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.255025]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.255025]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.255025]  [<f8b456c0>] ? gen2_read8+0x130/0x130 [i915]
[    4.255025]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.255025]  [<f8b717af>] ? intel_release_load_detect_pipe+0x4f/0x90 [i915]
[    4.255025]  [<f8baf085>] ? intel_tv_detect+0x385/0x5b0 [i915]
[    4.255025]  [<f8857f9d>] ? drm_helper_probe_single_connector_modes+0x42d/0x550 [drm_kms_helper]
[    4.255025]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.255025]  [<f8865cf9>] ? drm_fb_helper_initial_config+0x79/0x425 [drm_kms_helper]
[    4.255025]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.255025]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.255025]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.255025]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.255025]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.255025]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.255025]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.255025]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.255025]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.255025]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.255025]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.255025]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.255025]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.255025]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.255025]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.255025]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.255025]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.255636] ---[ end trace e96a1a7a1ce213ee ]---
[    4.256494] ------------[ cut here ]------------
[    4.256553] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/i915/intel_fbdev.c:414 intel_fb_initial_config+0x484/0x620 [i915]
[    4.256554] WARN_ON(!connector->state->crtc)
[    4.256555] Modules linked in:
[    4.256556]  ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.256599] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: P        W  O    4.9.160-antix.2-486-smp #1
[    4.256600] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.256602] Workqueue: events_unbound async_run_entry_fn
[    4.256604]  0000019e c1360ff2 f48c9da4 00000000 c1052c52 f8be3193 f48c9dbc 00000006
[    4.256610]  f8bd6628 0000019e f8b87eb4 f8b87eb4 00000009 00000001 f6123c00 00000003
[    4.256616]  00000000 c1052cab 00000009 00000000 f48c9da4 f8be3193 f48c9dbc f8b87eb4
[    4.256622] Call Trace:
[    4.256626]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.256628]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.256684]  [<f8b87eb4>] ? intel_fb_initial_config+0x484/0x620 [i915]
[    4.256739]  [<f8b87eb4>] ? intel_fb_initial_config+0x484/0x620 [i915]
[    4.256742]  [<c1052cab>] ? warn_slowpath_fmt+0x3b/0x40
[    4.256797]  [<f8b87eb4>] ? intel_fb_initial_config+0x484/0x620 [i915]
[    4.256853]  [<f8b87a30>] ? intelfb_create+0x480/0x480 [i915]
[    4.256858]  [<f886527c>] ? drm_setup_crtcs+0x1ac/0x990 [drm_kms_helper]
[    4.256870]  [<f87b8472>] ? drm_mode_connector_update_edid_property+0x42/0x60 [drm]
[    4.256877]  [<f8857b70>] ? drm_kms_helper_poll_enable_locked+0xf0/0xf0 [drm_kms_helper]
[    4.256882]  [<f8865d18>] ? drm_fb_helper_initial_config+0x98/0x425 [drm_kms_helper]
[    4.256885]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.256887]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.256889]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.256892]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.256894]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.256896]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.256899]  [<c101866f>] ? __switch_to+0xef/0x380
[    4.256955]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.257004]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.257004]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.257004]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.257004]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.257004]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.257004]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.257004]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.257004]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.257004]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.257045] ---[ end trace e96a1a7a1ce213ef ]---
[    4.261061] fbcon: inteldrmfb (fb0) is primary device
[    4.261632] ------------[ cut here ]------------
[    4.261647] WARNING: CPU: 0 PID: 6 at drivers/gpu/drm/drm_atomic_helper.c:783 drm_atomic_helper_update_legacy_modeset_state+0x20f/0x240 [drm_kms_helper]
[    4.261687] Modules linked in: ppdev evdev joydev input_leds serio_raw pcmcia ipw2200 libipw lib80211 cfg80211 lpc_ich rfkill rng_core snd_intel8x0m snd_intel8x0 snd_ac97_codec i915 ac97_bus snd_pcm yenta_socket pcmcia_rsrc pcmcia_core snd_timer snd soundcore drm_kms_helper parport_pc parport drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect intel_agp sysimgblt panasonic_laptop intel_gtt sparse_keymap shpchp battery video acpi_cpufreq tpm_tis ac tpm_tis_core tpm button btrfs xor raid6_pq psmouse i2c_i801 i2c_smbus sdhci_pci sdhci mmc_core sky2 thermal rtc_cmos fjes
[    4.261691] CPU: 0 PID: 6 Comm: kworker/u4:0 Tainted: P        W  O    4.9.160-antix.2-486-smp #1
[    4.261693] Hardware name: Matsushita Electric Industrial Co.,Ltd. CF-29N3LGZBM/CF29-5, BIOS V5.00L11 12/20/2005
[    4.261700] Workqueue: events_unbound async_run_entry_fn
[    4.261705]  0000030f c1360ff2 00000000 00000000 c1052c52 c17cc8dc 00000000 00000006
[    4.261710]  f88684bc 0000030f f885e83f f885e83f 00000009 f6123c00 00000000 f66c3c00
[    4.261715]  f6111000 c1052d13 00000009 00000000 00000000 f885e83f f8b6afcd f6140000
[    4.261715] Call Trace:
[    4.261722]  [<c1360ff2>] ? dump_stack+0x55/0x73
[    4.261725]  [<c1052c52>] ? __warn+0xe2/0x100
[    4.261731]  [<f885e83f>] ? drm_atomic_helper_update_legacy_modeset_state+0x20f/0x240 [drm_kms_helper]
[    4.261737]  [<f885e83f>] ? drm_atomic_helper_update_legacy_modeset_state+0x20f/0x240 [drm_kms_helper]
[    4.261740]  [<c1052d13>] ? warn_slowpath_null+0x23/0x30
[    4.261746]  [<f885e83f>] ? drm_atomic_helper_update_legacy_modeset_state+0x20f/0x240 [drm_kms_helper]
[    4.261832]  [<f8b6afcd>] ? intel_pre_plane_update+0x4d/0x140 [i915]
[    4.261889]  [<f8b6bfce>] ? intel_atomic_commit_tail+0xa6e/0xf60 [i915]
[    4.261896]  [<f8861444>] ? drm_atomic_helper_setup_commit+0x2e4/0x370 [drm_kms_helper]
[    4.261903]  [<f885e324>] ? drm_atomic_helper_prepare_planes+0x54/0x110 [drm_kms_helper]
[    4.261959]  [<f8b6c7ee>] ? intel_atomic_commit+0x32e/0x4b0 [i915]
[    4.262005]  [<f8b6c4c0>] ? intel_atomic_commit_tail+0xf60/0xf60 [i915]
[    4.262005]  [<f87b5316>] ? drm_atomic_commit+0x46/0x50 [drm]
[    4.262005]  [<f8863efb>] ? restore_fbdev_mode+0x14b/0x290 [drm_kms_helper]
[    4.262005]  [<f87b419c>] ? drm_modeset_lock_all_ctx+0x8c/0xa0 [drm]
[    4.262005]  [<f8865bbf>] ? drm_fb_helper_restore_fbdev_mode_unlocked+0x1f/0x70 [drm_kms_helper]
[    4.262005]  [<f8865c35>] ? drm_fb_helper_set_par+0x25/0x70 [drm_kms_helper]
[    4.262005]  [<f8b8754d>] ? intel_fbdev_set_par+0xd/0x70 [i915]
[    4.262005]  [<c140e3e0>] ? fbcon_init+0x5b0/0x600
[    4.262005]  [<c13e507e>] ? con_release_unimap+0x7e/0xc0
[    4.262005]  [<c13e6638>] ? visual_init+0xb8/0x110
[    4.262005]  [<c13e764d>] ? do_bind_con_driver+0x17d/0x380
[    4.262005]  [<c13e7b5e>] ? do_take_over_console+0x11e/0x1a0
[    4.262005]  [<c1410360>] ? fbcon_switch+0x6b0/0x6b0
[    4.262005]  [<c140c9ff>] ? do_fbcon_takeover+0x4f/0xc0
[    4.262005]  [<c106f936>] ? notifier_call_chain+0x46/0x70
[    4.262005]  [<c106fb93>] ? __blocking_notifier_call_chain+0x33/0x60
[    4.262005]  [<c106fbd7>] ? blocking_notifier_call_chain+0x17/0x20
[    4.262005]  [<c1419fb3>] ? register_framebuffer+0x1e3/0x320
[    4.262005]  [<f8865eec>] ? drm_fb_helper_initial_config+0x26c/0x425 [drm_kms_helper]
[    4.262005]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.262005]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.262005]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.262005]  [<c16a31e7>] ? __switch_to_asm+0x27/0x50
[    4.262005]  [<f8b88620>] ? intel_fbdev_fini+0xd0/0xd0 [i915]
[    4.262005]  [<f8b8862e>] ? intel_fbdev_initial_config+0xe/0x30 [i915]
[    4.262005]  [<c1070f83>] ? async_run_entry_fn+0x33/0xd0
[    4.262005]  [<c1069431>] ? process_one_work+0x191/0x3e0
[    4.262005]  [<c10696b7>] ? worker_thread+0x37/0x4e0
[    4.262005]  [<c1069680>] ? process_one_work+0x3e0/0x3e0
[    4.262005]  [<c106e644>] ? kthread+0xa4/0xc0
[    4.262005]  [<c16a31f3>] ? __switch_to_asm+0x33/0x50
[    4.262005]  [<c106e5a0>] ? kthread_park+0x50/0x50
[    4.262005]  [<c16a3240>] ? ret_from_fork+0x30/0x40
[    4.262314] ---[ end trace e96a1a7a1ce213f0 ]---
[    4.281441] Console: switching to colour frame buffer device 128x48
[    4.287524] gpio_ich: ACPI BAR is busy, GPI 0 - 15 unavailable
[    4.289072] gpio_ich: GPIO from 462 to 511 on gpio_ich
[    4.292140] hub 6-0:1.0: USB hub found
[    4.292184] hub 6-0:1.0: 2 ports detected
[    4.292415] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff:
[    4.292435]  excluding 0xc0000-0xc7fff 0xcc000-0xd3fff 0xe0000-0xfffff
[    4.292454] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff:
[    4.292470]  clean
[    4.292488] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff:
[    4.292500]  excluding 0x60000000-0x60ffffff
[    4.302914] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[    4.311967] iTCO_vendor_support: vendor-support=0
[    4.314981] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[    4.320131] iTCO_wdt: Found a ICH6-M TCO device (Version=2, TCOBASE=0x1060)
[    4.323260] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[    5.187292] Adding 2882556k swap on /dev/sda3.  Priority:-1 extents:1 across:2882556k SSFS
[    5.214256] EXT4-fs (sda2): re-mounted. Opts: (null)
[    5.427349] device-mapper: uevent: version 1.0.3
[    5.428512] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
[    5.569704] lp0: using parport0 (interrupt-driven).
[    5.569708] lp0: console ready
[    5.853677] urandom_read: 2 callbacks suppressed
[    5.853679] random: dd: uninitialized urandom read (512 bytes read)
[    5.947362] networking: ifup eth0
[    5.947643] networking: ifup eth1
[    5.988946] networking done
[    6.105037] NET: Registered protocol family 17
[    6.114486] sky2 0000:02:00.0 eth0: enabling interface
[    6.148292] random: wpa_supplicant: uninitialized urandom read (32 bytes read)
[    6.158041] NET: Registered protocol family 10
[    6.158474] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[    6.158539] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[    6.250670] RPC: Registered named UNIX socket transport module.
[    6.250674] RPC: Registered udp transport module.
[    6.250675] RPC: Registered tcp transport module.
[    6.250676] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    6.259382] FS-Cache: Loaded
[    6.279816] FS-Cache: Netfs 'nfs' registered for caching
[    6.297656] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[    7.259853] random: cupsd: uninitialized urandom read (4096 bytes read)
[    7.435675] Bluetooth: Core ver 2.22
[    7.435701] NET: Registered protocol family 31
[    7.435702] Bluetooth: HCI device and connection manager initialized
[    7.435978] Bluetooth: HCI socket layer initialized
[    7.435982] Bluetooth: L2CAP socket layer initialized
[    7.435991] Bluetooth: SCO socket layer initialized
[    7.461749] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    7.461753] Bluetooth: BNEP filters: protocol multicast
[    7.461761] Bluetooth: BNEP socket layer initialized
[    9.033083] random: crng init done
[   69.900054] usb 6-1: new full-speed USB device number 2 using ohci-pci
[   70.108040] usb 6-1: New USB device found, idVendor=046d, idProduct=c52f
[   70.108051] usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[   70.108058] usb 6-1: Product: USB Receiver
[   70.108064] usb 6-1: Manufacturer: Logitech
[   70.677236] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb6/6-1/6-1:1.0/0003:046D:C52F.0001/input/input9
[   70.730151] hid-generic 0003:046D:C52F.0001: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:07:00.1-1/input0
[   70.736188] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb6/6-1/6-1:1.1/0003:046D:C52F.0002/input/input10
[   70.835289] hid-generic 0003:046D:C52F.0002: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:07:00.1-1/input1
[  551.465218] ohci-pci 0000:07:00.0: HC died; cleaning up
[  551.465245] ohci-pci 0000:07:00.1: HC died; cleaning up
[  551.465261] ehci-pci 0000:07:00.2: HC died; cleaning up
[  551.465304] pcmcia_socket pcmcia_socket0: pccard: card ejected from slot 0
[  551.465619] usb 6-1: USB disconnect, device number 2
[  551.497135] ohci-pci 0000:07:00.0: remove, state 4
[  551.497148] usb usb5: USB disconnect, device number 1
[  551.497673] ohci-pci 0000:07:00.0: USB bus 5 deregistered
[  551.498061] ohci-pci 0000:07:00.1: remove, state 1
[  551.498076] usb usb6: USB disconnect, device number 1
[  551.498709] ohci-pci 0000:07:00.1: USB bus 6 deregistered
[  551.499045] ehci-pci 0000:07:00.2: remove, state 4
[  551.499210] usb usb7: USB disconnect, device number 1
[  551.499732] ehci-pci 0000:07:00.2: USB bus 7 deregistered
[  632.984046] pcmcia_socket pcmcia_socket0: pccard: CardBus card inserted into slot 0
[  632.984074] pci 0000:07:00.0: [1033:0035] type 00 class 0x0c0310
[  632.984100] pci 0000:07:00.0: reg 0x10: [mem 0x00000000-0x00000fff]
[  632.984216] pci 0000:07:00.0: supports D1 D2
[  632.984219] pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot
[  632.984380] pci 0000:07:00.1: [1033:0035] type 00 class 0x0c0310
[  632.984400] pci 0000:07:00.1: reg 0x10: [mem 0x00000000-0x00000fff]
[  632.984494] pci 0000:07:00.1: supports D1 D2
[  632.984497] pci 0000:07:00.1: PME# supported from D0 D1 D2 D3hot
[  632.984597] pci 0000:07:00.2: [1033:00e0] type 00 class 0x0c0320
[  632.984617] pci 0000:07:00.2: reg 0x10: [mem 0x00000000-0x000000ff]
[  632.984711] pci 0000:07:00.2: supports D1 D2
[  632.984714] pci 0000:07:00.2: PME# supported from D0 D1 D2 D3hot
[  632.984816] pci 0000:07:00.0: BAR 0: assigned [mem 0x88000000-0x88000fff]
[  632.984823] pci 0000:07:00.1: BAR 0: assigned [mem 0x88001000-0x88001fff]
[  632.984830] pci 0000:07:00.2: BAR 0: assigned [mem 0x88002000-0x880020ff]
[  632.984870] pci 0000:07:00.0: enabling device (0000 -> 0002)
[  632.985204] ohci-pci 0000:07:00.0: OHCI PCI host controller
[  632.985215] ohci-pci 0000:07:00.0: new USB bus registered, assigned bus number 5
[  632.985253] ohci-pci 0000:07:00.0: irq 20, io mem 0x88000000
[  633.067331] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[  633.067337] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[  633.067342] usb usb5: Product: OHCI PCI host controller
[  633.067346] usb usb5: Manufacturer: Linux 4.9.160-antix.2-486-smp ohci_hcd
[  633.067349] usb usb5: SerialNumber: 0000:07:00.0
[  633.070808] hub 5-0:1.0: USB hub found
[  633.070824] hub 5-0:1.0: 3 ports detected
[  633.071132] pci 0000:07:00.1: enabling device (0000 -> 0002)
[  633.071448] ohci-pci 0000:07:00.1: OHCI PCI host controller
[  633.071458] ohci-pci 0000:07:00.1: new USB bus registered, assigned bus number 6
[  633.071488] ohci-pci 0000:07:00.1: irq 20, io mem 0x88001000
[  633.153112] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
[  633.153115] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[  633.153117] usb usb6: Product: OHCI PCI host controller
[  633.153120] usb usb6: Manufacturer: Linux 4.9.160-antix.2-486-smp ohci_hcd
[  633.153122] usb usb6: SerialNumber: 0000:07:00.1
[  633.156329] hub 6-0:1.0: USB hub found
[  633.156343] hub 6-0:1.0: 2 ports detected
[  633.156503] pci 0000:07:00.2: enabling device (0000 -> 0002)
[  633.157895] ehci-pci 0000:07:00.2: EHCI Host Controller
[  633.157904] ehci-pci 0000:07:00.2: new USB bus registered, assigned bus number 7
[  633.157951] ehci-pci 0000:07:00.2: irq 20, io mem 0x88002000
[  633.164054] ehci-pci 0000:07:00.2: USB 2.0 started, EHCI 1.00
[  633.164124] usb usb7: New USB device found, idVendor=1d6b, idProduct=0002
[  633.164129] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[  633.164133] usb usb7: Product: EHCI Host Controller
[  633.164137] usb usb7: Manufacturer: Linux 4.9.160-antix.2-486-smp ehci_hcd
[  633.164141] usb usb7: SerialNumber: 0000:07:00.2
[  633.164939] hub 7-0:1.0: USB hub found
[  633.165244] hub 7-0:1.0: 5 ports detected
[  633.217252] hub 5-0:1.0: USB hub found
[  633.217287] hub 5-0:1.0: 3 ports detected
[  633.269209] hub 6-0:1.0: USB hub found
[  633.269244] hub 6-0:1.0: 2 ports detected
[  633.812029] usb 6-1: new full-speed USB device number 2 using ohci-pci
[  634.020046] usb 6-1: New USB device found, idVendor=046d, idProduct=c52f
[  634.020056] usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[  634.020063] usb 6-1: Product: USB Receiver
[  634.020070] usb 6-1: Manufacturer: Logitech
[  634.038756] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb6/6-1/6-1:1.0/0003:046D:C52F.0003/input/input11
[  634.091644] hid-generic 0003:046D:C52F.0003: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:07:00.1-1/input0
[  634.112301] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb6/6-1/6-1:1.1/0003:046D:C52F.0004/input/input12
[  634.197515] hid-generic 0003:046D:C52F.0004: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:07:00.1-1/input1
[  669.567479] ohci-pci 0000:07:00.0: HC died; cleaning up
[  669.567505] ohci-pci 0000:07:00.1: HC died; cleaning up
[  669.567520] ehci-pci 0000:07:00.2: HC died; cleaning up
[  669.567609] pcmcia_socket pcmcia_socket0: pccard: card ejected from slot 0
[  669.567929] usb 6-1: USB disconnect, device number 2
[  669.599138] ohci-pci 0000:07:00.0: remove, state 4
[  669.599151] usb usb5: USB disconnect, device number 1
[  669.599477] ohci-pci 0000:07:00.0: USB bus 5 deregistered
[  669.599719] ohci-pci 0000:07:00.1: remove, state 1
[  669.599728] usb usb6: USB disconnect, device number 1
[  669.600037] ohci-pci 0000:07:00.1: USB bus 6 deregistered
[  669.600229] ehci-pci 0000:07:00.2: remove, state 4
[  669.600238] usb usb7: USB disconnect, device number 1
[  669.600871] ehci-pci 0000:07:00.2: USB bus 7 deregistered
[ 1067.904057] pcmcia_socket pcmcia_socket0: pccard: CardBus card inserted into slot 0
[ 1067.904098] pci 0000:07:00.0: [1033:0035] type 00 class 0x0c0310
[ 1067.904135] pci 0000:07:00.0: reg 0x10: [mem 0x00000000-0x00000fff]
[ 1067.904283] pci 0000:07:00.0: supports D1 D2
[ 1067.904290] pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot
[ 1067.904600] pci 0000:07:00.1: [1033:0035] type 00 class 0x0c0310
[ 1067.904630] pci 0000:07:00.1: reg 0x10: [mem 0x00000000-0x00000fff]
[ 1067.904762] pci 0000:07:00.1: supports D1 D2
[ 1067.904769] pci 0000:07:00.1: PME# supported from D0 D1 D2 D3hot
[ 1067.905034] pci 0000:07:00.2: [1033:00e0] type 00 class 0x0c0320
[ 1067.905065] pci 0000:07:00.2: reg 0x10: [mem 0x00000000-0x000000ff]
[ 1067.907139] pci 0000:07:00.2: supports D1 D2
[ 1067.907147] pci 0000:07:00.2: PME# supported from D0 D1 D2 D3hot
[ 1067.907410] pci 0000:07:00.0: BAR 0: assigned [mem 0x88000000-0x88000fff]
[ 1067.907424] pci 0000:07:00.1: BAR 0: assigned [mem 0x88001000-0x88001fff]
[ 1067.907436] pci 0000:07:00.2: BAR 0: assigned [mem 0x88002000-0x880020ff]
[ 1067.907493] pci 0000:07:00.0: enabling device (0000 -> 0002)
[ 1067.909146] ohci-pci 0000:07:00.0: OHCI PCI host controller
[ 1067.909171] ohci-pci 0000:07:00.0: new USB bus registered, assigned bus number 5
[ 1067.909232] ohci-pci 0000:07:00.0: irq 20, io mem 0x88000000
[ 1067.991967] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[ 1067.991973] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1067.991975] usb usb5: Product: OHCI PCI host controller
[ 1067.991978] usb usb5: Manufacturer: Linux 4.9.160-antix.2-486-smp ohci_hcd
[ 1067.991980] usb usb5: SerialNumber: 0000:07:00.0
[ 1067.994679] hub 5-0:1.0: USB hub found
[ 1067.995725] hub 5-0:1.0: 3 ports detected
[ 1067.995938] pci 0000:07:00.1: enabling device (0000 -> 0002)
[ 1067.996366] ohci-pci 0000:07:00.1: OHCI PCI host controller
[ 1067.996375] ohci-pci 0000:07:00.1: new USB bus registered, assigned bus number 6
[ 1067.996411] ohci-pci 0000:07:00.1: irq 20, io mem 0x88001000
[ 1068.078220] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001
[ 1068.078229] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1068.078236] usb usb6: Product: OHCI PCI host controller
[ 1068.078243] usb usb6: Manufacturer: Linux 4.9.160-antix.2-486-smp ohci_hcd
[ 1068.078249] usb usb6: SerialNumber: 0000:07:00.1
[ 1068.081728] hub 6-0:1.0: USB hub found
[ 1068.081743] hub 6-0:1.0: 2 ports detected
[ 1068.081910] pci 0000:07:00.2: enabling device (0000 -> 0002)
[ 1068.083419] ehci-pci 0000:07:00.2: EHCI Host Controller
[ 1068.083429] ehci-pci 0000:07:00.2: new USB bus registered, assigned bus number 7
[ 1068.083476] ehci-pci 0000:07:00.2: irq 20, io mem 0x88002000
[ 1068.090052] ehci-pci 0000:07:00.2: USB 2.0 started, EHCI 1.00
[ 1068.090123] usb usb7: New USB device found, idVendor=1d6b, idProduct=0002
[ 1068.090128] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1068.090132] usb usb7: Product: EHCI Host Controller
[ 1068.090136] usb usb7: Manufacturer: Linux 4.9.160-antix.2-486-smp ehci_hcd
[ 1068.090140] usb usb7: SerialNumber: 0000:07:00.2
[ 1068.090940] hub 7-0:1.0: USB hub found
[ 1068.091183] hub 7-0:1.0: 5 ports detected
[ 1068.143254] hub 5-0:1.0: USB hub found
[ 1068.143287] hub 5-0:1.0: 3 ports detected
[ 1068.195207] hub 6-0:1.0: USB hub found
[ 1068.195239] hub 6-0:1.0: 2 ports detected
[ 1068.732049] usb 6-1: new full-speed USB device number 2 using ohci-pci
[ 1068.940023] usb 6-1: New USB device found, idVendor=046d, idProduct=c52f
[ 1068.940030] usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 1068.940034] usb 6-1: Product: USB Receiver
[ 1068.940037] usb 6-1: Manufacturer: Logitech
[ 1068.958864] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb6/6-1/6-1:1.0/0003:046D:C52F.0005/input/input13
[ 1069.012656] hid-generic 0003:046D:C52F.0005: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Receiver] on usb-0000:07:00.1-1/input0
[ 1069.033851] input: Logitech USB Receiver as /devices/pci0000:00/0000:00:1e.0/0000:06:01.0/0000:07:00.1/usb6/6-1/6-1:1.1/0003:046D:C52F.0006/input/input14
[ 1069.118544] hid-generic 0003:046D:C52F.0006: input,hiddev0,hidraw1: USB HID v1.11 Device [Logitech USB Receiver] on usb-0000:07:00.1-1/input1

lspci -vvv
00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Capabilities: [e0] Vendor Specific Information: Len=09 <?>
	Kernel modules: intel_agp

00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04) (prog-if 00 [VGA controller])
	Subsystem: Matsushita Electric Industrial Co., Ltd. Mobile 915GM/GMS/910GML Express Graphics Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at b0080000 (32-bit, non-prefetchable) [size=512K]
	Region 1: I/O ports at 1800 [size=8]
	Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M]
	Region 3: Memory at b0000000 (32-bit, non-prefetchable) [size=256K]
	[virtual] Expansion ROM at 000c0000 [disabled] [size=128K]
	Capabilities: [d0] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: i915
	Kernel modules: i915

00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Mobile 915GM/GMS/910GML Express Graphics Controller
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Region 0: Memory at 80000000 (32-bit, non-prefetchable) [disabled] [size=512K]
	Capabilities: [d0] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

00:1c.0 PCI bridge: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1 (rev 04) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 24
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00003000-00003fff
	Memory behind bridge: b4000000-b7ffffff
	Prefetchable memory behind bridge: 00000000d0000000-00000000d3ffffff
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag+ RBE-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 128 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 <4us
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
			Slot #2, PowerLimit 6.500W; Interlock- NoCompl-
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet- LinkState-
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
		RootCap: CRSVisible-
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
	Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
		Address: 00000000  Data: 0000
	Capabilities: [90] Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1
	Capabilities: [a0] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [100 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed+ WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=01
			Status:	NegoPending- InProgress-
		VC1:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable- ID=0 ArbSelect=Fixed TC/VC=00
			Status:	NegoPending- InProgress-
	Capabilities: [180 v1] Root Complex Link
		Desc:	PortNumber=01 ComponentID=02 EltType=Config
		Link0:	Desc:	TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
			Addr:	00000000fed1c001
	Kernel driver in use: pcieport
	Kernel modules: shpchp

00:1d.0 USB controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 4: I/O ports at 1820 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.1 USB controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at 1840 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.2 USB controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 04) (prog-if 00 [UHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 18
	Region 4: I/O ports at 1860 [size=32]
	Kernel driver in use: uhci_hcd

00:1d.7 USB controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 04) (prog-if 20 [EHCI])
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 23
	Region 0: Memory at b0040000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Debug port: BAR=1 offset=00a0
	Kernel driver in use: ehci-pci

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d4) (prog-if 01 [Subtractive decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=06, subordinate=08, sec-latency=32
	I/O behind bridge: 00004000-00004fff
	Memory behind bridge: b8000000-b80fffff
	Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Subsystem: Matsushita Electric Industrial Co., Ltd. 82801 Mobile PCI Bridge

00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 17
	Region 0: I/O ports at 1c00 [size=256]
	Region 1: I/O ports at 18c0 [size=64]
	Region 2: Memory at b0040800 (32-bit, non-prefetchable) [size=512]
	Region 3: Memory at b0040400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: snd_intel8x0
	Kernel modules: snd_intel8x0

00:1e.3 Modem: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller (rev 04) (prog-if 00 [Generic])
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 17
	Region 0: I/O ports at 2400 [size=256]
	Region 1: I/O ports at 2000 [size=128]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: snd_intel8x0m
	Kernel modules: snd_intel8x0m

00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FBM (ICH6M) LPC Interface Bridge
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Kernel driver in use: lpc_ich
	Kernel modules: intel_rng, lpc_ich

00:1f.2 IDE interface: Intel Corporation 82801FBM (ICH6M) SATA Controller (rev 04) (prog-if 80 [ISA Compatibility mode-only controller, supports bus mastering])
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FBM (ICH6M) SATA Controller
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 0: I/O ports at 01f0 [size=8]
	Region 1: I/O ports at 03f4
	Region 2: I/O ports at 0170 [size=8]
	Region 3: I/O ports at 0374
	Region 4: I/O ports at 1890 [size=16]
	Capabilities: [70] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ata_piix

00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 04)
	Subsystem: Matsushita Electric Industrial Co., Ltd. 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at 18a0 [size=32]
	Kernel driver in use: i801_smbus
	Kernel modules: i2c_i801

02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8053 PCI-E Gigabit Ethernet Controller (rev 19)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 25
	Region 0: Memory at b4000000 (64-bit, non-prefetchable) [size=16K]
	Region 2: I/O ports at 3000 [size=256]
	[virtual] Expansion ROM at b4020000 [disabled] [size=128K]
	Capabilities: [48] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
	Capabilities: [50] Vital Product Data
		Product Name: Marvell Yukon 88E8053 Gigabit Ethernet Controller
		Read-only fields:
			[PN] Part number: Yukon 88E8053
			[EC] Engineering changes: Rev. 1.9
			[MN] Manufacture ID: 4d 61 72 76 65 6c 6c
			[SN] Serial number: AbCdEfG962650
			[CP] Extended capability: 01 10 cc 03
			[RV] Reserved: checksum good, 9 byte(s) reserved
		Read/write fields:
			[RW] Read-write area: 121 byte(s) free
		End
	Capabilities: [5c] MSI: Enable+ Count=1/2 Maskable- 64bit+
		Address: 00000000fee0100c  Data: 4122
	Capabilities: [e0] Express (v1) Legacy Endpoint, MSI 00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset-
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr+ NoSnoop-
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <256ns, L1 unlimited
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 128 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
	Capabilities: [100 v1] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		AERCap:	First Error Pointer: 1f, GenCap- CGenEn- ChkCap- ChkEn-
	Kernel driver in use: sky2
	Kernel modules: sky2

06:01.0 CardBus bridge: Ricoh Co Ltd RL5c476 II (rev 8b)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Panasonic CF-Y5 laptop
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 168
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at b8000000 (32-bit, non-prefetchable) [size=4K]
	Bus: primary=06, secondary=07, subordinate=07, sec-latency=176
	Memory window 0: 84000000-87ffffff (prefetchable)
	Memory window 1: 88000000-8bffffff
	I/O window 0: 00004000-000040ff
	I/O window 1: 00004400-000044ff
	BridgeCtl: Parity- SERR- ISA- VGA- MAbort- >Reset- 16bInt- PostWrite+
	16-bit legacy interface ports at 0001
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME+
		Bridge: PM- B3+
	Kernel driver in use: yenta_cardbus
	Kernel modules: yenta_socket

06:01.1 SD Host controller: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter (rev 11)
	Subsystem: Matsushita Electric Industrial Co., Ltd. Panasonic CF-Y5 laptop
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32
	Interrupt: pin C routed to IRQ 19
	Region 0: Memory at b8002000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [80] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
	Kernel driver in use: sdhci-pci
	Kernel modules: sdhci_pci

06:02.0 Network controller: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection (rev 05)
	Subsystem: Intel Corporation PRO/Wireless 2915ABG [Calexico2] Network Connection
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32 (750ns min, 6000ns max), Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at b8003000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
	Kernel driver in use: ipw2200
	Kernel modules: ipw2200, wl

07:00.0 USB controller: NEC Corporation OHCI USB Controller (rev 43) (prog-if 10 [OHCI])
	Subsystem: Adaptec OHCI USB Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64 (250ns min, 10500ns max), Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at 88000000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ohci-pci

07:00.1 USB controller: NEC Corporation OHCI USB Controller (rev 43) (prog-if 10 [OHCI])
	Subsystem: Adaptec OHCI USB Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64 (250ns min, 10500ns max), Cache Line Size: 32 bytes
	Interrupt: pin B routed to IRQ 20
	Region 0: Memory at 88001000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+
	Kernel driver in use: ohci-pci

07:00.2 USB controller: NEC Corporation uPD72010x USB 2.0 Controller (rev 04) (prog-if 20 [EHCI])
	Subsystem: Adaptec uPD72010x USB 2.0 Controller
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 68 (4000ns min, 8500ns max), Cache Line Size: 32 bytes
	Interrupt: pin C routed to IRQ 20
	Region 0: Memory at 88002000 (32-bit, non-prefetchable) [size=256]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Kernel driver in use: ehci-pci
	
	lspcmcia -v -v
Socket 0 Bridge:   	[yenta_cardbus] 	(bus ID: 0000:06:01.0)
	Configuration:	state: on	ready: yes

			Voltage: 3.3V
 Vcc: 3.3V
 Vpp: 3.3V

			Available IRQs: 3, 4, 7, 10, 11
			Available ioports:	0x00000100 - 0x000003af
						0x000003e0 - 0x000004ff
						0x00000820 - 0x000008ff
						0x00000a00 - 0x00000aff
						0x00000c00 - 0x00000cf7
						0x00004000 - 0x00004fff
						
			Available iomem:	0x000c8000 - 0x000cbfff
						0x000d4000 - 0x000dffff
						0xa0000000 - 0xa0ffffff
						0xb8010000 - 0xb80fffff
						
  CardBus card -- see "lspci" for more information