* [PATCH v2 0/3] Misc bug fixes in mtk power domain driver
@ 2021-02-01 12:14 Bilal Wasim
2021-02-01 12:14 ` [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr Bilal Wasim
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Bilal Wasim @ 2021-02-01 12:14 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, matthias.bgg,
enric.balletbo, hsinyi, weiyi.lu
Incorrect mask for the "bus_prot_clr" field meant that imgtec
gpu power domain (mfg_async) was not powered up correctly, causing
failure in driver booting. Fixing this and also adding "domain_suuply"
capability to "mfg_async" power domain (for mt8173) as imgtec gpu
needs da9211 regulator to be enabled before enabling this subdomain.
Tested with mt8173 elm chromebook.
Bilal Wasim (3):
soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
arm64: dts: mediatek: mt8173: Add domain supply for mfg_async
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
5 files changed, 11 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
2021-02-01 12:14 [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
@ 2021-02-01 12:14 ` Bilal Wasim
2021-03-31 11:01 ` Matthias Brugger
2021-02-01 12:14 ` [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD Bilal Wasim
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Bilal Wasim @ 2021-02-01 12:14 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, matthias.bgg,
enric.balletbo, hsinyi, weiyi.lu
When "bus_prot_reg_update" is true, the driver should use
INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
protection. However, the driver does not use this mask for
clearing bus protection which causes failure when booting
the imgtec gpu.
Corrected and tested with mt8173 chromebook.
Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 141dc76054e6..7454c0b4f768 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -60,7 +60,7 @@
#define BUS_PROT_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \
INFRA_TOPAXI_PROTECTEN, \
- INFRA_TOPAXI_PROTECTEN_CLR, \
+ INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTSTA1)
struct scpsys_bus_prot_data {
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
2021-02-01 12:14 [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
2021-02-01 12:14 ` [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr Bilal Wasim
@ 2021-02-01 12:14 ` Bilal Wasim
2021-02-01 16:56 ` kernel test robot
2021-03-31 10:48 ` Matthias Brugger
2021-02-01 12:14 ` [PATCH v2 3/3] arm64: dts: mediatek: mt8173: Add domain supply for mfg_async Bilal Wasim
2021-02-16 11:59 ` [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
3 siblings, 2 replies; 9+ messages in thread
From: Bilal Wasim @ 2021-02-01 12:14 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, matthias.bgg,
enric.balletbo, hsinyi, weiyi.lu
The mfg_async power domain in mt8173 is used to power up imgtec
gpu. This domain requires the da9211 regulator to be enabled before
the power domain can be enabled successfully.
Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
index 3e8ee5dabb43..065b8195e7d6 100644
--- a/drivers/soc/mediatek/mt8173-pm-domains.h
+++ b/drivers/soc/mediatek/mt8173-pm-domains.h
@@ -63,6 +63,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
+ .caps = MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.sta_mask = PWR_STATUS_MFG_2D,
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] arm64: dts: mediatek: mt8173: Add domain supply for mfg_async
2021-02-01 12:14 [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
2021-02-01 12:14 ` [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr Bilal Wasim
2021-02-01 12:14 ` [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD Bilal Wasim
@ 2021-02-01 12:14 ` Bilal Wasim
2021-02-16 11:59 ` [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
3 siblings, 0 replies; 9+ messages in thread
From: Bilal Wasim @ 2021-02-01 12:14 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, matthias.bgg,
enric.balletbo, hsinyi, weiyi.lu
da9211 regulator needs to be enabled before enabling the mfg_async power
domain. Otherwise the subdomain is not enabled and causes failure in
imgtec gpu driver boot.
Add the "domain-supply" property to the "mfg_async" node in DT.
Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
---
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
index 21452c51a20a..a8efff2071bf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
@@ -157,6 +157,10 @@ hdmi_connector_in: endpoint {
};
};
+&mfg_async {
+ domain-supply = <&da9211_vgpu_reg>;
+};
+
&cec {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 6dffada2e66b..c8eece8f5beb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -62,6 +62,10 @@ usb_p0_vbus: regulator@1 {
};
};
+&mfg_async {
+ domain-supply = <&da9211_vgpu_reg>;
+};
+
&cec {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 7fa870e4386a..31d23099df90 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -504,7 +504,7 @@ power-domain@MT8173_POWER_DOMAIN_USB {
reg = <MT8173_POWER_DOMAIN_USB>;
#power-domain-cells = <0>;
};
- power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
+ mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&clk26m>;
clock-names = "mfg";
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
2021-02-01 12:14 ` [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD Bilal Wasim
@ 2021-02-01 16:56 ` kernel test robot
2021-03-31 10:48 ` Matthias Brugger
1 sibling, 0 replies; 9+ messages in thread
From: kernel test robot @ 2021-02-01 16:56 UTC (permalink / raw)
To: Bilal Wasim, linux-mediatek, linux-arm-kernel, linux-kernel,
matthias.bgg, enric.balletbo, hsinyi, weiyi.lu
Cc: kbuild-all, clang-built-linux
[-- Attachment #1: Type: text/plain, Size: 5832 bytes --]
Hi Bilal,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on keystone/next soc/for-next rockchip/for-next arm64/for-next/core shawnguo/for-next clk/clk-next kvmarm/next next-20210125]
[cannot apply to xlnx/master arm/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Bilal-Wasim/Misc-bug-fixes-in-mtk-power-domain-driver/20210201-201713
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc64-randconfig-r023-20210201 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 275c6af7d7f1ed63a03d05b4484413e447133269)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc64 cross compiling tool for clang build
# apt-get install binutils-powerpc64-linux-gnu
# https://github.com/0day-ci/linux/commit/6ec2b10aece5d26e1ad75ef4b9bbe1260f6c68de
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Bilal-Wasim/Misc-bug-fixes-in-mtk-power-domain-driver/20210201-201713
git checkout 6ec2b10aece5d26e1ad75ef4b9bbe1260f6c68de
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/soc/mediatek/mtk-pm-domains.c:18:
>> drivers/soc/mediatek/mt8173-pm-domains.h:66:11: error: use of undeclared identifier 'MTK_SCPD_DOMAIN_SUPPLY'
.caps = MTK_SCPD_DOMAIN_SUPPLY,
^
>> drivers/soc/mediatek/mt8173-pm-domains.h:90:17: error: invalid application of 'sizeof' to an incomplete type 'const struct scpsys_domain_data []'
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/kernel.h:49:32: note: expanded from macro 'ARRAY_SIZE'
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
^~~~~
2 errors generated.
vim +/MTK_SCPD_DOMAIN_SUPPLY +66 drivers/soc/mediatek/mt8173-pm-domains.h
8
9 /*
10 * MT8173 power domain support
11 */
12
13 static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
14 [MT8173_POWER_DOMAIN_VDEC] = {
15 .sta_mask = PWR_STATUS_VDEC,
16 .ctl_offs = SPM_VDE_PWR_CON,
17 .sram_pdn_bits = GENMASK(11, 8),
18 .sram_pdn_ack_bits = GENMASK(12, 12),
19 },
20 [MT8173_POWER_DOMAIN_VENC] = {
21 .sta_mask = PWR_STATUS_VENC,
22 .ctl_offs = SPM_VEN_PWR_CON,
23 .sram_pdn_bits = GENMASK(11, 8),
24 .sram_pdn_ack_bits = GENMASK(15, 12),
25 },
26 [MT8173_POWER_DOMAIN_ISP] = {
27 .sta_mask = PWR_STATUS_ISP,
28 .ctl_offs = SPM_ISP_PWR_CON,
29 .sram_pdn_bits = GENMASK(11, 8),
30 .sram_pdn_ack_bits = GENMASK(13, 12),
31 },
32 [MT8173_POWER_DOMAIN_MM] = {
33 .sta_mask = PWR_STATUS_DISP,
34 .ctl_offs = SPM_DIS_PWR_CON,
35 .sram_pdn_bits = GENMASK(11, 8),
36 .sram_pdn_ack_bits = GENMASK(12, 12),
37 .bp_infracfg = {
38 BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
39 MT8173_TOP_AXI_PROT_EN_MM_M1),
40 },
41 },
42 [MT8173_POWER_DOMAIN_VENC_LT] = {
43 .sta_mask = PWR_STATUS_VENC_LT,
44 .ctl_offs = SPM_VEN2_PWR_CON,
45 .sram_pdn_bits = GENMASK(11, 8),
46 .sram_pdn_ack_bits = GENMASK(15, 12),
47 },
48 [MT8173_POWER_DOMAIN_AUDIO] = {
49 .sta_mask = PWR_STATUS_AUDIO,
50 .ctl_offs = SPM_AUDIO_PWR_CON,
51 .sram_pdn_bits = GENMASK(11, 8),
52 .sram_pdn_ack_bits = GENMASK(15, 12),
53 },
54 [MT8173_POWER_DOMAIN_USB] = {
55 .sta_mask = PWR_STATUS_USB,
56 .ctl_offs = SPM_USB_PWR_CON,
57 .sram_pdn_bits = GENMASK(11, 8),
58 .sram_pdn_ack_bits = GENMASK(15, 12),
59 .caps = MTK_SCPD_ACTIVE_WAKEUP,
60 },
61 [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
62 .sta_mask = PWR_STATUS_MFG_ASYNC,
63 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
64 .sram_pdn_bits = GENMASK(11, 8),
65 .sram_pdn_ack_bits = 0,
> 66 .caps = MTK_SCPD_DOMAIN_SUPPLY,
67 },
68 [MT8173_POWER_DOMAIN_MFG_2D] = {
69 .sta_mask = PWR_STATUS_MFG_2D,
70 .ctl_offs = SPM_MFG_2D_PWR_CON,
71 .sram_pdn_bits = GENMASK(11, 8),
72 .sram_pdn_ack_bits = GENMASK(13, 12),
73 },
74 [MT8173_POWER_DOMAIN_MFG] = {
75 .sta_mask = PWR_STATUS_MFG,
76 .ctl_offs = SPM_MFG_PWR_CON,
77 .sram_pdn_bits = GENMASK(13, 8),
78 .sram_pdn_ack_bits = GENMASK(21, 16),
79 .bp_infracfg = {
80 BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
81 MT8173_TOP_AXI_PROT_EN_MFG_M0 |
82 MT8173_TOP_AXI_PROT_EN_MFG_M1 |
83 MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
84 },
85 },
86 };
87
88 static const struct scpsys_soc_data mt8173_scpsys_data = {
89 .domains_data = scpsys_domain_data_mt8173,
> 90 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
91 .pwr_sta_offs = SPM_PWR_STATUS,
92 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
93 };
94
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 30296 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] Misc bug fixes in mtk power domain driver
2021-02-01 12:14 [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
` (2 preceding siblings ...)
2021-02-01 12:14 ` [PATCH v2 3/3] arm64: dts: mediatek: mt8173: Add domain supply for mfg_async Bilal Wasim
@ 2021-02-16 11:59 ` Bilal Wasim
2021-03-31 8:46 ` Enric Balletbo Serra
3 siblings, 1 reply; 9+ messages in thread
From: Bilal Wasim @ 2021-02-16 11:59 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, matthias.bgg,
enric.balletbo, hsinyi, weiyi.lu
ping - can this series be merged ?
On Mon, 1 Feb 2021 17:14:13 +0500
Bilal Wasim <bilalwasim676@gmail.com> wrote:
> Incorrect mask for the "bus_prot_clr" field meant that imgtec
> gpu power domain (mfg_async) was not powered up correctly, causing
> failure in driver booting. Fixing this and also adding "domain_suuply"
> capability to "mfg_async" power domain (for mt8173) as imgtec gpu
> needs da9211 regulator to be enabled before enabling this subdomain.
>
> Tested with mt8173 elm chromebook.
>
> Bilal Wasim (3):
> soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
> soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
> arm64: dts: mediatek: mt8173: Add domain supply for mfg_async
>
> arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> 5 files changed, 11 insertions(+), 2 deletions(-)
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] Misc bug fixes in mtk power domain driver
2021-02-16 11:59 ` [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
@ 2021-03-31 8:46 ` Enric Balletbo Serra
0 siblings, 0 replies; 9+ messages in thread
From: Enric Balletbo Serra @ 2021-03-31 8:46 UTC (permalink / raw)
To: Bilal Wasim
Cc: moderated list:ARM/Mediatek SoC support, Linux ARM, linux-kernel,
Matthias Brugger, Enric Balletbo i Serra, Hsin-Yi Wang, Weiyi Lu
Hi Bilal,
Thank you for your patch.
Missatge de Bilal Wasim <bilalwasim676@gmail.com> del dia dt., 16 de
febr. 2021 a les 13:00:
>
>
> ping - can this series be merged ?
>
This series breaks my display with the current mainline. With those
patches applied my display doesn't turn on and I get the following
error. Note that in mainline we don't have a gpu working driver.
[ 66.979546] ------------[ cut here ]------------
[ 66.984234] [CRTC:43:crtc-0] vblank wait timed out
[ 66.989070] WARNING: CPU: 2 PID: 432 at
drivers/gpu/drm/drm_atomic_helper.c:1512
drm_atomic_helper_wait_for_vblanks.part.0+0x278/0x2a0
[ 67.001166] Modules linked in: af_alg mwifiex_sdio mwifiex
btmrvl_sdio btmrvl bluetooth mtk_vcodec_dec mtk_vcodec_enc cfg80211
uvcvideo mtk
_mdp mtk_vcodec_common v4l2_h264 v4l2_mem2mem videobuf2_dma_contig
videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 videobuf2_common
videodev
smsc ecdh_generic mt8173_rt5650 ecc smsc95xx rfkill mc usbnet
cros_ec_sensors snd_soc_rt5645 cros_ec_sensors_core elants_i2c
mt8173_afe_pcm c
rct10dif_ce elan_i2c industrialio_triggered_buffer sbs_battery
cros_ec_chardev kfifo_buf cros_usbpd_charger cros_usbpd_logger
snd_soc_rl6231 s
nd_soc_mtk_common mtk_vpu display_connector pwm_bl fuse ip_tables x_tables ipv6
[ 67.057686] CPU: 2 PID: 432 Comm: gnome-shell Tainted: G W
5.12.0-rc5+ #25
[ 67.065861] Hardware name: Google Elm (DT)
[ 67.069950] pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--)
[ 67.075952] pc :
drm_atomic_helper_wait_for_vblanks.part.0+0x278/0x2a0
[ 67.082477] lr :
drm_atomic_helper_wait_for_vblanks.part.0+0x278/0x2a0
[ 67.089000] sp : ffff800012c23aa0
[ 67.092308] x29: ffff800012c23aa0 x28: 0000000000000004
[ 67.097621] x27: 0000000000000000 x26: 0000000000000001
[ 67.102933] x25: 0000000000000038 x24: ffff0000c4726000
[ 67.108246] x23: 0000000000000001 x22: 0000000000000000
[ 67.113558] x21: ffff0000cabbd880 x20: ffff0000c3bd8080
[ 67.118869] x19: 0000000000000000 x18: 0000000000000000
[ 67.124180] x17: 0000000000000010 x16: 0000000000000000
[ 67.129492] x15: 0000000000000030 x14: ffffffffffffffff
[ 67.134805] x13: ffff800011ce2680 x12: 00000000000007c2
[ 67.140117] x11: 0000000000000296 x10: ffff800011d3a680
[ 67.145428] x9 : 00000000fffff000 x8 : ffff800011ce2680
[ 67.150741] x7 : ffff800011d3a680 x6 : 0000000000000000
[ 67.156052] x5 : 0000000000000000 x4 : ffff0000ff77c918
[ 67.161364] x3 : ffff0000ff783878 x2 : 0000000000000000
[ 67.166674] x1 : 0000000000000000 x0 : ffff0000cc660000
[ 67.171985] Call trace:
[ 67.174426] drm_atomic_helper_wait_for_vblanks.part.0+0x278/0x2a0
[ 67.180603] drm_atomic_helper_commit_tail_rpm+0x80/0xa0
[ 67.185913] commit_tail+0xa0/0x180
[ 67.189399] drm_atomic_helper_commit+0x160/0x370
[ 67.194100] drm_atomic_commit+0x4c/0x60
[ 67.198022] drm_mode_obj_set_property_ioctl+0x164/0x460
[ 67.203330] drm_ioctl_kernel+0xc4/0x11c
[ 67.207251] drm_ioctl+0x210/0x430
[ 67.210650] __arm64_sys_ioctl+0xa8/0xec
...
Thanks,
Enric
> On Mon, 1 Feb 2021 17:14:13 +0500
> Bilal Wasim <bilalwasim676@gmail.com> wrote:
>
> > Incorrect mask for the "bus_prot_clr" field meant that imgtec
> > gpu power domain (mfg_async) was not powered up correctly, causing
> > failure in driver booting. Fixing this and also adding "domain_suuply"
> > capability to "mfg_async" power domain (for mt8173) as imgtec gpu
> > needs da9211 regulator to be enabled before enabling this subdomain.
> >
> > Tested with mt8173 elm chromebook.
> >
> > Bilal Wasim (3):
> > soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
> > soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
> > arm64: dts: mediatek: mt8173: Add domain supply for mfg_async
> >
> > arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> > drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> > drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> > 5 files changed, 11 insertions(+), 2 deletions(-)
> >
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
2021-02-01 12:14 ` [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD Bilal Wasim
2021-02-01 16:56 ` kernel test robot
@ 2021-03-31 10:48 ` Matthias Brugger
1 sibling, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2021-03-31 10:48 UTC (permalink / raw)
To: Bilal Wasim, linux-mediatek, linux-arm-kernel, linux-kernel,
enric.balletbo, hsinyi, weiyi.lu
On 01/02/2021 13:14, Bilal Wasim wrote:
> The mfg_async power domain in mt8173 is used to power up imgtec
> gpu. This domain requires the da9211 regulator to be enabled before
> the power domain can be enabled successfully.
>
> Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
> drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
> index 3e8ee5dabb43..065b8195e7d6 100644
> --- a/drivers/soc/mediatek/mt8173-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8173-pm-domains.h
> @@ -63,6 +63,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> + .caps = MTK_SCPD_DOMAIN_SUPPLY,
Hm, I think the problem here is, that we don't find the regulator
"domain-supply" in the DTS. And that provokes that we error out on all power
domains. Not sure if we should fix that somehow, so that a missing regulator
will only affect one power domain (and it's childs).
Regards,
Matthias
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .sta_mask = PWR_STATUS_MFG_2D,
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
2021-02-01 12:14 ` [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr Bilal Wasim
@ 2021-03-31 11:01 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2021-03-31 11:01 UTC (permalink / raw)
To: Bilal Wasim, linux-mediatek, linux-arm-kernel, linux-kernel,
enric.balletbo, hsinyi, weiyi.lu, Fabien Parent
On 01/02/2021 13:14, Bilal Wasim wrote:
> When "bus_prot_reg_update" is true, the driver should use
> INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
> protection. However, the driver does not use this mask for
> clearing bus protection which causes failure when booting
> the imgtec gpu.
>
> Corrected and tested with mt8173 chromebook.
>
> Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
BUS_PROT_UPDATE_TOPAXI is also used in mt8167. I'd need feedback if this would
break that SoC before accepting this patch.
Regards,
Matthias
> ---
> drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 141dc76054e6..7454c0b4f768 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -60,7 +60,7 @@
> #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> BUS_PROT_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> - INFRA_TOPAXI_PROTECTEN_CLR, \
> + INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTSTA1)
>
> struct scpsys_bus_prot_data {
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-03-31 11:02 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-01 12:14 [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
2021-02-01 12:14 ` [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr Bilal Wasim
2021-03-31 11:01 ` Matthias Brugger
2021-02-01 12:14 ` [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD Bilal Wasim
2021-02-01 16:56 ` kernel test robot
2021-03-31 10:48 ` Matthias Brugger
2021-02-01 12:14 ` [PATCH v2 3/3] arm64: dts: mediatek: mt8173: Add domain supply for mfg_async Bilal Wasim
2021-02-16 11:59 ` [PATCH v2 0/3] Misc bug fixes in mtk power domain driver Bilal Wasim
2021-03-31 8:46 ` Enric Balletbo Serra
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