* [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp
@ 2014-09-03 15:37 Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Gabriel FERNANDEZ
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez
Changes in v2:
from Kishon
- create a common file for phy
- cosmetic correction in phy-miphy28lp.txt file
- change initialization of the registers
from Srinivas
- rename and simplify a procedure
- Add Tx impedance and SSC support for SATA and PCI
Hi Kishon,
The goal of this series is to add the support of MiPHY28lp Generic PHY.
I tried to be as close as possible to the MiPHY365x Lee Jones proposal.
Best Regards
Gabriel.
Gabriel Fernandez (8):
phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines
phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe &
USB3) PHY
phy: miphy28lp: Add SSC support for SATA
phy: miphy28lp: Add SSC support for PCIE
phy: miphy28lp: Tune tx impedance across Soc cuts
.../devicetree/bindings/phy/phy-miphy28lp.txt | 128 +++
arch/arm/boot/dts/stih407-b2120.dts | 11 +
arch/arm/boot/dts/stih407.dtsi | 65 ++
arch/arm/configs/multi_v7_defconfig | 1 +
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy28lp.c | 1076 ++++++++++++++++++++
include/dt-bindings/phy/phy-miphy.h | 12 +
8 files changed, 1302 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
create mode 100644 drivers/phy/phy-miphy28lp.c
create mode 100644 include/dt-bindings/phy/phy-miphy.h
--
1.9.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-08 14:33 ` Kishon Vijay Abraham I
2014-09-03 15:37 ` [PATCH v2 2/8] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines Gabriel FERNANDEZ
` (6 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
or USB3 devices.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++
1 file changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
new file mode 100644
index 0000000..5e307af
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -0,0 +1,126 @@
+STMicroelectronics STi MIPHY28LP PHY binding
+============================================
+
+This binding describes a miphy device that is used to control PHY hardware
+for SATA, PCIe or USB3.
+
+Required properties (controller (parent) node):
+- compatible : Should be "st,miphy28lp-phy"
+- st,syscfg : Should be a phandle of the system configuration register group
+ which contain the SATA, PCIe or USB3 mode setting bits
+
+Required nodes : A sub-node is required for each channel the controller
+ provides. Address range information including the usual
+ 'reg' and 'reg-names' properties are used inside these
+ nodes to describe the controller's topology. These nodes
+ are translated by the driver's .xlate() function.
+
+Required properties (port (child) node):
+- #phy-cells : Should be 1 (See second example)
+ Cell after port phandle is device type from:
+ - MIPHY_TYPE_SATA
+ - MIPHY_TYPE_PCI
+ - MIPHY_TYPE_USB3
+- reg : Address and length of the register set for the device
+- reg-names : The names of the register addresses corresponding to the registers
+ filled in "reg". Is can also contain the offset of the system configuration
+ registers used as glue-logic to setup the device for SATA/PCIe or USB3
+ devices.
+- resets : phandle to the parent reset controller.
+- reset-names : Associated name must be "miphy-sw-rst".
+
+Optional properties (port (child) node):
+- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
+ is not available in all the MiPHY. For example, for STiH407, only the
+ MiPHY0 has this bit.
+- st,osc-force-ext : to select the external oscillator. This can change from
+ different MiPHY inside the same SoC.
+- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
+ register.
+- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
+ line).
+
+example:
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>,
+ <0x114 0x4>, /* sysctrl MiPHY cntrl */
+ <0x818 0x4>, /* sysctrl MiPHY status*/
+ <0xe0 0x4>, /* sysctrl PCIe */
+ <0xec 0x4>; /* sysctrl SATA */
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+ st,osc-rdy;
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>,
+ <0x118 0x4>,
+ <0x81c 0x4>,
+ <0xe4 0x4>,
+ <0xf0 0x4>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+ st,osc-force-ext;
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+ };
+
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f90000 0xff>,
+ <0x11c 0x4>,
+ <0x820 0x4>;
+ reg-names = "pipew",
+ "usb3-up",
+ "miphy-ctrl-glue",
+ "miphy-status-glue";
+ #phy-cells = <1>;
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+ };
+ };
+
+
+Specifying phy control of devices
+=================================
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the miphy device node and an index
+specifying which configuration to use, as described in phy-bindings.txt.
+
+example:
+ sata0: sata@9b20000 {
+ ...
+ phys = <&phy_port0 MIPHY_TYPE_SATA>;
+ ...
+ };
+
+Macro definitions for the supported miphy configuration can be found in:
+
+include/dt-bindings/phy/phy-miphy28lp.h
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/8] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY Gabriel FERNANDEZ
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, alexandre torgue
This provides the shared header file which will be reference from both
the MiPHY28lp driver and its associated Device Tree node(s).
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
include/dt-bindings/phy/phy-miphy.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 include/dt-bindings/phy/phy-miphy.h
diff --git a/include/dt-bindings/phy/phy-miphy.h b/include/dt-bindings/phy/phy-miphy.h
new file mode 100644
index 0000000..9bc49b9
--- /dev/null
+++ b/include/dt-bindings/phy/phy-miphy.h
@@ -0,0 +1,12 @@
+/*
+ * This header provides constants for the phy framework
+ * based on the STMicroelectronics miphxxxx.
+ */
+#ifndef _DT_BINDINGS_PHY_MIPHY
+#define _DT_BINDINGS_PHY_MIPHY
+
+#define MIPHY_TYPE_SATA 1
+#define MIPHY_TYPE_PCIE 2
+#define MIPHY_TYPE_USB 3
+
+#endif /* _DT_BINDINGS_PHY_MIPHY */
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 2/8] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-08 15:12 ` Kishon Vijay Abraham I
2014-09-03 15:37 ` [PATCH v2 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp Gabriel FERNANDEZ
` (4 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
or USB3 devices.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
drivers/phy/Kconfig | 8 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy28lp.c | 985 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 994 insertions(+)
create mode 100644 drivers/phy/phy-miphy28lp.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 0dd7427..2053f72 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -230,4 +230,12 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_MIPHY28LP
+ tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
+ depends on ARCH_STI
+ depends on GENERIC_PHY
+ help
+ Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
+ that is part of STMicroelectronics STiH407 SoC.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 95c69ed..f7e7c59 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o
obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
new file mode 100644
index 0000000..aa36cea
--- /dev/null
+++ b/drivers/phy/phy-miphy28lp.c
@@ -0,0 +1,985 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics
+ *
+ * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
+ *
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/phy/phy-miphy.h>
+
+/* MiPHY mask registers */
+#define MIPHY_PHY_RDY 0x01
+#define MIPHY_PLL_HFC_RDY 0x06
+#define MIPHY_COMP_DONE 0x80
+
+#define MIPHY_PX_RX_POL BIT(5)
+
+/* MiPHY registers */
+#define MIPHY_CONF_RESET 0x00
+#define MIPHY_RESET 0x01
+#define MIPHY_STATUS_1 0x02
+#define MIPHY_CONTROL 0x04
+#define MIPHY_BOUNDARY_SEL 0x0a
+#define MIPHY_BOUNDARY_1 0x0b
+#define MIPHY_BOUNDARY_2 0x0c
+#define MIPHY_PLL_CLKREF_FREQ 0x0d
+#define MIPHY_SPEED 0x0e
+#define MIPHY_CONF 0x0f
+#define MIPHY_CTRL_TEST_SEL 0x20
+#define MIPHY_CTRL_TEST_1 0x21
+#define MIPHY_CTRL_TEST_2 0x22
+#define MIPHY_CTRL_TEST_3 0x23
+#define MIPHY_CTRL_TEST_4 0x24
+#define MIPHY_FEEDBACK_TEST 0x25
+#define MIPHY_DEBUG_BUS 0x26
+#define MIPHY_DEBUG_STATUS_MSB 0x27
+#define MIPHY_DEBUG_STATUS_LSB 0x28
+#define MIPHY_PWR_RAIL_1 0x29
+#define MIPHY_PWR_RAIL_2 0x2a
+#define MIPHY_SYNCHAR_CONTROL 0x30
+#define MIPHY_COMP_FSM_1 0x3a
+#define MIPHY_COMP_FSM_6 0x3f
+#define MIPHY_COMP_POSTP 0x42
+#define MIPHY_TX_CTRL_1 0x49
+#define MIPHY_TX_CTRL_2 0x4a
+#define MIPHY_TX_CTRL_3 0x4b
+#define MIPHY_TX_CAL_MAN 0x4e
+#define MIPHY_TST_BIAS_BOOST_2 0x62
+#define MIPHY_BIAS_BOOST_1 0x63
+#define MIPHY_BIAS_BOOST_2 0x64
+#define MIPHY_RX_DESBUFF_FDB_2 0x67
+#define MIPHY_RX_DESBUFF_FDB_3 0x68
+#define MIPHY_SIGDET_COMPENS1 0x69
+#define MIPHY_SIGDET_COMPENS2 0x6a
+#define MIPHY_JITTER_PERIOD 0x6b
+#define MIPHY_JITTER_AMPLITUDE_1 0x6c
+#define MIPHY_JITTER_AMPLITUDE_2 0x6d
+#define MIPHY_JITTER_AMPLITUDE_3 0x6e
+#define MIPHY_RX_K_GAIN 0x78
+#define MIPHY_RX_BUFFER_CTRL 0x7a
+#define MIPHY_RX_VGA_GAIN 0x7b
+#define MIPHY_RX_EQU_GAIN_1 0x7f
+#define MIPHY_RX_EQU_GAIN_2 0x80
+#define MIPHY_RX_EQU_GAIN_3 0x81
+#define MIPHY_RX_CAL_CTRL_1 0x97
+#define MIPHY_RX_CAL_CTRL_2 0x98
+#define MIPHY_RX_CAL_OFFSET_CTRL 0x99
+#define MIPHY_RX_CAL_VGA_STEP 0x9a
+#define MIPHY_RX_CAL_EYE_MIN 0x9d
+#define MIPHY_RX_CAL_OPT_LENGTH 0x9f
+#define MIPHY_RX_LOCK_CTRL_1 0xc1
+#define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
+#define MIPHY_RX_LOCK_STEP 0xc4
+#define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
+#define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
+#define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
+#define MIPHY_RX_SIGDET_DATA_SEL 0xcc
+#define MIPHY_RX_POWER_CTRL_1 0xcd
+#define MIPHY_RX_POWER_CTRL_2 0xce
+#define MIPHY_PLL_CALSET_CTRL 0xd3
+#define MIPHY_PLL_CALSET_1 0xd4
+#define MIPHY_PLL_CALSET_2 0xd5
+#define MIPHY_PLL_CALSET_3 0xd6
+#define MIPHY_PLL_CALSET_4 0xd7
+#define MIPHY_PLL_SBR_1 0xe3
+#define MIPHY_PLL_SBR_2 0xe4
+#define MIPHY_PLL_SBR_3 0xe5
+#define MIPHY_PLL_SBR_4 0xe6
+#define MIPHY_PLL_COMMON_MISC_2 0xe9
+#define MIPHY_PLL_SPAREIN 0xeb
+
+/*
+ * On STiH407 the glue logic can be different among MiPHY devices; for example:
+ * MiPHY0: OSC_FORCE_EXT means:
+ * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
+ * MiPHY1: OSC_FORCE_EXT means:
+ * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
+ * Some devices have not the possibility to check if the osc is ready.
+ */
+#define MIPHY_OSC_FORCE_EXT BIT(3)
+#define MIPHY_OSC_RDY BIT(5)
+
+#define MIPHY_CTRL_MASK 0x0f
+#define MIPHY_CTRL_DEFAULT 0
+#define MIPHY_CTRL_SYNC_D_EN BIT(2)
+
+/* SATA / PCIe defines */
+#define SATA_CTRL_MASK 0x07
+#define PCIE_CTRL_MASK 0xff
+#define SATA_CTRL_SELECT_SATA 1
+#define SATA_CTRL_SELECT_PCIE 0
+#define SYSCFG_PCIE_PCIE_VAL 0x80
+#define SATA_SPDMODE 1
+
+struct miphy28lp_phy {
+ struct phy *phy;
+ struct miphy28lp_dev *phydev;
+ void __iomem *base;
+ void __iomem *pipebase;
+
+ bool osc_force_ext;
+ bool osc_rdy;
+ bool px_rx_pol_inv;
+
+ struct reset_control *miphy_rst;
+
+ u32 sata_gen;
+
+ /* Sysconfig registers offsets needed to configure the device */
+ u32 syscfg_miphy_ctrl;
+ u32 syscfg_miphy_status;
+ u32 syscfg_pci;
+ u32 syscfg_sata;
+ u8 type;
+};
+
+struct miphy28lp_dev {
+ struct device *dev;
+ struct regmap *regmap;
+ struct mutex miphy_mutex;
+ struct miphy28lp_phy **phys;
+};
+
+struct miphy_initval {
+ u16 reg;
+ u16 val;
+};
+
+enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
+
+static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" };
+
+static inline void miphy28lp_cfg_out_of_reset(struct miphy28lp_phy *miphy_phy)
+{
+ unsigned long finish = jiffies + 5 * HZ;
+ u8 mask = MIPHY_PLL_HFC_RDY;
+ u8 val;
+
+ do {
+ val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
+ if ((val & mask) != mask)
+ cpu_relax();
+ else
+ break;
+ } while (!time_after_eq(jiffies, finish));
+}
+
+static inline void miphy28lp_configure_reset(struct miphy28lp_phy *miphy_phy)
+{
+ void *base = miphy_phy->base;
+
+ /* Putting Macro in reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
+
+ /* Wait for a while */
+ usleep_range(10, 20); /* extra delay after resetting */
+}
+
+
+
+static inline void miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
+{
+ void __iomem *base = miphy_phy->base;
+
+ /* Putting Macro in reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
+
+ /* Wait for a while */
+ usleep_range(10, 20); /* extra delay after resetting */
+
+ /* Bringing the MIPHY-CPU registers out of reset */
+ writeb_relaxed(0x1c, base + MIPHY_CONTROL);
+
+ /* Applying PLL Settings */
+ writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
+ writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
+
+ /* PLL Ratio */
+ writeb_relaxed(0xc8, base + MIPHY_PLL_CALSET_1);
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_2);
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_3);
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_4);
+
+ /* Number of PLL Calibrations */
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
+
+ /* Unbanked Settings */
+ writeb_relaxed(0xd1, base + MIPHY_TX_CAL_MAN);
+ writeb_relaxed(0x1f, base + MIPHY_RX_CAL_OFFSET_CTRL);
+ writeb_relaxed(0x40, base + MIPHY_BOUNDARY_SEL);
+
+ /* Banked settings */
+ /* Gen 1 */
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+ writeb_relaxed(0x00, base + MIPHY_SPEED);
+ writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
+ writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
+
+ /* TX buffer Settings */
+ writeb_relaxed(0x53, base + MIPHY_TX_CTRL_2);
+ writeb_relaxed(0x00, base + MIPHY_TX_CTRL_3);
+
+ /* RX Buffer Settings */
+ writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
+ writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
+ writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
+ writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
+ writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
+
+ /* Gen 2 */
+ writeb_relaxed(0x01, base + MIPHY_CONF);
+ writeb_relaxed(0x05, base + MIPHY_SPEED);
+ writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
+ writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
+
+ /* TX buffer Settings */
+ writeb_relaxed(0x72, base + MIPHY_TX_CTRL_2);
+ writeb_relaxed(0x20, base + MIPHY_TX_CTRL_3);
+
+ /* RX Buffer Settings */
+ writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
+ writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
+ writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
+ writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
+ writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
+
+ /* Gen 3 */
+ writeb_relaxed(0x02, base + MIPHY_CONF);
+ writeb_relaxed(0x0a, base + MIPHY_SPEED);
+ writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
+ writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
+
+ /* TX buffer Settings */
+ writeb_relaxed(0xc0, base + MIPHY_TX_CTRL_2);
+ writeb_relaxed(0x20, base + MIPHY_TX_CTRL_3);
+
+ /* RX Buffer Settings */
+ writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
+ writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
+ writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
+ writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
+ writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
+
+ /* Power control */
+ writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
+
+ /* Macro out of reset */
+ writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
+
+ /* Poll for HFC ready after reset release */
+ /* Compensation measurement */
+ writeb_relaxed(0x05, base + MIPHY_RESET);
+ writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
+ writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
+ writeb_relaxed(0x00, base + MIPHY_RESET);
+ writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
+}
+
+static inline void miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
+{
+ void __iomem *base = miphy_phy->base;
+
+ /* Putting Macro in reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
+
+ /* Wait for a while */
+ usleep_range(10, 20); /* extra delay after resetting */
+
+ /* Bringing the MIPHY-CPU registers out of reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x14, base + MIPHY_CONTROL);
+ writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
+
+ /* Applying PLL Settings */
+ writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
+
+ /* PLL Ratio */
+ writeb_relaxed(0xa6, base + MIPHY_PLL_CALSET_1);
+ writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_2);
+ writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_3);
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_4);
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
+
+ writeb_relaxed(0xd1, base + MIPHY_TX_CAL_MAN);
+ writeb_relaxed(0x5f, base + MIPHY_RX_CAL_OFFSET_CTRL);
+ writeb_relaxed(0x40, base + MIPHY_BOUNDARY_SEL);
+
+ /* Banked settings */
+ /* Gen 1 */
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+
+ writeb_relaxed(0x05, base + MIPHY_SPEED);
+ writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
+ writeb_relaxed(0xa5, base + MIPHY_BIAS_BOOST_2);
+
+ /* TX buffer Settings */
+ writeb_relaxed(0x07, base + MIPHY_TX_CTRL_1);
+ writeb_relaxed(0x71, base + MIPHY_TX_CTRL_2);
+ writeb_relaxed(0x60, base + MIPHY_TX_CTRL_3);
+ writeb_relaxed(0x98, base + MIPHY_RX_K_GAIN);
+
+ /* RX Buffer Settings */
+ writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
+ writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
+ writeb_relaxed(0x79, base + MIPHY_RX_EQU_GAIN_1);
+ writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
+
+ /* Gen 2 */
+ writeb_relaxed(0x01, base + MIPHY_CONF);
+ writeb_relaxed(0x0a, base + MIPHY_SPEED);
+ writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
+ writeb_relaxed(0xa5, base + MIPHY_BIAS_BOOST_2);
+
+ /* TX buffer Settings */
+ writeb_relaxed(0x07, base + MIPHY_TX_CTRL_1);
+ writeb_relaxed(0x70, base + MIPHY_TX_CTRL_2);
+ writeb_relaxed(0x60, base + MIPHY_TX_CTRL_3);
+ writeb_relaxed(0xcc, base + MIPHY_RX_K_GAIN);
+
+ /* RX Buffer Settings */
+ writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
+ writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
+ writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
+ writeb_relaxed(0x07, base + MIPHY_RX_EQU_GAIN_2);
+
+ writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
+
+ /* Macro out of reset */
+ writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
+
+ /* Poll for HFC ready after reset release */
+ /* Compensation measurement */
+ writeb_relaxed(0x05, base + MIPHY_RESET);
+ writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
+ writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
+ writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
+
+ /* extra delay to wait pll lock */
+ usleep_range(100, 120);
+
+ writeb_relaxed(0x01, base + MIPHY_RESET);
+ writeb_relaxed(0x00, base + MIPHY_RESET);
+ writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
+ writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
+}
+
+static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
+{
+ void __iomem *base = miphy_phy->base;
+
+ /* Putting Macro in reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
+
+ /* Wait for a while */
+ usleep_range(10, 20); /* extra delay after resetting */
+
+ /* Bringing the MIPHY-CPU registers out of reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x1c, base + MIPHY_CONTROL);
+
+ /* PLL calibration */
+ writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
+ writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+ writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
+
+ writeb_relaxed(0x02, base + MIPHY_RX_SIGDET_SLEEP_OA);
+ writeb_relaxed(0x02, base + MIPHY_RX_SIGDET_SLEEP_SEL);
+ writeb_relaxed(0x02, base + MIPHY_RX_SIGDET_WAIT_SEL);
+ writeb_relaxed(0x0a, base + MIPHY_RX_SIGDET_DATA_SEL);
+
+ /* Writing The PLL Ratio */
+ writeb_relaxed(0xa6, base + MIPHY_PLL_CALSET_1);
+ writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_2);
+ writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_3);
+ writeb_relaxed(0x04, base + MIPHY_PLL_CALSET_4);
+ writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
+
+ /* Writing The Speed Rate */
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+ writeb_relaxed(0x0a, base + MIPHY_SPEED);
+
+ /* RX Channel compensation and calibration */
+ writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
+ writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
+ writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
+ writeb_relaxed(0x5f, base + MIPHY_RX_CAL_OFFSET_CTRL);
+
+ /* Channel compensation and calibration */
+ writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
+ writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
+
+ writeb_relaxed(0x05, base + MIPHY_RX_BUFFER_CTRL);
+ writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
+ writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
+
+ /* Enable GENSEL_SEL and SSC */
+ /* TX_SEL=0 swing preemp forced by pipe registres */
+ writeb_relaxed(0x11, base + MIPHY_BOUNDARY_SEL);
+
+ /* MIPHY Bias boost */
+ writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
+ writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
+
+ /* TX compensation offset to re-center TX impedance */
+ writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
+
+ /* SSC modulation */
+ writeb_relaxed(0x04, base + MIPHY_BOUNDARY_2);
+
+ /* MIPHY TX control */
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+ writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
+ writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
+ writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+ writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
+ writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
+
+ /* Rx PI controller settings */
+ writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
+
+ /* MIPHY RX input bridge control */
+ /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
+ writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
+ writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
+ writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
+
+ /* MIPHY Reset */
+ writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
+ writeb_relaxed(0x04, base + MIPHY_RESET);
+ writeb_relaxed(0x05, base + MIPHY_RESET);
+
+ writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
+ writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
+ writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
+ writeb_relaxed(0x01, base + MIPHY_RESET);
+
+ writeb_relaxed(0x00, base + MIPHY_RESET);
+ writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+ writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
+
+ writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+ writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
+ writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
+
+ writeb_relaxed(0x00, base + MIPHY_CONF);
+}
+
+static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
+{
+ unsigned long finish = jiffies + 5 * HZ;
+ u8 mask = MIPHY_PLL_HFC_RDY;
+ u8 val;
+
+ /*
+ * For PCIe and USB3 check only that PLL and HFC are ready
+ * For SATA check also that phy is ready!
+ */
+ if (miphy_phy->type == MIPHY_TYPE_SATA)
+ mask |= MIPHY_PHY_RDY;
+
+ do {
+ val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
+ if ((val & mask) != mask)
+ cpu_relax();
+ else
+ return 0;
+ } while (!time_after_eq(jiffies, finish));
+
+ return -EBUSY;
+}
+
+static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
+{
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ unsigned long finish = jiffies + 5 * HZ;
+ u32 val;
+
+ if (!miphy_phy->osc_rdy)
+ return 0;
+
+ if (!miphy_phy->syscfg_miphy_status)
+ return -EINVAL;
+
+ do {
+ regmap_read(miphy_dev->regmap, miphy_phy->syscfg_miphy_status,
+ &val);
+
+ if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
+ cpu_relax();
+ else
+ return 0;
+ } while (!time_after_eq(jiffies, finish));
+
+ return -EBUSY;
+}
+
+static int miphy28lp_get_resource_byname(struct device_node *child,
+ char *rname, struct resource *res)
+{
+ int index;
+
+ index = of_property_match_string(child, "reg-names", rname);
+ if (index < 0)
+ return -ENODEV;
+
+ return of_address_to_resource(child, index, res);
+}
+
+static int miphy28lp_get_one_addr(struct device *dev,
+ struct device_node *child, char *rname,
+ void __iomem **base)
+{
+ struct resource res;
+ int ret;
+
+ ret = miphy28lp_get_resource_byname(child, rname, &res);
+ if (!ret) {
+ *base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (!*base) {
+ dev_err(dev, "failed to ioremap %s address region\n"
+ , rname);
+ return -ENOENT;
+ }
+ }
+
+ return 0;
+}
+
+/* MiPHY reset and sysconf setup */
+static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
+{
+ int err;
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+
+ if (!miphy_phy->syscfg_miphy_ctrl)
+ return -EINVAL;
+
+ err = reset_control_assert(miphy_phy->miphy_rst);
+ if (err) {
+ dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
+ return err;
+ }
+
+ if (miphy_phy->osc_force_ext)
+ miphy_val |= MIPHY_OSC_FORCE_EXT;
+
+ regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_miphy_ctrl,
+ MIPHY_CTRL_MASK, miphy_val);
+
+ err = reset_control_deassert(miphy_phy->miphy_rst);
+ if (err) {
+ dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
+ return err;
+ }
+
+ return miphy_osc_is_ready(miphy_phy);
+}
+
+static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
+{
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ int err, sata_conf = SATA_CTRL_SELECT_SATA;
+ u8 val;
+
+ if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci)
+ || (!miphy_phy->base))
+ return -EINVAL;
+
+ dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
+
+ /* Configure the glue-logic */
+ sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
+
+ regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata,
+ SATA_CTRL_MASK, sata_conf);
+
+ regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci,
+ PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
+
+ /* MiPHY path and clocking init */
+ err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
+
+ if (err) {
+ dev_err(miphy_dev->dev, "SATA phy setup failed\n");
+ return err;
+ }
+
+ /* initialize miphy */
+ miphy28lp_configure_sata(miphy_phy);
+
+ if (miphy_phy->px_rx_pol_inv) {
+ /* Invert Rx polarity */
+ val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
+ val |= MIPHY_PX_RX_POL;
+ writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
+ }
+
+ return miphy_is_ready(miphy_phy);
+}
+
+static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
+{
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ unsigned long finish = jiffies + 5 * HZ;
+ int err;
+ u8 val;
+
+ if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci)
+ || (!miphy_phy->base) || (!miphy_phy->pipebase))
+ return -EINVAL;
+
+ dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
+
+ /* Configure the glue-logic */
+ regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata,
+ SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
+
+ regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci,
+ PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL);
+
+ /* MiPHY path and clocking init */
+ err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
+
+ if (err) {
+ dev_err(miphy_dev->dev, "PCIe phy setup failed\n");
+ return err;
+ }
+
+ /* initialize miphy */
+ miphy28lp_configure_pcie(miphy_phy);
+
+ /* Waiting for Compensation to complete */
+ do {
+ val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
+ if (time_after_eq(jiffies, finish))
+ return -EBUSY;
+ cpu_relax();
+ } while (!(val & MIPHY_COMP_DONE));
+
+ /* PIPE Wrapper Configuration */
+ writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
+ writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
+ writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
+ writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
+ writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshhold_0 */
+ writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
+
+ /* Wait for phy_ready */
+ return miphy_is_ready(miphy_phy);
+}
+
+static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
+{
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ int err;
+
+ if ((!miphy_phy->base) || (!miphy_phy->pipebase))
+ return -EINVAL;
+
+ dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
+
+ /* MiPHY path and clocking init */
+ err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
+
+ if (err) {
+ dev_err(miphy_dev->dev, "USB3 phy setup failed\n");
+ return err;
+ }
+
+ /* initialize miphy */
+ miphy28lp_configure_usb3(miphy_phy);
+
+ /* PIPE Wrapper Configuration */
+ writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
+ writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
+ writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
+ writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
+ writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
+ writeb_relaxed(0x60, miphy_phy->pipebase + 0x2a);
+
+ /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
+ writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
+ writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
+ writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
+ writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
+ writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
+ writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
+ writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
+ writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
+
+ return miphy_is_ready(miphy_phy);
+}
+
+static int miphy28lp_init(struct phy *phy)
+{
+ struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ int ret;
+
+ mutex_lock(&miphy_dev->miphy_mutex);
+
+ switch (miphy_phy->type) {
+
+ case MIPHY_TYPE_SATA:
+ ret = miphy28lp_init_sata(miphy_phy);
+ break;
+ case MIPHY_TYPE_PCIE:
+ ret = miphy28lp_init_pcie(miphy_phy);
+ break;
+ case MIPHY_TYPE_USB:
+ ret = miphy28lp_init_usb3(miphy_phy);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mutex_unlock(&miphy_dev->miphy_mutex);
+
+ return ret;
+}
+
+static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
+{
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ struct device_node *phynode = miphy_phy->phy->dev.of_node;
+ int err;
+
+ if (!miphy_phy->type || (miphy_phy->type > MIPHY_TYPE_USB))
+ return -EINVAL;
+
+ err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,
+ miphy_type_name[miphy_phy->type - MIPHY_TYPE_SATA],
+ &miphy_phy->base);
+ if (err)
+ return err;
+
+ if ((miphy_phy->type == MIPHY_TYPE_PCIE) ||
+ (miphy_phy->type == MIPHY_TYPE_USB)) {
+ err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",
+ &miphy_phy->pipebase);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static struct phy *miphy28lp_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev);
+ struct miphy28lp_phy *miphy_phy = NULL;
+ struct device_node *phynode = args->np;
+ int ret, index = 0;
+
+ if (!of_device_is_available(phynode)) {
+ dev_warn(dev, "Requested PHY is disabled\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ if (args->args_count != 1) {
+ dev_err(dev, "Invalid number of cells in 'phy' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ for (index = 0; index < of_get_child_count(dev->of_node); index++)
+ if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
+ miphy_phy = miphy_dev->phys[index];
+ break;
+ }
+
+ if (!miphy_phy) {
+ dev_err(dev, "Failed to find appropriate phy\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ miphy_phy->type = args->args[0];
+
+ ret = miphy28lp_get_addr(miphy_phy);
+ if (ret < 0)
+ return ERR_PTR(ret);
+
+ return miphy_phy->phy;
+}
+
+static struct phy_ops miphy28lp_ops = {
+ .init = miphy28lp_init,
+ .owner = THIS_MODULE,
+};
+
+static int miphy28lp_probe_resets(struct device_node *node,
+ struct miphy28lp_phy *miphy_phy)
+{
+ struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
+ int err;
+
+ miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst");
+
+ if (IS_ERR(miphy_phy->miphy_rst)) {
+ dev_err(miphy_dev->dev,
+ "miphy soft reset control not defined\n");
+ return PTR_ERR(miphy_phy->miphy_rst);
+ }
+
+ err = reset_control_deassert(miphy_phy->miphy_rst);
+ if (err) {
+ dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int miphy28lp_of_probe(struct device_node *np,
+ struct miphy28lp_phy *miphy_phy)
+{
+ struct resource res;
+
+ miphy_phy->osc_force_ext =
+ of_property_read_bool(np, "st,osc-force-ext");
+
+ miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
+
+ miphy_phy->px_rx_pol_inv =
+ of_property_read_bool(np, "st,px_rx_pol_inv");
+
+ of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
+ if (!miphy_phy->sata_gen)
+ miphy_phy->sata_gen = SATA_GEN1;
+
+ if (!miphy28lp_get_resource_byname(np, "miphy-ctrl-glue", &res))
+ miphy_phy->syscfg_miphy_ctrl = res.start;
+
+ if (!miphy28lp_get_resource_byname(np, "miphy-status-glue", &res))
+ miphy_phy->syscfg_miphy_status = res.start;
+
+ if (!miphy28lp_get_resource_byname(np, "pcie-glue", &res))
+ miphy_phy->syscfg_pci = res.start;
+
+ if (!miphy28lp_get_resource_byname(np, "sata-glue", &res))
+ miphy_phy->syscfg_sata = res.start;
+
+
+ return 0;
+}
+
+static int miphy28lp_probe(struct platform_device *pdev)
+{
+ struct device_node *child, *np = pdev->dev.of_node;
+ struct miphy28lp_dev *miphy_dev;
+ struct phy_provider *provider;
+ struct phy *phy;
+ int chancount, port = 0;
+ int ret;
+
+ miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
+ if (!miphy_dev)
+ return -ENOMEM;
+
+ chancount = of_get_child_count(np);
+ miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount,
+ GFP_KERNEL);
+ if (!miphy_dev->phys)
+ return -ENOMEM;
+
+ miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
+ if (IS_ERR(miphy_dev->regmap)) {
+ dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
+ return PTR_ERR(miphy_dev->regmap);
+ }
+
+ miphy_dev->dev = &pdev->dev;
+
+ dev_set_drvdata(&pdev->dev, miphy_dev);
+
+ mutex_init(&miphy_dev->miphy_mutex);
+
+ for_each_child_of_node(np, child) {
+ struct miphy28lp_phy *miphy_phy;
+
+ miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
+ GFP_KERNEL);
+ if (!miphy_phy)
+ return -ENOMEM;
+
+ miphy_dev->phys[port] = miphy_phy;
+
+ phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops, NULL);
+ if (IS_ERR(phy)) {
+ dev_err(&pdev->dev, "failed to create PHY\n");
+ return PTR_ERR(phy);
+ }
+
+ miphy_dev->phys[port]->phy = phy;
+ miphy_dev->phys[port]->phydev = miphy_dev;
+
+ ret = miphy28lp_of_probe(child, miphy_phy);
+ if (ret)
+ return ret;
+
+ ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);
+ if (ret)
+ return ret;
+
+ phy_set_drvdata(phy, miphy_dev->phys[port]);
+ port++;
+
+ }
+
+ provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);
+ if (IS_ERR(provider))
+ return PTR_ERR(provider);
+
+ return 0;
+}
+
+static const struct of_device_id miphy28lp_of_match[] = {
+ {.compatible = "st,miphy28lp-phy", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, miphy28lp_of_match);
+
+static struct platform_driver miphy28lp_driver = {
+ .probe = miphy28lp_probe,
+ .driver = {
+ .name = "miphy28lp-phy",
+ .owner = THIS_MODULE,
+ .of_match_table = miphy28lp_of_match,
+ }
+};
+
+module_platform_driver(miphy28lp_driver);
+
+MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
` (2 preceding siblings ...)
2014-09-03 15:37 ` [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 5/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY Gabriel FERNANDEZ
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
arch/arm/boot/dts/stih407-b2120.dts | 11 +++++++
arch/arm/boot/dts/stih407.dtsi | 65 +++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92..d0837fb 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -74,5 +74,16 @@
st,i2c-min-scl-pulse-width-us = <0>;
st,i2c-min-sda-pulse-width-us = <5>;
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+
+ phy_port0: port@9b22000 {
+ st,osc-rdy;
+ };
+
+ phy_port1: port@9b2a000 {
+ st,osc-force-ext;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 4f9024f..b8cc9a3 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -259,5 +259,70 @@
status = "disabled";
};
+
+ miphy28lp_phy: miphy28lp@9b22000 {
+ compatible = "st,miphy28lp-phy";
+ st,syscfg = <&syscfg_core>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ phy_port0: port@9b22000 {
+ reg = <0x9b22000 0xff>,
+ <0x9b09000 0xff>,
+ <0x9b04000 0xff>,
+ <0x114 0x4>, /* sysctrl MiPHY cntrl */
+ <0x818 0x4>, /* sysctrl MiPHY status*/
+ <0xe0 0x4>, /* sysctrl PCIe */
+ <0xec 0x4>; /* sysctrl SATA */
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+ };
+
+ phy_port1: port@9b2a000 {
+ reg = <0x9b2a000 0xff>,
+ <0x9b19000 0xff>,
+ <0x9b14000 0xff>,
+ <0x118 0x4>,
+ <0x81c 0x4>,
+ <0xe4 0x4>,
+ <0xf0 0x4>;
+ reg-names = "sata-up",
+ "pcie-up",
+ "pipew",
+ "miphy-ctrl-glue",
+ "miphy-status-glue",
+ "pcie-glue",
+ "sata-glue";
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+ };
+
+ phy_port2: port@8f95000 {
+ reg = <0x8f95000 0xff>,
+ <0x8f90000 0xff>,
+ <0x11c 0x4>,
+ <0x820 0x4>;
+ reg-names = "pipew",
+ "usb3-up",
+ "miphy-ctrl-glue",
+ "miphy-status-glue";
+ #phy-cells = <1>;
+
+ reset-names = "miphy-sw-rst";
+ resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+ };
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 5/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
` (3 preceding siblings ...)
2014-09-03 15:37 ` [PATCH v2 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 6/8] phy: miphy28lp: Add SSC support for SATA Gabriel FERNANDEZ
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel, Gabriel Fernandez
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fb95fb..641e367 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -386,6 +386,7 @@ CONFIG_PWM_TEGRA=y
CONFIG_PWM_VT8500=y
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
+CONFIG_PHY_MIPHY28LP=y
CONFIG_PHY_MIPHY365X=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_EXT4_FS=y
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 6/8] phy: miphy28lp: Add SSC support for SATA
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
` (4 preceding siblings ...)
2014-09-03 15:37 ` [PATCH v2 5/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 8/8] phy: miphy28lp: Tune tx impedance across Soc cuts Gabriel FERNANDEZ
7 siblings, 0 replies; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, Giuseppe Condorelli
This patch to tune on/off the ssc on miphy sata setup.
User can now enable ssc via dt blob, it is useful to reduce
effects of EMI.
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 1 +
drivers/phy/phy-miphy28lp.c | 35 ++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
index 5e307af..49bb7bb 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -39,6 +39,7 @@ Optional properties (port (child) node):
register.
- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
line).
+- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
example:
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index aa36cea..b36e737 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -140,6 +140,7 @@ struct miphy28lp_phy {
bool osc_force_ext;
bool osc_rdy;
bool px_rx_pol_inv;
+ bool ssc;
struct reset_control *miphy_rst;
@@ -604,6 +605,36 @@ static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
return miphy_osc_is_ready(miphy_phy);
}
+static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
+{
+ u8 val;
+
+ /* Compensate Tx impedance to avoid out of range values */
+ if (miphy_phy->ssc) {
+ /*
+ * Enable the SSC on PLL for all banks
+ * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
+ */
+
+ val = readb_relaxed(miphy_phy->base + 0x0c);
+ val |= 0x04;
+ writeb_relaxed(val, miphy_phy->base + 0x0c);
+ val = readb_relaxed(miphy_phy->base + 0x0a);
+ val |= 0x10;
+ writeb_relaxed(val, miphy_phy->base + 0x0a);
+
+ for (val = 0; val < 3; val++) {
+ writeb_relaxed(val, miphy_phy->base + 0x0f);
+ writeb_relaxed(0x3c, miphy_phy->base + 0xe4);
+ writeb_relaxed(0x6c, miphy_phy->base + 0xe5);
+ writeb_relaxed(0x81, miphy_phy->base + 0xe6);
+ writeb_relaxed(0x00, miphy_phy->base + 0xe3);
+ writeb_relaxed(0x02, miphy_phy->base + 0xe3);
+ writeb_relaxed(0x00, miphy_phy->base + 0xe3);
+ }
+ }
+}
+
static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
{
struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
@@ -643,6 +674,8 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
}
+ miphy_sata_tune_ssc(miphy_phy);
+
return miphy_is_ready(miphy_phy);
}
@@ -872,6 +905,8 @@ static int miphy28lp_of_probe(struct device_node *np,
miphy_phy->px_rx_pol_inv =
of_property_read_bool(np, "st,px_rx_pol_inv");
+ miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
+
of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
if (!miphy_phy->sata_gen)
miphy_phy->sata_gen = SATA_GEN1;
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
` (5 preceding siblings ...)
2014-09-03 15:37 ` [PATCH v2 6/8] phy: miphy28lp: Add SSC support for SATA Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
2014-09-08 15:15 ` Kishon Vijay Abraham I
2014-09-03 15:37 ` [PATCH v2 8/8] phy: miphy28lp: Tune tx impedance across Soc cuts Gabriel FERNANDEZ
7 siblings, 1 reply; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, Harsh Gupta, Gabriel Fernandez
SSC is the technique of modulating the operating frequency of a signal
slightly to spread its radiated emissions over a range of frequencies.
This reduction in the maximum emission for a given frequency helps meet
radiated emission requirements.
These settings are applicable for PCIE with Internal clock.
Signed-off-by: Harsh Gupta <harsh.gupta@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.orgm>
---
drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index b36e737..976fdda 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -679,6 +679,36 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
return miphy_is_ready(miphy_phy);
}
+static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
+{
+ u8 val;
+
+ /* Compensate Tx impedance to avoid out of range values */
+ if (miphy_phy->ssc) {
+ /*
+ * Enable the SSC on PLL for all banks
+ * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
+ */
+ val = readb_relaxed(miphy_phy->base + 0x0c);
+ val |= 0x04;
+ writeb_relaxed(val, miphy_phy->base + 0x0c);
+ val = readb_relaxed(miphy_phy->base + 0x0a);
+ val |= 0x10;
+ writeb_relaxed(val, miphy_phy->base + 0x0a);
+
+ for (val = 0; val < 2; val++) {
+ writeb_relaxed(val, miphy_phy->base + 0x0f);
+ writeb_relaxed(0x69, miphy_phy->base + 0xe5);
+ writeb_relaxed(0x21, miphy_phy->base + 0xe6);
+ writeb_relaxed(0x3c, miphy_phy->base + 0xe4);
+ writeb_relaxed(0x21, miphy_phy->base + 0xe6);
+ writeb_relaxed(0x00, miphy_phy->base + 0xe3);
+ writeb_relaxed(0x02, miphy_phy->base + 0xe3);
+ writeb_relaxed(0x00, miphy_phy->base + 0xe3);
+ }
+ }
+}
+
static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
{
struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
@@ -710,6 +740,8 @@ static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
/* initialize miphy */
miphy28lp_configure_pcie(miphy_phy);
+ miphy_pcie_tune_ssc(miphy_phy);
+
/* Waiting for Compensation to complete */
do {
val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 8/8] phy: miphy28lp: Tune tx impedance across Soc cuts
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
` (6 preceding siblings ...)
2014-09-03 15:37 ` [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE Gabriel FERNANDEZ
@ 2014-09-03 15:37 ` Gabriel FERNANDEZ
7 siblings, 0 replies; 15+ messages in thread
From: Gabriel FERNANDEZ @ 2014-09-03 15:37 UTC (permalink / raw)
To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Srinivas Kandagatla, Maxime Coquelin, Patrice Chotard,
Russell King, Kishon Vijay Abraham I, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, Giuseppe Condorelli
This patch to compensate tx impedance (Sata, PCIe)
depending on Soc cuts the kernel is built for.
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 1 +
drivers/phy/phy-miphy28lp.c | 24 ++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
index 49bb7bb..de25e8f 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -40,6 +40,7 @@ Optional properties (port (child) node):
- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
line).
- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
+- st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
example:
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
index 976fdda..148dd9c 100644
--- a/drivers/phy/phy-miphy28lp.c
+++ b/drivers/phy/phy-miphy28lp.c
@@ -141,6 +141,7 @@ struct miphy28lp_phy {
bool osc_rdy;
bool px_rx_pol_inv;
bool ssc;
+ bool tx_impedance;
struct reset_control *miphy_rst;
@@ -296,6 +297,10 @@ static inline void miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
writeb_relaxed(0x00, base + MIPHY_RESET);
writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
+
+ /* TX compensation offset to re-center TX impedance */
+ writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
+
}
static inline void miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
@@ -385,6 +390,10 @@ static inline void miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
writeb_relaxed(0x00, base + MIPHY_RESET);
writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
+
+ /* TX compensation offset to re-center TX impedance */
+ writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
+
}
static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
@@ -605,6 +614,14 @@ static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
return miphy_osc_is_ready(miphy_phy);
}
+static void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
+{
+ /* Compensate Tx impedance to avoid out of range values */
+ if (miphy_phy->tx_impedance)
+ writeb_relaxed(0x02, miphy_phy->base + 0x42);
+
+}
+
static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
{
u8 val;
@@ -676,6 +693,8 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
miphy_sata_tune_ssc(miphy_phy);
+ miphy_tune_tx_impedance(miphy_phy);
+
return miphy_is_ready(miphy_phy);
}
@@ -750,6 +769,8 @@ static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
cpu_relax();
} while (!(val & MIPHY_COMP_DONE));
+ miphy_tune_tx_impedance(miphy_phy);
+
/* PIPE Wrapper Configuration */
writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
@@ -939,6 +960,9 @@ static int miphy28lp_of_probe(struct device_node *np,
miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
+ miphy_phy->tx_impedance =
+ of_property_read_bool(np, "st,tx-impedance-comp");
+
of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
if (!miphy_phy->sata_gen)
miphy_phy->sata_gen = SATA_GEN1;
--
1.9.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
2014-09-03 15:37 ` [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Gabriel FERNANDEZ
@ 2014-09-08 14:33 ` Kishon Vijay Abraham I
2014-09-09 9:24 ` Gabriel Fernandez
0 siblings, 1 reply; 15+ messages in thread
From: Kishon Vijay Abraham I @ 2014-09-08 14:33 UTC (permalink / raw)
To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin,
Patrice Chotard, Russell King, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro
Hi,
On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
> or USB3 devices.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
> .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++
> 1 file changed, 126 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
> new file mode 100644
> index 0000000..5e307af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
> @@ -0,0 +1,126 @@
> +STMicroelectronics STi MIPHY28LP PHY binding
> +============================================
> +
> +This binding describes a miphy device that is used to control PHY hardware
> +for SATA, PCIe or USB3.
> +
> +Required properties (controller (parent) node):
> +- compatible : Should be "st,miphy28lp-phy"
> +- st,syscfg : Should be a phandle of the system configuration register group
> + which contain the SATA, PCIe or USB3 mode setting bits
> +
> +Required nodes : A sub-node is required for each channel the controller
> + provides. Address range information including the usual
> + 'reg' and 'reg-names' properties are used inside these
> + nodes to describe the controller's topology. These nodes
> + are translated by the driver's .xlate() function.
> +
> +Required properties (port (child) node):
> +- #phy-cells : Should be 1 (See second example)
> + Cell after port phandle is device type from:
> + - MIPHY_TYPE_SATA
> + - MIPHY_TYPE_PCI
> + - MIPHY_TYPE_USB3
> +- reg : Address and length of the register set for the device
> +- reg-names : The names of the register addresses corresponding to the registers
> + filled in "reg". Is can also contain the offset of the system configuration
%s/Is/It
Thanks
Kishon
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
2014-09-03 15:37 ` [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY Gabriel FERNANDEZ
@ 2014-09-08 15:12 ` Kishon Vijay Abraham I
2014-09-09 9:15 ` Gabriel Fernandez
0 siblings, 1 reply; 15+ messages in thread
From: Kishon Vijay Abraham I @ 2014-09-08 15:12 UTC (permalink / raw)
To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin,
Patrice Chotard, Russell King, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, alexandre torgue, Giuseppe Cavallaro
Hi,
On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
> or USB3 devices.
>
> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-miphy28lp.c | 985 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 994 insertions(+)
> create mode 100644 drivers/phy/phy-miphy28lp.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 0dd7427..2053f72 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -230,4 +230,12 @@ config PHY_XGENE
> help
> This option enables support for APM X-Gene SoC multi-purpose PHY.
>
> +config PHY_MIPHY28LP
> + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
> + depends on ARCH_STI
> + depends on GENERIC_PHY
Select GENERIC_PHY so that it's same as other PHY drivers.
> + help
> + Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
> + that is part of STMicroelectronics STiH407 SoC.
> +
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 95c69ed..f7e7c59 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
> obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o
> obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
> new file mode 100644
> index 0000000..aa36cea
> --- /dev/null
> +++ b/drivers/phy/phy-miphy28lp.c
> @@ -0,0 +1,985 @@
> +/*
> + * Copyright (C) 2014 STMicroelectronics
> + *
> + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
> + *
> + * Author: Alexandre Torgue <alexandre.torgue@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2, as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#include <dt-bindings/phy/phy-miphy.h>
> +
> +/* MiPHY mask registers */
> +#define MIPHY_PHY_RDY 0x01
> +#define MIPHY_PLL_HFC_RDY 0x06
> +#define MIPHY_COMP_DONE 0x80
> +
> +#define MIPHY_PX_RX_POL BIT(5)
> +
> +/* MiPHY registers */
> +#define MIPHY_CONF_RESET 0x00
> +#define MIPHY_RESET 0x01
> +#define MIPHY_STATUS_1 0x02
> +#define MIPHY_CONTROL 0x04
> +#define MIPHY_BOUNDARY_SEL 0x0a
> +#define MIPHY_BOUNDARY_1 0x0b
> +#define MIPHY_BOUNDARY_2 0x0c
> +#define MIPHY_PLL_CLKREF_FREQ 0x0d
> +#define MIPHY_SPEED 0x0e
> +#define MIPHY_CONF 0x0f
> +#define MIPHY_CTRL_TEST_SEL 0x20
> +#define MIPHY_CTRL_TEST_1 0x21
> +#define MIPHY_CTRL_TEST_2 0x22
> +#define MIPHY_CTRL_TEST_3 0x23
> +#define MIPHY_CTRL_TEST_4 0x24
> +#define MIPHY_FEEDBACK_TEST 0x25
> +#define MIPHY_DEBUG_BUS 0x26
> +#define MIPHY_DEBUG_STATUS_MSB 0x27
> +#define MIPHY_DEBUG_STATUS_LSB 0x28
> +#define MIPHY_PWR_RAIL_1 0x29
> +#define MIPHY_PWR_RAIL_2 0x2a
> +#define MIPHY_SYNCHAR_CONTROL 0x30
> +#define MIPHY_COMP_FSM_1 0x3a
> +#define MIPHY_COMP_FSM_6 0x3f
> +#define MIPHY_COMP_POSTP 0x42
> +#define MIPHY_TX_CTRL_1 0x49
> +#define MIPHY_TX_CTRL_2 0x4a
> +#define MIPHY_TX_CTRL_3 0x4b
> +#define MIPHY_TX_CAL_MAN 0x4e
> +#define MIPHY_TST_BIAS_BOOST_2 0x62
> +#define MIPHY_BIAS_BOOST_1 0x63
> +#define MIPHY_BIAS_BOOST_2 0x64
> +#define MIPHY_RX_DESBUFF_FDB_2 0x67
> +#define MIPHY_RX_DESBUFF_FDB_3 0x68
> +#define MIPHY_SIGDET_COMPENS1 0x69
> +#define MIPHY_SIGDET_COMPENS2 0x6a
> +#define MIPHY_JITTER_PERIOD 0x6b
> +#define MIPHY_JITTER_AMPLITUDE_1 0x6c
> +#define MIPHY_JITTER_AMPLITUDE_2 0x6d
> +#define MIPHY_JITTER_AMPLITUDE_3 0x6e
> +#define MIPHY_RX_K_GAIN 0x78
> +#define MIPHY_RX_BUFFER_CTRL 0x7a
> +#define MIPHY_RX_VGA_GAIN 0x7b
> +#define MIPHY_RX_EQU_GAIN_1 0x7f
> +#define MIPHY_RX_EQU_GAIN_2 0x80
> +#define MIPHY_RX_EQU_GAIN_3 0x81
> +#define MIPHY_RX_CAL_CTRL_1 0x97
> +#define MIPHY_RX_CAL_CTRL_2 0x98
> +#define MIPHY_RX_CAL_OFFSET_CTRL 0x99
> +#define MIPHY_RX_CAL_VGA_STEP 0x9a
> +#define MIPHY_RX_CAL_EYE_MIN 0x9d
> +#define MIPHY_RX_CAL_OPT_LENGTH 0x9f
> +#define MIPHY_RX_LOCK_CTRL_1 0xc1
> +#define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
> +#define MIPHY_RX_LOCK_STEP 0xc4
> +#define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
> +#define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
> +#define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
> +#define MIPHY_RX_SIGDET_DATA_SEL 0xcc
> +#define MIPHY_RX_POWER_CTRL_1 0xcd
> +#define MIPHY_RX_POWER_CTRL_2 0xce
> +#define MIPHY_PLL_CALSET_CTRL 0xd3
> +#define MIPHY_PLL_CALSET_1 0xd4
> +#define MIPHY_PLL_CALSET_2 0xd5
> +#define MIPHY_PLL_CALSET_3 0xd6
> +#define MIPHY_PLL_CALSET_4 0xd7
> +#define MIPHY_PLL_SBR_1 0xe3
> +#define MIPHY_PLL_SBR_2 0xe4
> +#define MIPHY_PLL_SBR_3 0xe5
> +#define MIPHY_PLL_SBR_4 0xe6
> +#define MIPHY_PLL_COMMON_MISC_2 0xe9
> +#define MIPHY_PLL_SPAREIN 0xeb
> +
> +/*
> + * On STiH407 the glue logic can be different among MiPHY devices; for example:
> + * MiPHY0: OSC_FORCE_EXT means:
> + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
> + * MiPHY1: OSC_FORCE_EXT means:
> + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
> + * Some devices have not the possibility to check if the osc is ready.
> + */
> +#define MIPHY_OSC_FORCE_EXT BIT(3)
> +#define MIPHY_OSC_RDY BIT(5)
> +
> +#define MIPHY_CTRL_MASK 0x0f
> +#define MIPHY_CTRL_DEFAULT 0
> +#define MIPHY_CTRL_SYNC_D_EN BIT(2)
> +
> +/* SATA / PCIe defines */
> +#define SATA_CTRL_MASK 0x07
> +#define PCIE_CTRL_MASK 0xff
> +#define SATA_CTRL_SELECT_SATA 1
> +#define SATA_CTRL_SELECT_PCIE 0
> +#define SYSCFG_PCIE_PCIE_VAL 0x80
> +#define SATA_SPDMODE 1
> +
> +struct miphy28lp_phy {
> + struct phy *phy;
> + struct miphy28lp_dev *phydev;
> + void __iomem *base;
> + void __iomem *pipebase;
> +
> + bool osc_force_ext;
> + bool osc_rdy;
> + bool px_rx_pol_inv;
> +
> + struct reset_control *miphy_rst;
> +
> + u32 sata_gen;
> +
> + /* Sysconfig registers offsets needed to configure the device */
> + u32 syscfg_miphy_ctrl;
> + u32 syscfg_miphy_status;
> + u32 syscfg_pci;
> + u32 syscfg_sata;
> + u8 type;
> +};
> +
> +struct miphy28lp_dev {
> + struct device *dev;
> + struct regmap *regmap;
> + struct mutex miphy_mutex;
> + struct miphy28lp_phy **phys;
> +};
> +
> +struct miphy_initval {
> + u16 reg;
> + u16 val;
> +};
> +
> +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
> +
> +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" };
> +
> +static inline void miphy28lp_cfg_out_of_reset(struct miphy28lp_phy *miphy_phy)
> +{
> + unsigned long finish = jiffies + 5 * HZ;
> + u8 mask = MIPHY_PLL_HFC_RDY;
> + u8 val;
> +
> + do {
> + val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
> + if ((val & mask) != mask)
> + cpu_relax();
> + else
> + break;
> + } while (!time_after_eq(jiffies, finish));
> +}
> +
> +static inline void miphy28lp_configure_reset(struct miphy28lp_phy *miphy_phy)
> +{
> + void *base = miphy_phy->base;
> +
> + /* Putting Macro in reset */
> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
> + writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
> +
> + /* Wait for a while */
> + usleep_range(10, 20); /* extra delay after resetting */
How was this delay value derived? If the HW spec says so, it would be better to
document it here. Applicable for all the delays added in this patch.
> +}
> +
> +
> +
> +static inline void miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
> +{
> + void __iomem *base = miphy_phy->base;
> +
> + /* Putting Macro in reset */
> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
> + writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
> +
> + /* Wait for a while */
> + usleep_range(10, 20); /* extra delay after resetting */
You already have a function miphy28lp_configure_reset doing the same no?
> +
> + /* Bringing the MIPHY-CPU registers out of reset */
> + writeb_relaxed(0x1c, base + MIPHY_CONTROL);
> +
> + /* Applying PLL Settings */
> + writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
> + writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
> +
> + /* PLL Ratio */
> + writeb_relaxed(0xc8, base + MIPHY_PLL_CALSET_1);
> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_2);
> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_3);
> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_4);
> +
> + /* Number of PLL Calibrations */
> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
> +
> + /* Unbanked Settings */
> + writeb_relaxed(0xd1, base + MIPHY_TX_CAL_MAN);
> + writeb_relaxed(0x1f, base + MIPHY_RX_CAL_OFFSET_CTRL);
> + writeb_relaxed(0x40, base + MIPHY_BOUNDARY_SEL);
> +
> + /* Banked settings */
> + /* Gen 1 */
> + writeb_relaxed(0x00, base + MIPHY_CONF);
> + writeb_relaxed(0x00, base + MIPHY_SPEED);
> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
Aren't the 0's default reset values? Can we do only the bare minimal settings
required to get this PHY functions.
> + writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
> +
> + /* TX buffer Settings */
> + writeb_relaxed(0x53, base + MIPHY_TX_CTRL_2);
> + writeb_relaxed(0x00, base + MIPHY_TX_CTRL_3);
> +
> + /* RX Buffer Settings */
> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
> + writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
> + writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
> +
> + /* Gen 2 */
> + writeb_relaxed(0x01, base + MIPHY_CONF);
> + writeb_relaxed(0x05, base + MIPHY_SPEED);
> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
> + writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
> +
> + /* TX buffer Settings */
> + writeb_relaxed(0x72, base + MIPHY_TX_CTRL_2);
> + writeb_relaxed(0x20, base + MIPHY_TX_CTRL_3);
> +
> + /* RX Buffer Settings */
> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
> + writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
> + writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
> +
> + /* Gen 3 */
> + writeb_relaxed(0x02, base + MIPHY_CONF);
> + writeb_relaxed(0x0a, base + MIPHY_SPEED);
> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
> + writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
> +
> + /* TX buffer Settings */
> + writeb_relaxed(0xc0, base + MIPHY_TX_CTRL_2);
> + writeb_relaxed(0x20, base + MIPHY_TX_CTRL_3);
> +
> + /* RX Buffer Settings */
> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
> + writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
> + writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
> +
> + /* Power control */
> + writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
> +
> + /* Macro out of reset */
> + writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
> +
> + /* Poll for HFC ready after reset release */
> + /* Compensation measurement */
> + writeb_relaxed(0x05, base + MIPHY_RESET);
> + writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
> + writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
> + writeb_relaxed(0x00, base + MIPHY_RESET);
> + writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
This function can be split into separate smaller functions and can be resued
for pcie and usb3.
> +}
> +
> +static inline void miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
> +{
> + void __iomem *base = miphy_phy->base;
> +
> + /* Putting Macro in reset */
> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
> + writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
> +
> + /* Wait for a while */
> + usleep_range(10, 20); /* extra delay after resetting */
> +
> + /* Bringing the MIPHY-CPU registers out of reset */
> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
> + writeb_relaxed(0x14, base + MIPHY_CONTROL);
> + writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
> +
> + /* Applying PLL Settings */
> + writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
> +
> + /* PLL Ratio */
> + writeb_relaxed(0xa6, base + MIPHY_PLL_CALSET_1);
> + writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_2);
> + writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_3);
> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_4);
> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
> +
> + writeb_relaxed(0xd1, base + MIPHY_TX_CAL_MAN);
> + writeb_relaxed(0x5f, base + MIPHY_RX_CAL_OFFSET_CTRL);
> + writeb_relaxed(0x40, base + MIPHY_BOUNDARY_SEL);
> +
> + /* Banked settings */
> + /* Gen 1 */
> + writeb_relaxed(0x00, base + MIPHY_CONF);
> +
> + writeb_relaxed(0x05, base + MIPHY_SPEED);
> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
> + writeb_relaxed(0xa5, base + MIPHY_BIAS_BOOST_2);
> +
> + /* TX buffer Settings */
> + writeb_relaxed(0x07, base + MIPHY_TX_CTRL_1);
> + writeb_relaxed(0x71, base + MIPHY_TX_CTRL_2);
> + writeb_relaxed(0x60, base + MIPHY_TX_CTRL_3);
> + writeb_relaxed(0x98, base + MIPHY_RX_K_GAIN);
> +
> + /* RX Buffer Settings */
> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
> + writeb_relaxed(0x79, base + MIPHY_RX_EQU_GAIN_1);
> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
> +
> + /* Gen 2 */
> + writeb_relaxed(0x01, base + MIPHY_CONF);
> + writeb_relaxed(0x0a, base + MIPHY_SPEED);
> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
> + writeb_relaxed(0xa5, base + MIPHY_BIAS_BOOST_2);
> +
> + /* TX buffer Settings */
> + writeb_relaxed(0x07, base + MIPHY_TX_CTRL_1);
> + writeb_relaxed(0x70, base + MIPHY_TX_CTRL_2);
> + writeb_relaxed(0x60, base + MIPHY_TX_CTRL_3);
> + writeb_relaxed(0xcc, base + MIPHY_RX_K_GAIN);
> +
> + /* RX Buffer Settings */
> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
> + writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
> + writeb_relaxed(0x07, base + MIPHY_RX_EQU_GAIN_2);
> +
> + writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
> +
> + /* Macro out of reset */
> + writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
> +
> + /* Poll for HFC ready after reset release */
> + /* Compensation measurement */
> + writeb_relaxed(0x05, base + MIPHY_RESET);
> + writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
> + writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
> + writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
> +
> + /* extra delay to wait pll lock */
> + usleep_range(100, 120);
> +
> + writeb_relaxed(0x01, base + MIPHY_RESET);
> + writeb_relaxed(0x00, base + MIPHY_RESET);
> + writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
> + writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
Are all these settings necessary? Can't we have a bare minimal settings needed
to get the PHY functional.
Thanks
Kishon
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE
2014-09-03 15:37 ` [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE Gabriel FERNANDEZ
@ 2014-09-08 15:15 ` Kishon Vijay Abraham I
2014-09-09 9:23 ` Gabriel Fernandez
0 siblings, 1 reply; 15+ messages in thread
From: Kishon Vijay Abraham I @ 2014-09-08 15:15 UTC (permalink / raw)
To: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin,
Patrice Chotard, Russell King, Grant Likely
Cc: devicetree, linux-kernel, linux-arm-kernel, kernel,
Gabriel Fernandez, Harsh Gupta, Gabriel Fernandez
On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
> SSC is the technique of modulating the operating frequency of a signal
> slightly to spread its radiated emissions over a range of frequencies.
> This reduction in the maximum emission for a given frequency helps meet
> radiated emission requirements.
> These settings are applicable for PCIE with Internal clock.
>
> Signed-off-by: Harsh Gupta <harsh.gupta@st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.orgm>
> ---
> drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
> index b36e737..976fdda 100644
> --- a/drivers/phy/phy-miphy28lp.c
> +++ b/drivers/phy/phy-miphy28lp.c
> @@ -679,6 +679,36 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
> return miphy_is_ready(miphy_phy);
> }
>
> +static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
> +{
> + u8 val;
> +
> + /* Compensate Tx impedance to avoid out of range values */
> + if (miphy_phy->ssc) {
> + /*
> + * Enable the SSC on PLL for all banks
> + * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
> + */
> + val = readb_relaxed(miphy_phy->base + 0x0c);
> + val |= 0x04;
> + writeb_relaxed(val, miphy_phy->base + 0x0c);
> + val = readb_relaxed(miphy_phy->base + 0x0a);
> + val |= 0x10;
> + writeb_relaxed(val, miphy_phy->base + 0x0a);
macros for these registers and values is needed. Or else it's difficult to review.
> +
> + for (val = 0; val < 2; val++) {
> + writeb_relaxed(val, miphy_phy->base + 0x0f);
> + writeb_relaxed(0x69, miphy_phy->base + 0xe5);
Do these registers have to be written for every iteration?
Thanks
Kishon
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
2014-09-08 15:12 ` Kishon Vijay Abraham I
@ 2014-09-09 9:15 ` Gabriel Fernandez
0 siblings, 0 replies; 15+ messages in thread
From: Gabriel Fernandez @ 2014-09-09 9:15 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin,
Patrice Chotard, Russell King, Grant Likely, devicetree,
linux-kernel, linux-arm-kernel, kernel, alexandre torgue,
Giuseppe Cavallaro
Hi Kishon,
Thanks for reviewing.
BR
Gabriel
On 8 September 2014 17:12, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Hi,
>
> On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
>> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
>> or USB3 devices.
>>
>> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
>> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> ---
>> drivers/phy/Kconfig | 8 +
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-miphy28lp.c | 985 ++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 994 insertions(+)
>> create mode 100644 drivers/phy/phy-miphy28lp.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 0dd7427..2053f72 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -230,4 +230,12 @@ config PHY_XGENE
>> help
>> This option enables support for APM X-Gene SoC multi-purpose PHY.
>>
>> +config PHY_MIPHY28LP
>> + tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
>> + depends on ARCH_STI
>> + depends on GENERIC_PHY
>
> Select GENERIC_PHY so that it's same as other PHY drivers.
Ok
>> + help
>> + Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
>> + that is part of STMicroelectronics STiH407 SoC.
>> +
>> endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 95c69ed..f7e7c59 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
>> obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
>> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
>> +obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
>> obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o
>> obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
>> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
>> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
>> new file mode 100644
>> index 0000000..aa36cea
>> --- /dev/null
>> +++ b/drivers/phy/phy-miphy28lp.c
>> @@ -0,0 +1,985 @@
>> +/*
>> + * Copyright (C) 2014 STMicroelectronics
>> + *
>> + * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
>> + *
>> + * Author: Alexandre Torgue <alexandre.torgue@st.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2, as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/delay.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +
>> +#include <dt-bindings/phy/phy-miphy.h>
>> +
>> +/* MiPHY mask registers */
>> +#define MIPHY_PHY_RDY 0x01
>> +#define MIPHY_PLL_HFC_RDY 0x06
>> +#define MIPHY_COMP_DONE 0x80
>> +
>> +#define MIPHY_PX_RX_POL BIT(5)
>> +
>> +/* MiPHY registers */
>> +#define MIPHY_CONF_RESET 0x00
>> +#define MIPHY_RESET 0x01
>> +#define MIPHY_STATUS_1 0x02
>> +#define MIPHY_CONTROL 0x04
>> +#define MIPHY_BOUNDARY_SEL 0x0a
>> +#define MIPHY_BOUNDARY_1 0x0b
>> +#define MIPHY_BOUNDARY_2 0x0c
>> +#define MIPHY_PLL_CLKREF_FREQ 0x0d
>> +#define MIPHY_SPEED 0x0e
>> +#define MIPHY_CONF 0x0f
>> +#define MIPHY_CTRL_TEST_SEL 0x20
>> +#define MIPHY_CTRL_TEST_1 0x21
>> +#define MIPHY_CTRL_TEST_2 0x22
>> +#define MIPHY_CTRL_TEST_3 0x23
>> +#define MIPHY_CTRL_TEST_4 0x24
>> +#define MIPHY_FEEDBACK_TEST 0x25
>> +#define MIPHY_DEBUG_BUS 0x26
>> +#define MIPHY_DEBUG_STATUS_MSB 0x27
>> +#define MIPHY_DEBUG_STATUS_LSB 0x28
>> +#define MIPHY_PWR_RAIL_1 0x29
>> +#define MIPHY_PWR_RAIL_2 0x2a
>> +#define MIPHY_SYNCHAR_CONTROL 0x30
>> +#define MIPHY_COMP_FSM_1 0x3a
>> +#define MIPHY_COMP_FSM_6 0x3f
>> +#define MIPHY_COMP_POSTP 0x42
>> +#define MIPHY_TX_CTRL_1 0x49
>> +#define MIPHY_TX_CTRL_2 0x4a
>> +#define MIPHY_TX_CTRL_3 0x4b
>> +#define MIPHY_TX_CAL_MAN 0x4e
>> +#define MIPHY_TST_BIAS_BOOST_2 0x62
>> +#define MIPHY_BIAS_BOOST_1 0x63
>> +#define MIPHY_BIAS_BOOST_2 0x64
>> +#define MIPHY_RX_DESBUFF_FDB_2 0x67
>> +#define MIPHY_RX_DESBUFF_FDB_3 0x68
>> +#define MIPHY_SIGDET_COMPENS1 0x69
>> +#define MIPHY_SIGDET_COMPENS2 0x6a
>> +#define MIPHY_JITTER_PERIOD 0x6b
>> +#define MIPHY_JITTER_AMPLITUDE_1 0x6c
>> +#define MIPHY_JITTER_AMPLITUDE_2 0x6d
>> +#define MIPHY_JITTER_AMPLITUDE_3 0x6e
>> +#define MIPHY_RX_K_GAIN 0x78
>> +#define MIPHY_RX_BUFFER_CTRL 0x7a
>> +#define MIPHY_RX_VGA_GAIN 0x7b
>> +#define MIPHY_RX_EQU_GAIN_1 0x7f
>> +#define MIPHY_RX_EQU_GAIN_2 0x80
>> +#define MIPHY_RX_EQU_GAIN_3 0x81
>> +#define MIPHY_RX_CAL_CTRL_1 0x97
>> +#define MIPHY_RX_CAL_CTRL_2 0x98
>> +#define MIPHY_RX_CAL_OFFSET_CTRL 0x99
>> +#define MIPHY_RX_CAL_VGA_STEP 0x9a
>> +#define MIPHY_RX_CAL_EYE_MIN 0x9d
>> +#define MIPHY_RX_CAL_OPT_LENGTH 0x9f
>> +#define MIPHY_RX_LOCK_CTRL_1 0xc1
>> +#define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
>> +#define MIPHY_RX_LOCK_STEP 0xc4
>> +#define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
>> +#define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
>> +#define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
>> +#define MIPHY_RX_SIGDET_DATA_SEL 0xcc
>> +#define MIPHY_RX_POWER_CTRL_1 0xcd
>> +#define MIPHY_RX_POWER_CTRL_2 0xce
>> +#define MIPHY_PLL_CALSET_CTRL 0xd3
>> +#define MIPHY_PLL_CALSET_1 0xd4
>> +#define MIPHY_PLL_CALSET_2 0xd5
>> +#define MIPHY_PLL_CALSET_3 0xd6
>> +#define MIPHY_PLL_CALSET_4 0xd7
>> +#define MIPHY_PLL_SBR_1 0xe3
>> +#define MIPHY_PLL_SBR_2 0xe4
>> +#define MIPHY_PLL_SBR_3 0xe5
>> +#define MIPHY_PLL_SBR_4 0xe6
>> +#define MIPHY_PLL_COMMON_MISC_2 0xe9
>> +#define MIPHY_PLL_SPAREIN 0xeb
>> +
>> +/*
>> + * On STiH407 the glue logic can be different among MiPHY devices; for example:
>> + * MiPHY0: OSC_FORCE_EXT means:
>> + * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
>> + * MiPHY1: OSC_FORCE_EXT means:
>> + * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
>> + * Some devices have not the possibility to check if the osc is ready.
>> + */
>> +#define MIPHY_OSC_FORCE_EXT BIT(3)
>> +#define MIPHY_OSC_RDY BIT(5)
>> +
>> +#define MIPHY_CTRL_MASK 0x0f
>> +#define MIPHY_CTRL_DEFAULT 0
>> +#define MIPHY_CTRL_SYNC_D_EN BIT(2)
>> +
>> +/* SATA / PCIe defines */
>> +#define SATA_CTRL_MASK 0x07
>> +#define PCIE_CTRL_MASK 0xff
>> +#define SATA_CTRL_SELECT_SATA 1
>> +#define SATA_CTRL_SELECT_PCIE 0
>> +#define SYSCFG_PCIE_PCIE_VAL 0x80
>> +#define SATA_SPDMODE 1
>> +
>> +struct miphy28lp_phy {
>> + struct phy *phy;
>> + struct miphy28lp_dev *phydev;
>> + void __iomem *base;
>> + void __iomem *pipebase;
>> +
>> + bool osc_force_ext;
>> + bool osc_rdy;
>> + bool px_rx_pol_inv;
>> +
>> + struct reset_control *miphy_rst;
>> +
>> + u32 sata_gen;
>> +
>> + /* Sysconfig registers offsets needed to configure the device */
>> + u32 syscfg_miphy_ctrl;
>> + u32 syscfg_miphy_status;
>> + u32 syscfg_pci;
>> + u32 syscfg_sata;
>> + u8 type;
>> +};
>> +
>> +struct miphy28lp_dev {
>> + struct device *dev;
>> + struct regmap *regmap;
>> + struct mutex miphy_mutex;
>> + struct miphy28lp_phy **phys;
>> +};
>> +
>> +struct miphy_initval {
>> + u16 reg;
>> + u16 val;
>> +};
>> +
>> +enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
>> +
>> +static char *miphy_type_name[] = { "sata-up", "pcie-up", "usb3-up" };
>> +
>> +static inline void miphy28lp_cfg_out_of_reset(struct miphy28lp_phy *miphy_phy)
>> +{
>> + unsigned long finish = jiffies + 5 * HZ;
>> + u8 mask = MIPHY_PLL_HFC_RDY;
>> + u8 val;
>> +
>> + do {
>> + val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
>> + if ((val & mask) != mask)
>> + cpu_relax();
>> + else
>> + break;
>> + } while (!time_after_eq(jiffies, finish));
>> +}
>> +
>> +static inline void miphy28lp_configure_reset(struct miphy28lp_phy *miphy_phy)
>> +{
>> + void *base = miphy_phy->base;
>> +
>> + /* Putting Macro in reset */
>> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
>> + writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
>> +
>> + /* Wait for a while */
>> + usleep_range(10, 20); /* extra delay after resetting */
>
> How was this delay value derived? If the HW spec says so, it would be better to
> document it here. Applicable for all the delays added in this patch.
After check with team validation, we remove this delay because it's
only for debug.
>> +}
>> +
>> +
>> +
>> +static inline void miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
>> +{
>> + void __iomem *base = miphy_phy->base;
>> +
>> + /* Putting Macro in reset */
>> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
>> + writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
>> +
>> + /* Wait for a while */
>> + usleep_range(10, 20); /* extra delay after resetting */
>
> You already have a function miphy28lp_configure_reset doing the same no?
yes, will be fix on v3
>> +
>> + /* Bringing the MIPHY-CPU registers out of reset */
>> + writeb_relaxed(0x1c, base + MIPHY_CONTROL);
>> +
>> + /* Applying PLL Settings */
>> + writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
>> + writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
>> +
>> + /* PLL Ratio */
>> + writeb_relaxed(0xc8, base + MIPHY_PLL_CALSET_1);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_2);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_3);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_4);
>> +
>> + /* Number of PLL Calibrations */
>> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
>> +
>> + /* Unbanked Settings */
>> + writeb_relaxed(0xd1, base + MIPHY_TX_CAL_MAN);
>> + writeb_relaxed(0x1f, base + MIPHY_RX_CAL_OFFSET_CTRL);
>> + writeb_relaxed(0x40, base + MIPHY_BOUNDARY_SEL);
>> +
>> + /* Banked settings */
>> + /* Gen 1 */
>> + writeb_relaxed(0x00, base + MIPHY_CONF);
>> + writeb_relaxed(0x00, base + MIPHY_SPEED);
>> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
>
> Aren't the 0's default reset values? Can we do only the bare minimal settings
> required to get this PHY functions.
0's aren't default reset values, differ on cut version.
>
>> + writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
>> +
>> + /* TX buffer Settings */
>> + writeb_relaxed(0x53, base + MIPHY_TX_CTRL_2);
>> + writeb_relaxed(0x00, base + MIPHY_TX_CTRL_3);
>> +
>> + /* RX Buffer Settings */
>> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
>> + writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
>> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
>> + writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
>> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
>> +
>> + /* Gen 2 */
>> + writeb_relaxed(0x01, base + MIPHY_CONF);
>> + writeb_relaxed(0x05, base + MIPHY_SPEED);
>> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
>> + writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
>> +
>> + /* TX buffer Settings */
>> + writeb_relaxed(0x72, base + MIPHY_TX_CTRL_2);
>> + writeb_relaxed(0x20, base + MIPHY_TX_CTRL_3);
>> +
>> + /* RX Buffer Settings */
>> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
>> + writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
>> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
>> + writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
>> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
>> +
>> + /* Gen 3 */
>> + writeb_relaxed(0x02, base + MIPHY_CONF);
>> + writeb_relaxed(0x0a, base + MIPHY_SPEED);
>> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
>> + writeb_relaxed(0xae, base + MIPHY_BIAS_BOOST_2);
>> +
>> + /* TX buffer Settings */
>> + writeb_relaxed(0xc0, base + MIPHY_TX_CTRL_2);
>> + writeb_relaxed(0x20, base + MIPHY_TX_CTRL_3);
>> +
>> + /* RX Buffer Settings */
>> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
>> + writeb_relaxed(0x7d, base + MIPHY_RX_EQU_GAIN_1);
>> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
>> + writeb_relaxed(0x00, base + MIPHY_RX_EQU_GAIN_3);
>> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
>> +
>> + /* Power control */
>> + writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
>> +
>> + /* Macro out of reset */
>> + writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
>> +
>> + /* Poll for HFC ready after reset release */
>> + /* Compensation measurement */
>> + writeb_relaxed(0x05, base + MIPHY_RESET);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
>> + writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
>> + writeb_relaxed(0x00, base + MIPHY_RESET);
>> + writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
>
> This function can be split into separate smaller functions and can be resued
> for pcie and usb3.
ok
>> +}
>> +
>> +static inline void miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
>> +{
>> + void __iomem *base = miphy_phy->base;
>> +
>> + /* Putting Macro in reset */
>> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
>> + writeb_relaxed(0x03, base + MIPHY_CONF_RESET);
>> +
>> + /* Wait for a while */
>> + usleep_range(10, 20); /* extra delay after resetting */
>> +
>> + /* Bringing the MIPHY-CPU registers out of reset */
>> + writeb_relaxed(0x01, base + MIPHY_CONF_RESET);
>> + writeb_relaxed(0x14, base + MIPHY_CONTROL);
>> + writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
>> +
>> + /* Applying PLL Settings */
>> + writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
>> +
>> + /* PLL Ratio */
>> + writeb_relaxed(0xa6, base + MIPHY_PLL_CALSET_1);
>> + writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_2);
>> + writeb_relaxed(0xaa, base + MIPHY_PLL_CALSET_3);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_4);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_CALSET_CTRL);
>> +
>> + writeb_relaxed(0xd1, base + MIPHY_TX_CAL_MAN);
>> + writeb_relaxed(0x5f, base + MIPHY_RX_CAL_OFFSET_CTRL);
>> + writeb_relaxed(0x40, base + MIPHY_BOUNDARY_SEL);
>> +
>> + /* Banked settings */
>> + /* Gen 1 */
>> + writeb_relaxed(0x00, base + MIPHY_CONF);
>> +
>> + writeb_relaxed(0x05, base + MIPHY_SPEED);
>> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
>> + writeb_relaxed(0xa5, base + MIPHY_BIAS_BOOST_2);
>> +
>> + /* TX buffer Settings */
>> + writeb_relaxed(0x07, base + MIPHY_TX_CTRL_1);
>> + writeb_relaxed(0x71, base + MIPHY_TX_CTRL_2);
>> + writeb_relaxed(0x60, base + MIPHY_TX_CTRL_3);
>> + writeb_relaxed(0x98, base + MIPHY_RX_K_GAIN);
>> +
>> + /* RX Buffer Settings */
>> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
>> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
>> + writeb_relaxed(0x79, base + MIPHY_RX_EQU_GAIN_1);
>> + writeb_relaxed(0x56, base + MIPHY_RX_EQU_GAIN_2);
>> +
>> + /* Gen 2 */
>> + writeb_relaxed(0x01, base + MIPHY_CONF);
>> + writeb_relaxed(0x0a, base + MIPHY_SPEED);
>> + writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
>> + writeb_relaxed(0xa5, base + MIPHY_BIAS_BOOST_2);
>> +
>> + /* TX buffer Settings */
>> + writeb_relaxed(0x07, base + MIPHY_TX_CTRL_1);
>> + writeb_relaxed(0x70, base + MIPHY_TX_CTRL_2);
>> + writeb_relaxed(0x60, base + MIPHY_TX_CTRL_3);
>> + writeb_relaxed(0xcc, base + MIPHY_RX_K_GAIN);
>> +
>> + /* RX Buffer Settings */
>> + writeb_relaxed(0x0d, base + MIPHY_RX_BUFFER_CTRL);
>> + writeb_relaxed(0x00, base + MIPHY_RX_VGA_GAIN);
>> + writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
>> + writeb_relaxed(0x07, base + MIPHY_RX_EQU_GAIN_2);
>> +
>> + writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
>> +
>> + /* Macro out of reset */
>> + writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
>> +
>> + /* Poll for HFC ready after reset release */
>> + /* Compensation measurement */
>> + writeb_relaxed(0x05, base + MIPHY_RESET);
>> + writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
>> + writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
>> + writeb_relaxed(0x40, base + MIPHY_COMP_FSM_1);
>> +
>> + /* extra delay to wait pll lock */
>> + usleep_range(100, 120);
>> +
>> + writeb_relaxed(0x01, base + MIPHY_RESET);
>> + writeb_relaxed(0x00, base + MIPHY_RESET);
>> + writeb_relaxed(0x40, base + MIPHY_PLL_COMMON_MISC_2);
>> + writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
>
> Are all these settings necessary? Can't we have a bare minimal settings needed
> to get the PHY functional.
Yes all settings are necessary.
>
> Thanks
> Kishon
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE
2014-09-08 15:15 ` Kishon Vijay Abraham I
@ 2014-09-09 9:23 ` Gabriel Fernandez
0 siblings, 0 replies; 15+ messages in thread
From: Gabriel Fernandez @ 2014-09-09 9:23 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin,
Patrice Chotard, Russell King, Grant Likely, devicetree,
linux-kernel, linux-arm-kernel, kernel, Harsh Gupta,
Gabriel Fernandez
Hi Kishon,
On 8 September 2014 17:15, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
>
> On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
>> SSC is the technique of modulating the operating frequency of a signal
>> slightly to spread its radiated emissions over a range of frequencies.
>> This reduction in the maximum emission for a given frequency helps meet
>> radiated emission requirements.
>> These settings are applicable for PCIE with Internal clock.
>>
>> Signed-off-by: Harsh Gupta <harsh.gupta@st.com>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.orgm>
>> ---
>> drivers/phy/phy-miphy28lp.c | 32 ++++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
>> index b36e737..976fdda 100644
>> --- a/drivers/phy/phy-miphy28lp.c
>> +++ b/drivers/phy/phy-miphy28lp.c
>> @@ -679,6 +679,36 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
>> return miphy_is_ready(miphy_phy);
>> }
>>
>> +static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
>> +{
>> + u8 val;
>> +
>> + /* Compensate Tx impedance to avoid out of range values */
>> + if (miphy_phy->ssc) {
>> + /*
>> + * Enable the SSC on PLL for all banks
>> + * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
>> + */
>> + val = readb_relaxed(miphy_phy->base + 0x0c);
>> + val |= 0x04;
>> + writeb_relaxed(val, miphy_phy->base + 0x0c);
>> + val = readb_relaxed(miphy_phy->base + 0x0a);
>> + val |= 0x10;
>> + writeb_relaxed(val, miphy_phy->base + 0x0a);
>
> macros for these registers and values is needed. Or else it's difficult to review.
ok will be fix to v3
>> +
>> + for (val = 0; val < 2; val++) {
>> + writeb_relaxed(val, miphy_phy->base + 0x0f);
>> + writeb_relaxed(0x69, miphy_phy->base + 0xe5);
>
> Do these registers have to be written for every iteration?
Yes because we select the bank value before (with val)
>
> Thanks
> Kishon
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
2014-09-08 14:33 ` Kishon Vijay Abraham I
@ 2014-09-09 9:24 ` Gabriel Fernandez
0 siblings, 0 replies; 15+ messages in thread
From: Gabriel Fernandez @ 2014-09-09 9:24 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Gabriel FERNANDEZ, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Srinivas Kandagatla, Maxime Coquelin,
Patrice Chotard, Russell King, Grant Likely, devicetree,
linux-kernel, linux-arm-kernel, kernel, alexandre torgue,
Giuseppe Cavallaro
Hi Kishon,
ok will be fix to v3
BR
Gabriel
On 8 September 2014 16:33, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Hi,
>
> On Wednesday 03 September 2014 09:07 PM, Gabriel FERNANDEZ wrote:
>> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
>> or USB3 devices.
>>
>> Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
>> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
>> ---
>> .../devicetree/bindings/phy/phy-miphy28lp.txt | 126 +++++++++++++++++++++
>> 1 file changed, 126 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
>> new file mode 100644
>> index 0000000..5e307af
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
>> @@ -0,0 +1,126 @@
>> +STMicroelectronics STi MIPHY28LP PHY binding
>> +============================================
>> +
>> +This binding describes a miphy device that is used to control PHY hardware
>> +for SATA, PCIe or USB3.
>> +
>> +Required properties (controller (parent) node):
>> +- compatible : Should be "st,miphy28lp-phy"
>> +- st,syscfg : Should be a phandle of the system configuration register group
>> + which contain the SATA, PCIe or USB3 mode setting bits
>> +
>> +Required nodes : A sub-node is required for each channel the controller
>> + provides. Address range information including the usual
>> + 'reg' and 'reg-names' properties are used inside these
>> + nodes to describe the controller's topology. These nodes
>> + are translated by the driver's .xlate() function.
>> +
>> +Required properties (port (child) node):
>> +- #phy-cells : Should be 1 (See second example)
>> + Cell after port phandle is device type from:
>> + - MIPHY_TYPE_SATA
>> + - MIPHY_TYPE_PCI
>> + - MIPHY_TYPE_USB3
>> +- reg : Address and length of the register set for the device
>> +- reg-names : The names of the register addresses corresponding to the registers
>> + filled in "reg". Is can also contain the offset of the system configuration
>
> %s/Is/It
>
> Thanks
> Kishon
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2014-09-09 9:24 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-09-03 15:37 [PATCH v2 0/8] phy: miphy28lp: Introduce support for MiPHY28lp Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 1/8] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Gabriel FERNANDEZ
2014-09-08 14:33 ` Kishon Vijay Abraham I
2014-09-09 9:24 ` Gabriel Fernandez
2014-09-03 15:37 ` [PATCH v2 2/8] phy: miphy28lp: Add MiPHY28lp header file for DT x Driver defines Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 3/8] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY Gabriel FERNANDEZ
2014-09-08 15:12 ` Kishon Vijay Abraham I
2014-09-09 9:15 ` Gabriel Fernandez
2014-09-03 15:37 ` [PATCH v2 4/8] ARM: DT: STi: STiH407: Add DT node for MiPHY28lp Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 5/8] ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe & USB3) PHY Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 6/8] phy: miphy28lp: Add SSC support for SATA Gabriel FERNANDEZ
2014-09-03 15:37 ` [PATCH v2 7/8] phy: miphy28lp: Add SSC support for PCIE Gabriel FERNANDEZ
2014-09-08 15:15 ` Kishon Vijay Abraham I
2014-09-09 9:23 ` Gabriel Fernandez
2014-09-03 15:37 ` [PATCH v2 8/8] phy: miphy28lp: Tune tx impedance across Soc cuts Gabriel FERNANDEZ
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