From: jonghwan Choi <jhbird.choi@gmail.com>
To: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Jonghwan Choi <jhbird.choi@samsung.com>,
Nishanth Menon <nm@ti.com>,
Linux PM list <linux-pm@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Len Brown <len.brown@intel.com>,
Amit Daniel Kachhap <amit.daniel@samsung.com>
Subject: Re: [PATCH 1/3] PM / OPP: Add support for descending order for cpufreq table
Date: Fri, 9 May 2014 04:59:28 -0700 [thread overview]
Message-ID: <CAGZ6kuO_N+bZpWa8uQiZUCTWscMbwAd7EL-1dbCJX9JCvFDnyQ@mail.gmail.com> (raw)
In-Reply-To: <CAKohpomX_ZXSyk7RuCyO1t8VUee5H5KN5zj1-VhDp+ZtFbF-xA@mail.gmail.com>
On Thu, May 8, 2014 at 11:00 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> Why? So, as far as I got it your dividers are nothing but 0,1,2...
> i.e.
> Freqs: 400 500 600 700 800
> div: 4 3 2 1 0
>
> right? That's what you are doing in exynos5440. So just add this in your
> probe after doing: dev_pm_opp_init_cpufreq_table
>
> for(i = 0; all-available-freqs; i++)
> dvfs_info->freq_table[i].driver_data = dvfs_info->freq_count - i;
>
> And this will work with changes in dts files.
I am sorry
I couldn’t provide detailed information about this suggestion.
This suggestion is not for exynos5440. This is for exynos4210,
exynos4x12 and exynos5250.
(But this can be applied to exynos5440 also)
I want to make exynos cpufreq driver simple.
There are exynos-cpufreq.c, exynos4210-cpufreq.c exynos4x12-cpufreq.
exynos5250-cpufreq.c for exynos soc.
And exynos4210-cpufreq.c, exynos4x12 and exynos5250-cpufreq. c has a
clk divider table for each frequency.
example) exynos4210-cpufreq.c
static struct apll_freq apll_freq_4210[] = {
/*
* values:
* freq
* clock divider for CORE, COREM0, COREM1, PERIPH, ATB,
PCLK_DBG, APLL, RESERVED
* clock divider for COPY, HPM, RESERVED
* PLL M, P, S
*/
APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
};
If we can pass this clk divider value to exynos cpufreq driver through
DT, we can remove most of exynosxxxx-cpufreq.c files/codes. And when
new frequency is added/removed or new soc is released, for supporting
dvfs we have only to describe frequency, voltage and divider value in
dts file.
Thanks
Best Regards.
next prev parent reply other threads:[~2014-05-09 11:59 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-30 6:28 [PATCH 1/3] PM / OPP: Add support for descending order for cpufreq table Jonghwan Choi
2014-04-30 8:25 ` Viresh Kumar
2014-05-03 0:16 ` Jonghwan Choi
2014-05-05 5:54 ` Viresh Kumar
2014-05-05 13:38 ` Nishanth Menon
2014-05-05 14:14 ` Viresh Kumar
2014-05-05 14:23 ` Nishanth Menon
2014-05-05 14:38 ` Viresh Kumar
2014-05-05 14:46 ` Nishanth Menon
2014-05-06 23:43 ` Jonghwan Choi
2014-05-07 1:00 ` Nishanth Menon
2014-05-07 6:04 ` Viresh Kumar
2014-05-08 1:22 ` Jonghwan Choi
2014-05-08 1:55 ` Nishanth Menon
2014-05-08 2:07 ` Jonghwan Choi
2014-05-08 5:55 ` Viresh Kumar
2014-05-09 1:09 ` Jonghwan Choi
2014-05-09 6:00 ` Viresh Kumar
2014-05-09 11:59 ` jonghwan Choi [this message]
2014-05-09 13:23 ` Nishanth Menon
2014-05-11 11:38 ` jonghwan Choi
2014-05-12 6:18 ` Viresh Kumar
2014-05-08 5:50 ` Viresh Kumar
2014-05-06 17:25 ` Sudeep Holla
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