Re: [PATCH 1/3] PM / OPP: Add support for descending order for cpufreq table

[jonghwan Choi <jhbird.choi@gmail.com>]

On Fri, May 9, 2014 at 6:23 AM, Nishanth Menon <nm@ti.com> wrote:
> Have you considered the option of having a clock driver which can
> decide the divider (based on dts OR index or whatever)?
>
> example: you could do clk_set_rate(apll, rate);
> and instead of implementing clock divider programmation inside cpufreq
> driver, you let corresponding clock driver do it for you. that allows
> you to reuse clock driver with various parameters needed for your SoC
> variations. IMHO, we are trying to solve a problem meant to be solved
> in clock framework instead of within cpufreq.


I already considered it.
(But it only passes on  what cpufreq driver has to do to clock framework.
For changing clock rate, if changing operation just divides a rate of
parent it can be solved easily
But exycpufreq driver is  more complicated.

Previously, to change frequency, pll value and clk divider value were
changed in cpufreq driver.
Later someone moved the code which changes pll value to clock framework.
In there, pll values are maintained as table per frequency. And if
frequency is added/removed, values of
pll table should be changed.
when we change the pll value through clk_set_rate, internally  to find
proper pll value,  pll table is searched.
If proper pll value is found, that value is written into the register)

My suggestion is that all these change details should be removed
according to adding/removing frequency.
I believe that cpufreq driver just writes a specific value per
frequency  into the register for dvfs(Maybe other work is also needed)

If we just describe the specific value per frequency in dts file, the
driver will get that information through DT, and use it for DVFS.)
Then when a new chip is  released(if the chip has the same h/w
interface - register map), we only have to do as above.


Thanks

Best Regards