From: Raghavendra Rao Ananta <rananta@google.com>
To: Eric Auger <eauger@redhat.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
Marc Zyngier <maz@kernel.org>,
Alexandru Elisei <alexandru.elisei@arm.com>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Shaoqin Huang <shahuang@redhat.com>,
Jing Zhang <jingzhangos@google.com>,
Reiji Watanabe <reijiw@google.com>,
Colton Lewis <coltonlewis@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v7 03/12] KVM: arm64: PMU: Clear PM{C,I}NTEN{SET,CLR} and PMOVS{SET,CLR} on vCPU reset
Date: Mon, 16 Oct 2023 14:28:58 -0700 [thread overview]
Message-ID: <CAJHc60wYyfsJPiFEyLYLyv9femNzDUXy+xFaGx59=2HrUGScyw@mail.gmail.com> (raw)
In-Reply-To: <53546f35-f2cc-4c75-171c-26719550f7df@redhat.com>
On Mon, Oct 16, 2023 at 12:45 PM Eric Auger <eauger@redhat.com> wrote:
>
> Hi Raghavendra,
>
> On 10/10/23 01:08, Raghavendra Rao Ananta wrote:
> > From: Reiji Watanabe <reijiw@google.com>
> >
> > On vCPU reset, PMCNTEN{SET,CLR}_EL0, PMINTEN{SET,CLR}_EL1, and
> > PMOVS{SET,CLR}_EL1 for a vCPU are reset by reset_pmu_reg().
> PMOVS{SET,CLR}_EL0?
Ah, yes. It should be PMOVS{SET,CLR}_EL0.
> > This function clears RAZ bits of those registers corresponding
> > to unimplemented event counters on the vCPU, and sets bits
> > corresponding to implemented event counters to a predefined
> > pseudo UNKNOWN value (some bits are set to 1).
> >
> > The function identifies (un)implemented event counters on the
> > vCPU based on the PMCR_EL0.N value on the host. Using the host
> > value for this would be problematic when KVM supports letting
> > userspace set PMCR_EL0.N to a value different from the host value
> > (some of the RAZ bits of those registers could end up being set to 1).
> >
> > Fix this by clearing the registers so that it can ensure
> > that all the RAZ bits are cleared even when the PMCR_EL0.N value
> > for the vCPU is different from the host value. Use reset_val() to
> > do this instead of fixing reset_pmu_reg(), and remove
> > reset_pmu_reg(), as it is no longer used.
> do you intend to restore the 'unknown' behavior at some point?
>
I believe Reiji's (original author) intention was to keep them
cleared, which would still imply an 'unknown' behavior. Do you think
there's an issue with this?
Thank you.
Raghavendra
> Thanks
>
> Eric
> >
> > Signed-off-by: Reiji Watanabe <reijiw@google.com>
> > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> > ---
> > arch/arm64/kvm/sys_regs.c | 21 +--------------------
> > 1 file changed, 1 insertion(+), 20 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index 818a52e257ed..3dbb7d276b0e 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -717,25 +717,6 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
> > return REG_HIDDEN;
> > }
> >
> > -static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > -{
> > - u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
> > -
> > - /* No PMU available, any PMU reg may UNDEF... */
> > - if (!kvm_arm_support_pmu_v3())
> > - return 0;
> > -
> > - n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
> > - n &= ARMV8_PMU_PMCR_N_MASK;
> > - if (n)
> > - mask |= GENMASK(n - 1, 0);
> > -
> > - reset_unknown(vcpu, r);
> > - __vcpu_sys_reg(vcpu, r->reg) &= mask;
> > -
> > - return __vcpu_sys_reg(vcpu, r->reg);
> > -}
> > -
> > static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > {
> > reset_unknown(vcpu, r);
> > @@ -1115,7 +1096,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> > trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
> >
> > #define PMU_SYS_REG(name) \
> > - SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
> > + SYS_DESC(SYS_##name), .reset = reset_val, \
> > .visibility = pmu_visibility
> >
> > /* Macro to expand the PMEVCNTRn_EL0 register */
>
next prev parent reply other threads:[~2023-10-16 21:29 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 23:08 [PATCH v7 00/12] KVM: arm64: PMU: Allow userspace to limit the number of PMCs on vCPU Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 01/12] KVM: arm64: PMU: Introduce helpers to set the guest's PMU Raghavendra Rao Ananta
2023-10-16 19:45 ` Eric Auger
2023-10-09 23:08 ` [PATCH v7 02/12] KVM: arm64: PMU: Set the default PMU for the guest before vCPU reset Raghavendra Rao Ananta
2023-10-10 22:25 ` Oliver Upton
2023-10-13 20:27 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 03/12] KVM: arm64: PMU: Clear PM{C,I}NTEN{SET,CLR} and PMOVS{SET,CLR} on " Raghavendra Rao Ananta
2023-10-16 19:44 ` Eric Auger
2023-10-16 21:28 ` Raghavendra Rao Ananta [this message]
2023-10-17 9:23 ` Eric Auger
2023-10-17 16:59 ` Raghavendra Rao Ananta
2023-10-18 21:16 ` Raghavendra Rao Ananta
2023-10-18 22:17 ` Oliver Upton
2023-10-19 18:46 ` Raghavendra Rao Ananta
2023-10-19 19:05 ` Oliver Upton
2023-10-19 20:17 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 04/12] KVM: arm64: PMU: Don't define the sysreg reset() for PM{USERENR,CCFILTR}_EL0 Raghavendra Rao Ananta
2023-10-16 19:47 ` Eric Auger
2023-10-09 23:08 ` [PATCH v7 05/12] KVM: arm64: PMU: Add a helper to read a vCPU's PMCR_EL0 Raghavendra Rao Ananta
2023-10-16 20:02 ` Eric Auger
2023-10-09 23:08 ` [PATCH v7 06/12] KVM: arm64: PMU: Add a helper to read the number of counters Raghavendra Rao Ananta
2023-10-10 22:30 ` Oliver Upton
2023-10-13 5:43 ` Oliver Upton
2023-10-13 20:24 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 07/12] KVM: arm64: PMU: Set PMCR_EL0.N for vCPU based on the associated PMU Raghavendra Rao Ananta
2023-10-16 13:35 ` Sebastian Ott
2023-10-16 19:02 ` Raghavendra Rao Ananta
2023-10-16 19:15 ` Oliver Upton
2023-10-16 21:35 ` Raghavendra Rao Ananta
2023-10-17 5:52 ` Oliver Upton
2023-10-17 5:55 ` Oliver Upton
2023-10-17 16:58 ` Raghavendra Rao Ananta
2023-10-17 17:09 ` Oliver Upton
2023-10-17 17:25 ` Raghavendra Rao Ananta
2023-10-17 18:10 ` Oliver Upton
2023-10-17 18:45 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 08/12] KVM: arm64: PMU: Allow userspace to limit PMCR_EL0.N for the guest Raghavendra Rao Ananta
2023-10-17 15:52 ` Sebastian Ott
2023-10-17 16:49 ` Raghavendra Rao Ananta
2023-10-19 10:45 ` Sebastian Ott
2023-10-19 18:05 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 09/12] tools: Import arm_pmuv3.h Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 10/12] KVM: selftests: aarch64: Introduce vpmu_counter_access test Raghavendra Rao Ananta
2023-10-12 11:24 ` Sebastian Ott
2023-10-12 15:01 ` Sebastian Ott
2023-10-13 21:05 ` Raghavendra Rao Ananta
2023-10-16 10:01 ` Sebastian Ott
2023-10-16 18:56 ` Oliver Upton
2023-10-16 19:05 ` Raghavendra Rao Ananta
2023-10-16 19:07 ` Oliver Upton
2023-10-17 14:51 ` Eric Auger
2023-10-17 17:07 ` Raghavendra Rao Ananta
2023-10-17 15:48 ` Sebastian Ott
2023-10-17 17:10 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 11/12] KVM: selftests: aarch64: vPMU register test for implemented counters Raghavendra Rao Ananta
2023-10-17 18:54 ` Eric Auger
2023-10-17 21:42 ` Raghavendra Rao Ananta
2023-10-09 23:08 ` [PATCH v7 12/12] KVM: selftests: aarch64: vPMU register test for unimplemented counters Raghavendra Rao Ananta
2023-10-18 6:54 ` Eric Auger
2023-10-19 18:09 ` Raghavendra Rao Ananta
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