From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
To: Andrew Lunn <andrew@lunn.ch>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Samin Guo <samin.guo@starfivetech.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Jose Abreu <joabreu@synopsys.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Richard Cochran <richardcochran@gmail.com>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, kernel@collabora.com,
Emil Renner Berthing <emil.renner.berthing@canonical.com>
Subject: Re: [PATCH v2 08/12] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
Date: Tue, 31 Oct 2023 07:56:38 -0700 [thread overview]
Message-ID: <CAJM55Z_+A1jceB5QWwZ9=roAs7jeAb7E-CEdw3mSOng=jyVDYg@mail.gmail.com> (raw)
In-Reply-To: <9b8c9846-20be-4cfa-aff5-f9ae8ac2aba4@lunn.ch>
Andrew Lunn wrote:
> On Sun, Oct 29, 2023 at 06:27:08AM +0200, Cristian Ciocaltea wrote:
> > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers
> > expect to be able to allocate coherent memory for DMA descriptors and
> > such. However on the JH7100 DDR memory appears twice in the physical
> > memory map, once cached and once uncached:
> >
> > 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached
> > 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached
> >
> > To use this uncached region we create a global DMA memory pool there and
> > reserve the corresponding area in the cached region.
> >
> > However the uncached region is fully above the 32bit address limit, so add
> > a dma-ranges map so the DMA address used for peripherals is still in the
> > regular cached region below the limit.
> >
> > Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> > ---
> > .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> > index b93ce351a90f..504c73f01f14 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> > @@ -39,6 +39,30 @@ led-ack {
> > label = "ack";
> > };
> > };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + dma-reserved {
> > + reg = <0x0 0xfa000000 0x0 0x1000000>;
>
> If i'm reading this correctly, this is at the top of the first 4G of
> RAM. But this is jh7100-common.dtsi. Is it guaranteed that all boards
> derived from this have at least 4G? What happens is a board only has
> 2G?
Yes, both the BeagleV Starlight and StarFive VisionFive V1 boards have at least
4G of ram and there won't be any more boards with this SoC. It was a test chip
for the JH7110 after all.
There aren't really any limitations on where this pool could be placed, so I
just chose to wedge it between ranges reserved for graphics by the bootloader.
If anyone has a better idea please go ahead and change it.
>
> It might also be worth putting a comment here about the memory being
> mapped twice. In the ARM world that would be illegal, so its maybe not
> seen that often. Yes, the commit message explains that, but when i
> look at the code on its own, it is less obvious.
>
> > + no-map;
> > + };
> > +
> > + linux,dma {
> > + compatible = "shared-dma-pool";
> > + reg = <0x10 0x7a000000 0x0 0x1000000>;
> > + no-map;
> > + linux,dma-default;
> > + };
> > + };
next prev parent reply other threads:[~2023-10-31 14:56 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-29 4:27 [PATCH v2 00/12] Enable networking support for StarFive JH7100 SoC Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 01/12] dt-bindings: net: snps,dwmac: Allow exclusive usage of ahb reset Cristian Ciocaltea
2023-10-29 11:21 ` Krzysztof Kozlowski
2023-10-29 21:55 ` Cristian Ciocaltea
2023-10-29 22:02 ` Cristian Ciocaltea
2023-10-29 11:25 ` Krzysztof Kozlowski
2023-10-29 22:24 ` Cristian Ciocaltea
2023-10-30 7:26 ` Krzysztof Kozlowski
2023-10-30 19:07 ` Cristian Ciocaltea
2023-10-31 5:48 ` Krzysztof Kozlowski
2023-10-31 11:00 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 02/12] dt-bindings: net: starfive,jh7110-dwmac: Drop superfluous select Cristian Ciocaltea
2023-10-29 11:18 ` Krzysztof Kozlowski
2023-10-29 21:08 ` Cristian Ciocaltea
2023-10-30 7:27 ` Krzysztof Kozlowski
2023-10-30 19:25 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 03/12] dt-bindings: net: starfive,jh7110-dwmac: Drop redundant reset description Cristian Ciocaltea
2023-10-29 11:19 ` Krzysztof Kozlowski
2023-10-29 21:23 ` Cristian Ciocaltea
2023-10-30 7:29 ` Krzysztof Kozlowski
2023-10-30 19:35 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 04/12] dt-bindings: net: starfive,jh7110-dwmac: Add JH7100 SoC compatible Cristian Ciocaltea
2023-10-29 11:24 ` Krzysztof Kozlowski
2023-10-29 22:15 ` Cristian Ciocaltea
2023-10-30 7:30 ` Krzysztof Kozlowski
2023-10-30 20:02 ` Cristian Ciocaltea
2023-10-30 1:37 ` Rob Herring
2023-10-30 7:29 ` Krzysztof Kozlowski
2023-10-29 4:27 ` [PATCH v2 05/12] net: stmmac: dwmac-starfive: Add support for JH7100 SoC Cristian Ciocaltea
2023-10-31 14:33 ` Emil Renner Berthing
2023-10-31 18:07 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 06/12] riscv: dts: starfive: jh7100: Add dma-noncoherent property Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 07/12] riscv: dts: starfive: jh7100: Add ccache DT node Cristian Ciocaltea
2023-10-31 14:38 ` Emil Renner Berthing
2023-10-31 19:01 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 08/12] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards Cristian Ciocaltea
2023-10-29 18:35 ` Andrew Lunn
2023-10-31 14:56 ` Emil Renner Berthing [this message]
2023-10-31 14:40 ` Emil Renner Berthing
2023-10-31 19:16 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 09/12] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes Cristian Ciocaltea
2023-11-26 21:15 ` Emil Renner Berthing
2023-11-28 0:46 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 10/12] riscv: dts: starfive: jh7100-common: Setup gmac pinmux Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 11/12] riscv: dts: starfive: visionfive-v1: Enable gmac and setup phy Cristian Ciocaltea
2023-10-29 18:45 ` Andrew Lunn
2023-10-29 22:41 ` Cristian Ciocaltea
2023-10-29 22:50 ` Andrew Lunn
2023-10-29 23:35 ` Cristian Ciocaltea
2023-10-29 4:27 ` [PATCH v2 12/12] [UNTESTED] riscv: dts: starfive: beaglev-starlight: Enable gmac Cristian Ciocaltea
2023-10-29 18:46 ` Andrew Lunn
2023-10-29 22:53 ` Cristian Ciocaltea
2023-11-16 13:15 ` Cristian Ciocaltea
2023-11-16 17:55 ` Conor Dooley
2023-11-16 18:30 ` Cristian Ciocaltea
2023-11-17 8:37 ` Geert Uytterhoeven
2023-11-17 8:49 ` Cristian Ciocaltea
2023-11-17 8:58 ` Cristian Ciocaltea
2023-11-17 9:12 ` Geert Uytterhoeven
2023-11-17 11:19 ` Cristian Ciocaltea
2023-11-17 22:48 ` Cristian Ciocaltea
2023-11-26 21:10 ` Emil Renner Berthing
2023-11-28 0:40 ` Cristian Ciocaltea
2023-11-28 12:08 ` Emil Renner Berthing
2023-11-28 15:47 ` Cristian Ciocaltea
2023-11-28 16:09 ` Emil Renner Berthing
2023-11-28 16:22 ` Cristian Ciocaltea
2023-11-29 14:28 ` Emil Renner Berthing
2023-11-29 14:59 ` Cristian Ciocaltea
2023-12-15 21:13 ` Cristian Ciocaltea
2023-12-16 19:24 ` Emil Renner Berthing
2023-12-18 11:38 ` Cristian Ciocaltea
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