From: Jim Mattson <jmattson@google.com>
To: Yang Weijiang <weijiang.yang@intel.com>
Cc: "kvm list" <kvm@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Sean Christopherson" <sean.j.christopherson@intel.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>
Subject: Re: [PATCH v7 7/7] KVM: x86: Add user-space access interface for CET MSRs
Date: Wed, 2 Oct 2019 13:57:50 -0700 [thread overview]
Message-ID: <CALMp9eQNDNmmCr8DM-2fMVYvQ-eTEpeE=bW8+BLbfxmBsTmQvg@mail.gmail.com> (raw)
In-Reply-To: <20190927021927.23057-8-weijiang.yang@intel.com>
On Thu, Sep 26, 2019 at 7:17 PM Yang Weijiang <weijiang.yang@intel.com> wrote:
>
> There're two different places storing Guest CET states, the states
> managed with XSAVES/XRSTORS, as restored/saved
> in previous patch, can be read/write directly from/to the MSRs.
> For those stored in VMCS fields, they're access via vmcs_read/
> vmcs_write.
>
> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> ---
> arch/x86/kvm/vmx/vmx.c | 83 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 44913e4ab558..5265db7cd2af 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -1671,6 +1671,49 @@ static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
> return 0;
> }
>
> +static int check_cet_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
I'd suggest changing return type to bool, since you are essentially
returning true or false.
> +{
> + u64 kvm_xss = kvm_supported_xss();
> +
> + switch (msr_info->index) {
> + case MSR_IA32_PL0_SSP ... MSR_IA32_PL2_SSP:
> + if (!(kvm_xss | XFEATURE_MASK_CET_KERNEL))
'|' should be '&'
> + return 1;
> + if (!msr_info->host_initiated &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK))
> + return 1;
> + break;
> + case MSR_IA32_PL3_SSP:
> + if (!(kvm_xss | XFEATURE_MASK_CET_USER))
'|' should be '&'
> + return 1;
> + if (!msr_info->host_initiated &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK))
> + return 1;
> + break;
> + case MSR_IA32_U_CET:
> + if (!(kvm_xss | XFEATURE_MASK_CET_USER))
'|' should be '&'
> + return 1;
> + if (!msr_info->host_initiated &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_IBT))
> + return 1;
> + break;
> + case MSR_IA32_S_CET:
> + if (!msr_info->host_initiated &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK) &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_IBT))
> + return 1;
> + break;
> + case MSR_IA32_INT_SSP_TAB:
> + if (!msr_info->host_initiated &&
> + !guest_cpuid_has(vcpu, X86_FEATURE_SHSTK))
> + return 1;
> + break;
> + default:
> + return 1;
> + }
> + return 0;
> +}
> /*
> * Reads an msr value (of 'msr_index') into 'pdata'.
> * Returns 0 on success, non-0 otherwise.
> @@ -1788,6 +1831,26 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> else
> msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
> break;
> + case MSR_IA32_S_CET:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
> + msr_info->data = vmcs_readl(GUEST_S_CET);
Have we ensured that this VMCS field exists?
> + break;
> + case MSR_IA32_INT_SSP_TAB:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
> + msr_info->data = vmcs_readl(GUEST_INTR_SSP_TABLE);
Have we ensured that this VMCS field exists?
> + break;
> + case MSR_IA32_U_CET:
Can this be lumped together with MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP, below?
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
> + rdmsrl(MSR_IA32_U_CET, msr_info->data);
> + break;
> + case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
> + rdmsrl(msr_info->index, msr_info->data);
> + break;
> case MSR_TSC_AUX:
> if (!msr_info->host_initiated &&
> !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
> @@ -2039,6 +2102,26 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> else
> vmx->pt_desc.guest.addr_a[index / 2] = data;
> break;
> + case MSR_IA32_S_CET:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
Bits 9:6 must be zero.
> + vmcs_writel(GUEST_S_CET, data);
Have we ensured that this VMCS field exists?
> + break;
> + case MSR_IA32_INT_SSP_TAB:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
Must be canonical. vCPU must support longmode.
> + vmcs_writel(GUEST_INTR_SSP_TABLE, data);
Have we ensured that this VMCS field exists?
> + break;
> + case MSR_IA32_U_CET:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
Bits 9:6 must be zero.
> + wrmsrl(MSR_IA32_U_CET, data);
> + break;
> + case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP:
> + if (check_cet_msr(vcpu, msr_info))
> + return 1;
'Data' must be canonical and 4-byte aligned. High dword must be zero
on vCPUs that don't support longmode.
> + wrmsrl(msr_info->index, data);
> + break;
> case MSR_TSC_AUX:
> if (!msr_info->host_initiated &&
> !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
> --
> 2.17.2
>
next prev parent reply other threads:[~2019-10-02 20:58 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-27 2:19 [PATCH v7 0/7] Introduce support for Guest CET feature Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 1/7] KVM: CPUID: Fix IA32_XSS support in CPUID(0xd,i) enumeration Yang Weijiang
2019-10-02 17:26 ` Jim Mattson
2019-10-08 8:30 ` Yang Weijiang
2019-10-17 19:46 ` Sean Christopherson
2019-10-18 1:28 ` Yang Weijiang
2019-10-22 19:46 ` Sean Christopherson
2019-10-23 1:16 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 2/7] kvm: vmx: Define CET VMCS fields and CPUID flags Yang Weijiang
2019-10-02 18:04 ` Jim Mattson
2019-10-09 5:56 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 3/7] KVM: VMX: Pass through CET related MSRs to Guest Yang Weijiang
2019-10-02 18:18 ` Jim Mattson
2019-10-09 6:15 ` Yang Weijiang
2019-10-10 19:04 ` Jim Mattson
2019-10-11 1:51 ` Yang Weijiang
2019-10-17 20:04 ` Sean Christopherson
2019-10-18 1:31 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 4/7] KVM: VMX: Load Guest CET via VMCS when CET is enabled in Guest Yang Weijiang
2019-10-02 18:54 ` Jim Mattson
2019-10-09 6:43 ` Yang Weijiang
2019-10-09 23:08 ` Jim Mattson
2019-10-10 1:30 ` Yang Weijiang
2019-10-10 23:44 ` Jim Mattson
2019-10-11 1:43 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 5/7] kvm: x86: Add CET CR4 bit and XSS support Yang Weijiang
2019-10-02 19:05 ` Jim Mattson
2019-10-17 19:56 ` Sean Christopherson
2019-10-18 1:58 ` Yang Weijiang
2019-10-22 20:13 ` Sean Christopherson
2019-10-23 1:19 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 6/7] KVM: x86: Load Guest fpu state when accessing MSRs managed by XSAVES Yang Weijiang
2019-10-02 19:56 ` Jim Mattson
2019-10-09 6:46 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 7/7] KVM: x86: Add user-space access interface for CET MSRs Yang Weijiang
2019-10-02 20:57 ` Jim Mattson [this message]
2019-10-09 6:56 ` Yang Weijiang
2019-10-17 19:58 ` Sean Christopherson
2019-10-18 1:32 ` Yang Weijiang
2019-10-02 22:40 ` [PATCH v7 0/7] Introduce support for Guest CET feature Jim Mattson
2019-10-03 13:01 ` Yang Weijiang
2019-10-03 16:33 ` Jim Mattson
2019-10-08 8:50 ` Yang Weijiang
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