From: Jim Mattson <jmattson@google.com>
To: Yang Weijiang <weijiang.yang@intel.com>
Cc: "kvm list" <kvm@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Sean Christopherson" <sean.j.christopherson@intel.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>
Subject: Re: [PATCH v7 5/7] kvm: x86: Add CET CR4 bit and XSS support
Date: Wed, 2 Oct 2019 12:05:23 -0700 [thread overview]
Message-ID: <CALMp9eStz-VCv5G60KFtumQ8W1Jqf9bOcK_=KwL1P3LLjgajnQ@mail.gmail.com> (raw)
In-Reply-To: <20190927021927.23057-6-weijiang.yang@intel.com>
On Thu, Sep 26, 2019 at 7:17 PM Yang Weijiang <weijiang.yang@intel.com> wrote:
>
> CR4.CET(bit 23) is master enable bit for CET feature.
> Previously, KVM did not support setting any bits in XSS
> so it's hardcoded to check and inject a #GP if Guest
> attempted to write a non-zero value to XSS, now it supports
> CET related bits setting.
>
> Co-developed-by: Zhang Yi Z <yi.z.zhang@linux.intel.com>
> Signed-off-by: Zhang Yi Z <yi.z.zhang@linux.intel.com>
> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
> ---
> arch/x86/include/asm/kvm_host.h | 4 +++-
> arch/x86/kvm/cpuid.c | 11 +++++++++--
> arch/x86/kvm/vmx/vmx.c | 6 +-----
> 3 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index d018df8c5f32..8f97269d6d9f 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -90,7 +90,8 @@
> | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
> | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
> | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
> - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
> + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \
> + | X86_CR4_CET))
>
> #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
>
> @@ -623,6 +624,7 @@ struct kvm_vcpu_arch {
>
> u64 xcr0;
> u64 guest_supported_xcr0;
> + u64 guest_supported_xss;
> u32 guest_xstate_size;
>
> struct kvm_pio_request pio;
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 0a47b9e565be..dd3ddc6daa58 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -120,8 +120,15 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu)
> }
>
> best = kvm_find_cpuid_entry(vcpu, 0xD, 1);
> - if (best && (best->eax & (F(XSAVES) | F(XSAVEC))))
> - best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
> + if (best && (best->eax & (F(XSAVES) | F(XSAVEC)))) {
Is XSAVEC alone sufficient? Don't we explicitly need XSAVES to
save/restore the extended state components enumerated by IA32_XSS?
> + u64 kvm_xss = kvm_supported_xss();
> +
> + best->ebx =
> + xstate_required_size(vcpu->arch.xcr0 | kvm_xss, true);
Shouldn't this size be based on the *current* IA32_XSS value, rather
than the supported IA32_XSS bits? (i.e.
s/kvm_xss/vcpu->arch.ia32_xss/)
> + vcpu->arch.guest_supported_xss = best->ecx & kvm_xss;
Shouldn't unsupported bits in best->ecx be masked off, so that the
guest CPUID doesn't mis-report the capabilities of the vCPU?
> + } else {
> + vcpu->arch.guest_supported_xss = 0;
> + }
>
> /*
> * The existing code assumes virtual address is 48-bit or 57-bit in the
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index ba1a83d11e69..44913e4ab558 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -1973,11 +1973,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> !(guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
> guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))))
> return 1;
> - /*
> - * The only supported bit as of Skylake is bit 8, but
> - * it is not supported on KVM.
> - */
> - if (data != 0)
> + if (data & ~vcpu->arch.guest_supported_xss)
> return 1;
> vcpu->arch.ia32_xss = data;
> if (vcpu->arch.ia32_xss != host_xss)
> --
> 2.17.2
>
next prev parent reply other threads:[~2019-10-02 19:05 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-27 2:19 [PATCH v7 0/7] Introduce support for Guest CET feature Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 1/7] KVM: CPUID: Fix IA32_XSS support in CPUID(0xd,i) enumeration Yang Weijiang
2019-10-02 17:26 ` Jim Mattson
2019-10-08 8:30 ` Yang Weijiang
2019-10-17 19:46 ` Sean Christopherson
2019-10-18 1:28 ` Yang Weijiang
2019-10-22 19:46 ` Sean Christopherson
2019-10-23 1:16 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 2/7] kvm: vmx: Define CET VMCS fields and CPUID flags Yang Weijiang
2019-10-02 18:04 ` Jim Mattson
2019-10-09 5:56 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 3/7] KVM: VMX: Pass through CET related MSRs to Guest Yang Weijiang
2019-10-02 18:18 ` Jim Mattson
2019-10-09 6:15 ` Yang Weijiang
2019-10-10 19:04 ` Jim Mattson
2019-10-11 1:51 ` Yang Weijiang
2019-10-17 20:04 ` Sean Christopherson
2019-10-18 1:31 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 4/7] KVM: VMX: Load Guest CET via VMCS when CET is enabled in Guest Yang Weijiang
2019-10-02 18:54 ` Jim Mattson
2019-10-09 6:43 ` Yang Weijiang
2019-10-09 23:08 ` Jim Mattson
2019-10-10 1:30 ` Yang Weijiang
2019-10-10 23:44 ` Jim Mattson
2019-10-11 1:43 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 5/7] kvm: x86: Add CET CR4 bit and XSS support Yang Weijiang
2019-10-02 19:05 ` Jim Mattson [this message]
2019-10-17 19:56 ` Sean Christopherson
2019-10-18 1:58 ` Yang Weijiang
2019-10-22 20:13 ` Sean Christopherson
2019-10-23 1:19 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 6/7] KVM: x86: Load Guest fpu state when accessing MSRs managed by XSAVES Yang Weijiang
2019-10-02 19:56 ` Jim Mattson
2019-10-09 6:46 ` Yang Weijiang
2019-09-27 2:19 ` [PATCH v7 7/7] KVM: x86: Add user-space access interface for CET MSRs Yang Weijiang
2019-10-02 20:57 ` Jim Mattson
2019-10-09 6:56 ` Yang Weijiang
2019-10-17 19:58 ` Sean Christopherson
2019-10-18 1:32 ` Yang Weijiang
2019-10-02 22:40 ` [PATCH v7 0/7] Introduce support for Guest CET feature Jim Mattson
2019-10-03 13:01 ` Yang Weijiang
2019-10-03 16:33 ` Jim Mattson
2019-10-08 8:50 ` Yang Weijiang
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