From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Heiko Stuebner <heiko@sntech.de>,
Atish Patra <atishp@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
Date: Tue, 20 Sep 2022 14:32:25 +0200 [thread overview]
Message-ID: <CAMuHMdW99EutciosPtOTU9AztfvfMdKTaS+YRmpmS4VnhZ9KAA@mail.gmail.com> (raw)
In-Reply-To: <20220915181558.354737-9-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> Note we have deleted the nodes from the DT for which support needs to be
> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> board DTS/I.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Dropped RB tags from Conor and Geert
> * Now re-using the SoM and carrier board DTS/I from RZ/G2UL
Thanks for the update!
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +/*
> + * DIP-Switch SW1 setting
> + * 1 : High; 0: Low
> + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
> + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
> + * Please change below macros according to SW1 setting on SoM
"on the SoM" (like in r9a07g043u11-smarc.dts)?
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK SOM
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ ethernet0;
> + /delete-property/ ethernet1;
OK
> + };
> +
> + chosen {
> + bootargs = "ignore_loglevel";
> + };
> +};
> +
> +#if (SW_SW0_DEV_SEL)
> +/delete-node/ &adc;
> +#endif
> +
> +#if (!SW_ET0_EN_N)
> +/delete-node/ ð0;
> +#endif
> +/delete-node/ ð1;
> +
> +/delete-node/ &ostm1;
> +/delete-node/ &ostm2;
Given they are all placeholders, do you really need to delete them?
(more below)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-09-20 12:32 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-15 18:15 [PATCH v3 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-15 21:13 ` Conor.Dooley
2022-09-15 21:56 ` Lad, Prabhakar
2022-09-20 12:00 ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-15 20:53 ` Heiko Stuebner
2022-09-15 18:15 ` [PATCH v3 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-15 18:15 ` [PATCH v3 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Prabhakar
2022-09-15 20:58 ` Conor.Dooley
2022-09-15 22:18 ` Lad, Prabhakar
2022-09-15 22:25 ` Conor.Dooley
2022-09-15 18:15 ` [PATCH v3 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-15 21:36 ` Conor.Dooley
2022-09-15 22:26 ` Lad, Prabhakar
2022-09-15 22:40 ` Conor Dooley
2022-09-20 12:17 ` Geert Uytterhoeven
2022-09-20 12:31 ` Conor Dooley
2022-09-20 13:46 ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-15 21:56 ` Conor.Dooley
2022-09-15 22:41 ` Lad, Prabhakar
2022-09-15 22:44 ` Conor.Dooley
2022-09-15 22:51 ` Lad, Prabhakar
2022-09-20 12:32 ` Geert Uytterhoeven [this message]
2022-09-20 14:05 ` Lad, Prabhakar
2022-09-20 15:07 ` Geert Uytterhoeven
2022-09-20 16:05 ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-20 12:34 ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
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