* [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC
@ 2020-06-20 16:36 Martin Blumenstingl
2020-06-20 16:36 ` [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller Martin Blumenstingl
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Martin Blumenstingl @ 2020-06-20 16:36 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl
Amlogic Meson6/8/8b/8m2 SoCs have two built-in MMC controllers:
- SDIO (which is supported on mainline for a long time now but is
limited to ~40MHz bus frequency)
- SDHC (which supports up to HS-200 modes at ~100MHz bus frequency but
for which we didn't have a driver)
Boards with NAND flash will now be able to use the SDIO controller for
SDIO based wifi cards and the SDHC controller for the SD card slot.
Boards with eMMC, SD card and SDIO wifi can only use two out of three
MMC based devices for now until the MMC core and Meson SDIO driver gain
support for multiple "mmc-slots" per controller.
Now that we have a driver for it, add the SDHC controller to meson.dtsi
and wire up the eMMC connection on the Endless Mini EC-100 and the
Odroid-C1.
Martin Blumenstingl (3):
ARM: dts: meson: add the SDHC MMC controller
ARM: dts: meson8b: ec100: enable the SDHC controller
ARM: dts: meson8b: odroidc1: enable the SDHC controller
arch/arm/boot/dts/meson.dtsi | 7 +++++++
arch/arm/boot/dts/meson8.dtsi | 19 +++++++++++++++++++
arch/arm/boot/dts/meson8b-ec100.dts | 25 +++++++++++++++++++++++++
arch/arm/boot/dts/meson8b-odroidc1.dts | 26 ++++++++++++++++++++++++++
arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++
arch/arm/boot/dts/meson8m2.dtsi | 4 ++++
6 files changed, 101 insertions(+)
--
2.27.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller 2020-06-20 16:36 [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Martin Blumenstingl @ 2020-06-20 16:36 ` Martin Blumenstingl 2020-06-22 12:47 ` Anand Moon 2020-06-20 16:36 ` [PATCH 2/3] ARM: dts: meson8b: ec100: enable the SDHC controller Martin Blumenstingl ` (2 subsequent siblings) 3 siblings, 1 reply; 7+ messages in thread From: Martin Blumenstingl @ 2020-06-20 16:36 UTC (permalink / raw) To: linux-amlogic, khilman Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller IP which typically connects to an eMMC chip (because unlike the SDIO controller the SDHC controller has an 8-bit bus interface). On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. However, Meson8m2 seems to have an improved version of the SHDC controller IP which doesn't require the driver to wait manually for a flush of a DMA transfer. Thus every SoC has it's own compatible string so if more difference are discovered they can be implemented. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/meson8m2.dtsi | 4 ++++ 4 files changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index ae89deaa8c9c..464057989572 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -140,6 +140,13 @@ spifc: spi@8c80 { status = "disabled"; }; + sdhc: mmc@8e00 { + compatible = "amlogic,meson-mx-sdhc"; + reg = <0x8e00 0x42>; + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + gpio_intc: interrupt-controller@9880 { compatible = "amlogic,meson-gpio-intc"; reg = <0x9880 0x10>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 3d0ab2ac5332..04688e8abce2 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -384,6 +384,15 @@ mux { }; }; + sdxc_b_pins: sdxc-b { + mux { + groups = "sdxc_d0_b", "sdxc_d13_b", + "sdxc_clk_b", "sdxc_cmd_b"; + function = "sdxc_b"; + bias-pull-up; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs"; @@ -558,6 +567,16 @@ &saradc { nvmem-cell-names = "temperature_calib"; }; +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + &sdio { compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 2069c57343e5..2401cdf5f751 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -363,6 +363,16 @@ mux { }; }; + sdxc_c_pins: sdxc-c { + mux { + groups = "sdxc_d0_c", "sdxc_d13_c", + "sdxc_d47_c", "sdxc_clk_c", + "sdxc_cmd_c"; + function = "sdxc_c"; + bias-pull-up; + }; + }; + pwm_c1_pins: pwm-c1 { mux { groups = "pwm_c1"; @@ -554,6 +564,16 @@ &saradc { nvmem-cell-names = "temperature_calib"; }; +&sdhc { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_SDHC>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; +}; + &sdio { compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index c7ddbb210366..6725dd9fd825 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -84,6 +84,10 @@ &saradc { compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&sdhc { + compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; +}; + &usb0_phy { compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; }; -- 2.27.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller 2020-06-20 16:36 ` [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller Martin Blumenstingl @ 2020-06-22 12:47 ` Anand Moon 0 siblings, 0 replies; 7+ messages in thread From: Anand Moon @ 2020-06-22 12:47 UTC (permalink / raw) To: Martin Blumenstingl Cc: linux-amlogic, Kevin Hilman, Linux Kernel, linux-arm-kernel Hi Martin, On Sat, 20 Jun 2020 at 22:07, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller > IP which typically connects to an eMMC chip (because unlike the SDIO > controller the SDHC controller has an 8-bit bus interface). > > On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. > However, Meson8m2 seems to have an improved version of the SHDC > controller IP which doesn't require the driver to wait manually for a > flush of a DMA transfer. Thus every SoC has it's own compatible string > so if more difference are discovered they can be implemented. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Please add my Reviewed-by: Anand Moon <linux.amoon@gmail.com> -Anand > --- > arch/arm/boot/dts/meson.dtsi | 7 +++++++ > arch/arm/boot/dts/meson8.dtsi | 19 +++++++++++++++++++ > arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++ > arch/arm/boot/dts/meson8m2.dtsi | 4 ++++ > 4 files changed, 50 insertions(+) > > diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi > index ae89deaa8c9c..464057989572 100644 > --- a/arch/arm/boot/dts/meson.dtsi > +++ b/arch/arm/boot/dts/meson.dtsi > @@ -140,6 +140,13 @@ spifc: spi@8c80 { > status = "disabled"; > }; > > + sdhc: mmc@8e00 { > + compatible = "amlogic,meson-mx-sdhc"; > + reg = <0x8e00 0x42>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; > + status = "disabled"; > + }; > + > gpio_intc: interrupt-controller@9880 { > compatible = "amlogic,meson-gpio-intc"; > reg = <0x9880 0x10>; > diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi > index 3d0ab2ac5332..04688e8abce2 100644 > --- a/arch/arm/boot/dts/meson8.dtsi > +++ b/arch/arm/boot/dts/meson8.dtsi > @@ -384,6 +384,15 @@ mux { > }; > }; > > + sdxc_b_pins: sdxc-b { > + mux { > + groups = "sdxc_d0_b", "sdxc_d13_b", > + "sdxc_clk_b", "sdxc_cmd_b"; > + function = "sdxc_b"; > + bias-pull-up; > + }; > + }; > + > spi_nor_pins: nor { > mux { > groups = "nor_d", "nor_q", "nor_c", "nor_cs"; > @@ -558,6 +567,16 @@ &saradc { > nvmem-cell-names = "temperature_calib"; > }; > > +&sdhc { > + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; > + clocks = <&xtal>, > + <&clkc CLKID_FCLK_DIV4>, > + <&clkc CLKID_FCLK_DIV3>, > + <&clkc CLKID_FCLK_DIV5>, > + <&clkc CLKID_SDHC>; > + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; > +}; > + > &sdio { > compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; > clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; > diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi > index 2069c57343e5..2401cdf5f751 100644 > --- a/arch/arm/boot/dts/meson8b.dtsi > +++ b/arch/arm/boot/dts/meson8b.dtsi > @@ -363,6 +363,16 @@ mux { > }; > }; > > + sdxc_c_pins: sdxc-c { > + mux { > + groups = "sdxc_d0_c", "sdxc_d13_c", > + "sdxc_d47_c", "sdxc_clk_c", > + "sdxc_cmd_c"; > + function = "sdxc_c"; > + bias-pull-up; > + }; > + }; > + > pwm_c1_pins: pwm-c1 { > mux { > groups = "pwm_c1"; > @@ -554,6 +564,16 @@ &saradc { > nvmem-cell-names = "temperature_calib"; > }; > > +&sdhc { > + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; > + clocks = <&xtal>, > + <&clkc CLKID_FCLK_DIV4>, > + <&clkc CLKID_FCLK_DIV3>, > + <&clkc CLKID_FCLK_DIV5>, > + <&clkc CLKID_SDHC>; > + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; > +}; > + > &sdio { > compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; > clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; > diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi > index c7ddbb210366..6725dd9fd825 100644 > --- a/arch/arm/boot/dts/meson8m2.dtsi > +++ b/arch/arm/boot/dts/meson8m2.dtsi > @@ -84,6 +84,10 @@ &saradc { > compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; > }; > > +&sdhc { > + compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc"; > +}; > + > &usb0_phy { > compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; > }; > -- > 2.27.0 > > > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] ARM: dts: meson8b: ec100: enable the SDHC controller 2020-06-20 16:36 [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Martin Blumenstingl 2020-06-20 16:36 ` [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller Martin Blumenstingl @ 2020-06-20 16:36 ` Martin Blumenstingl 2020-06-20 16:36 ` [PATCH 3/3] ARM: dts: meson8b: odroidc1: " Martin Blumenstingl 2020-07-13 19:03 ` [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Kevin Hilman 3 siblings, 0 replies; 7+ messages in thread From: Martin Blumenstingl @ 2020-06-20 16:36 UTC (permalink / raw) To: linux-amlogic, khilman Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl EC-100 has built-in eMMC flash which is hard-wired to 3.3V VCC (which means it's limited to high-speed MMC modes). Enable the SDHC controller to access the contents of the eMMC flash. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- arch/arm/boot/dts/meson8b-ec100.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 163a200d5a7b..ed06102a4014 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -27,6 +27,11 @@ memory { reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -299,6 +304,26 @@ &saradc { vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <50000000>; + + cap-mmc-highspeed; + disable-wp; + non-removable; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + &sdio { status = "okay"; -- 2.27.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] ARM: dts: meson8b: odroidc1: enable the SDHC controller 2020-06-20 16:36 [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Martin Blumenstingl 2020-06-20 16:36 ` [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller Martin Blumenstingl 2020-06-20 16:36 ` [PATCH 2/3] ARM: dts: meson8b: ec100: enable the SDHC controller Martin Blumenstingl @ 2020-06-20 16:36 ` Martin Blumenstingl 2020-06-22 12:47 ` Anand Moon 2020-07-13 19:03 ` [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Kevin Hilman 3 siblings, 1 reply; 7+ messages in thread From: Martin Blumenstingl @ 2020-06-20 16:36 UTC (permalink / raw) To: linux-amlogic, khilman Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl Odroid-C1 has an eMMC connector where users can optionally install an eMMC module. The eMMC modules run off a 1.8V VQMMC supply which means that HS-200 mode can be used (this is the highest mode that the SDHC controller supports). Enable the SDHC controller so eMMC modules can be accessed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- arch/arm/boot/dts/meson8b-odroidc1.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index cb21ac9f517c..0c26467de4d0 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -15,6 +15,7 @@ / { aliases { serial0 = &uart_AO; mmc0 = &sd_card_slot; + mmc1 = &sdhc; }; chosen { @@ -26,6 +27,11 @@ memory { reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + leds { compatible = "gpio-leds"; blue { @@ -310,6 +316,26 @@ &saradc { vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <100000000>; + + disable-wp; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; +}; + &sdio { status = "okay"; -- 2.27.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] ARM: dts: meson8b: odroidc1: enable the SDHC controller 2020-06-20 16:36 ` [PATCH 3/3] ARM: dts: meson8b: odroidc1: " Martin Blumenstingl @ 2020-06-22 12:47 ` Anand Moon 0 siblings, 0 replies; 7+ messages in thread From: Anand Moon @ 2020-06-22 12:47 UTC (permalink / raw) To: Martin Blumenstingl Cc: linux-amlogic, Kevin Hilman, Linux Kernel, linux-arm-kernel Hi Martin, On Sat, 20 Jun 2020 at 22:08, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > Odroid-C1 has an eMMC connector where users can optionally install an > eMMC module. The eMMC modules run off a 1.8V VQMMC supply which means > that HS-200 mode can be used (this is the highest mode that the SDHC > controller supports). Enable the SDHC controller so eMMC modules can be > accessed. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Please add my Reviewed-by: Anand Moon <linux.amoon@gmail.com> -Anand > --- > arch/arm/boot/dts/meson8b-odroidc1.dts | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts > index cb21ac9f517c..0c26467de4d0 100644 > --- a/arch/arm/boot/dts/meson8b-odroidc1.dts > +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts > @@ -15,6 +15,7 @@ / { > aliases { > serial0 = &uart_AO; > mmc0 = &sd_card_slot; > + mmc1 = &sdhc; > }; > > chosen { > @@ -26,6 +27,11 @@ memory { > reg = <0x40000000 0x40000000>; > }; > > + emmc_pwrseq: emmc-pwrseq { > + compatible = "mmc-pwrseq-emmc"; > + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; > + }; > + > leds { > compatible = "gpio-leds"; > blue { > @@ -310,6 +316,26 @@ &saradc { > vref-supply = <&vcc_1v8>; > }; > > +&sdhc { > + status = "okay"; > + > + pinctrl-0 = <&sdxc_c_pins>; > + pinctrl-names = "default"; > + > + bus-width = <8>; > + max-frequency = <100000000>; > + > + disable-wp; > + cap-mmc-highspeed; > + mmc-hs200-1_8v; > + no-sdio; > + > + mmc-pwrseq = <&emmc_pwrseq>; > + > + vmmc-supply = <&vcc_3v3>; > + vqmmc-supply = <&vcc_1v8>; > +}; > + > &sdio { > status = "okay"; > > -- > 2.27.0 > > > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC 2020-06-20 16:36 [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Martin Blumenstingl ` (2 preceding siblings ...) 2020-06-20 16:36 ` [PATCH 3/3] ARM: dts: meson8b: odroidc1: " Martin Blumenstingl @ 2020-07-13 19:03 ` Kevin Hilman 3 siblings, 0 replies; 7+ messages in thread From: Kevin Hilman @ 2020-07-13 19:03 UTC (permalink / raw) To: linux-amlogic, Martin Blumenstingl; +Cc: linux-arm-kernel, linux-kernel On Sat, 20 Jun 2020 18:36:51 +0200, Martin Blumenstingl wrote: > Amlogic Meson6/8/8b/8m2 SoCs have two built-in MMC controllers: > - SDIO (which is supported on mainline for a long time now but is > limited to ~40MHz bus frequency) > - SDHC (which supports up to HS-200 modes at ~100MHz bus frequency but > for which we didn't have a driver) > > Boards with NAND flash will now be able to use the SDIO controller for > SDIO based wifi cards and the SDHC controller for the SD card slot. > Boards with eMMC, SD card and SDIO wifi can only use two out of three > MMC based devices for now until the MMC core and Meson SDIO driver gain > support for multiple "mmc-slots" per controller. > > [...] Applied, thanks! [1/3] ARM: dts: meson: add the SDHC MMC controller commit: 73106f75bf9498ff5d50f1052ad3cf03730d806d [2/3] ARM: dts: meson8b: ec100: enable the SDHC controller commit: 73501b890a6f15460613878b463319d0e0cd1632 [3/3] ARM: dts: meson8b: odroidc1: enable the SDHC controller commit: d6a3873c7be6d58914ea5584dc7875f2045d6721 Best regards, -- Kevin Hilman <khilman@baylibre.com> ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-07-13 19:03 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-06-20 16:36 [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Martin Blumenstingl 2020-06-20 16:36 ` [PATCH 1/3] ARM: dts: meson: add the SDHC MMC controller Martin Blumenstingl 2020-06-22 12:47 ` Anand Moon 2020-06-20 16:36 ` [PATCH 2/3] ARM: dts: meson8b: ec100: enable the SDHC controller Martin Blumenstingl 2020-06-20 16:36 ` [PATCH 3/3] ARM: dts: meson8b: odroidc1: " Martin Blumenstingl 2020-06-22 12:47 ` Anand Moon 2020-07-13 19:03 ` [PATCH 0/3] ARM: dts: use the SDHC MMC controller for eMMC Kevin Hilman
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