[PATCH v4 0/2] lx216x DTS updates

[PATCH v4 0/2] lx216x DTS updates

[Li Yang]

Some accumulated updates for lx2160/lx2162 SoC and boards.

v2 updates:
- Dropped duplicated "arm64: dts: lx2160a-qds: enable sata nodes"
- Removed binding patches which are applied in fsl-soc tree
- Enables optee-tz in the missing lx2162a-qds board
- added new patches "arm64: dts: lx2162a-qds: add interrupt line for RTC node"
- added new patches "arm64: dts: lx2162a-qds: enable CAN nodes"

v3 updates:
- Dropped "arm64: dts: lx2162a-qds: enable CAN nodes" merged
- Added new "fsl,lx2160ar2-pcie" compatible and use it dts update
- Changed pcie_ep node name to pcie-ep
- Added Fixes tag for "arm64: dts: lx2160a: fix scl-gpios property name"

v4 updates:
- Dropped patches from v3 that have been merged

Li Yang (1):
  arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

Xiaowei Bao (1):
  arm64: dts: lx2160a: add pcie EP mode nodes

 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 156 ++++++++++++------
 1 file changed, 108 insertions(+), 48 deletions(-)

-- 
2.37.1

[PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Li Yang]

The original dts was created based on the non-production rev1 silicon
which was only used for evaluation.  Update the PCIe nodes to align with
the different controller used in production rev2 silicon.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 96 +++++++++----------
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 6680fb2a6dc9..a7c549277dcc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1104,10 +1104,10 @@ sata3: sata@3230000 {
 		};
 
 		pcie1: pcie@3400000 {
-			compatible = "fsl,lx2160a-pcie";
-			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
-			      <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
-			reg-names = "csr_axi_slave", "config_axi_slave";
+			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+			       0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1116,26 +1116,26 @@ pcie1: pcie@3400000 {
 			#size-cells = <2>;
 			device_type = "pci";
 			dma-coherent;
-			apio-wins = <8>;
-			ppio-wins = <8>;
+			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
+				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 			status = "disabled";
 		};
 
 		pcie2: pcie@3500000 {
-			compatible = "fsl,lx2160a-pcie";
-			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
-			      <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
-			reg-names = "csr_axi_slave", "config_axi_slave";
+			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+			       0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1144,26 +1144,26 @@ pcie2: pcie@3500000 {
 			#size-cells = <2>;
 			device_type = "pci";
 			dma-coherent;
-			apio-wins = <8>;
-			ppio-wins = <8>;
+			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
+				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 			status = "disabled";
 		};
 
 		pcie3: pcie@3600000 {
-			compatible = "fsl,lx2160a-pcie";
-			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
-			      <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
-			reg-names = "csr_axi_slave", "config_axi_slave";
+			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+			       0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
 			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1172,26 +1172,26 @@ pcie3: pcie@3600000 {
 			#size-cells = <2>;
 			device_type = "pci";
 			dma-coherent;
-			apio-wins = <256>;
-			ppio-wins = <24>;
+			num-viewport = <256>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
+				  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 			status = "disabled";
 		};
 
 		pcie4: pcie@3700000 {
-			compatible = "fsl,lx2160a-pcie";
-			reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
-			      <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
-			reg-names = "csr_axi_slave", "config_axi_slave";
+			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
+			       0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1200,26 +1200,26 @@ pcie4: pcie@3700000 {
 			#size-cells = <2>;
 			device_type = "pci";
 			dma-coherent;
-			apio-wins = <8>;
-			ppio-wins = <8>;
+			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
+				  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 			status = "disabled";
 		};
 
 		pcie5: pcie@3800000 {
-			compatible = "fsl,lx2160a-pcie";
-			reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
-			      <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
-			reg-names = "csr_axi_slave", "config_axi_slave";
+			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+			reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
+			       0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
 			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1228,26 +1228,26 @@ pcie5: pcie@3800000 {
 			#size-cells = <2>;
 			device_type = "pci";
 			dma-coherent;
-			apio-wins = <256>;
-			ppio-wins = <24>;
+			num-viewport = <256>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
+				  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
-			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 			status = "disabled";
 		};
 
 		pcie6: pcie@3900000 {
-			compatible = "fsl,lx2160a-pcie";
-			reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
-			      <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
-			reg-names = "csr_axi_slave", "config_axi_slave";
+			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+			reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
+			       0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
 			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
@@ -1256,18 +1256,18 @@ pcie6: pcie@3900000 {
 			#size-cells = <2>;
 			device_type = "pci";
 			dma-coherent;
-			apio-wins = <8>;
-			ppio-wins = <8>;
+			num-viewport = <8>;
 			bus-range = <0x0 0xff>;
-			ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
+				  0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 			msi-parent = <&its>;
+			iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 					<0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 			status = "disabled";
 		};
 
-- 
2.37.1

Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Olof Johansson]

Hi,

On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
>
> The original dts was created based on the non-production rev1 silicon
> which was only used for evaluation.  Update the PCIe nodes to align with
> the different controller used in production rev2 silicon.

How can I confirm what version of silicon I have on a system?

My non-evaluation commercially purchased system (HoneyComb LX2K) has:

# cat /sys/bus/soc/devices/soc0/revision
1.0

And I will be really grumpy if this system stops working. It's what I
use to do all my maintainer work, even if that's been fairly dormant
this year.

It's overall setting off red flags to update an in-place devicetree to
a "new revision" of silicon instead of adding a new DT for said
revision. 2160A has been on the market for several years, so it just
seems odd to all of the sudden retroactively make things
non-backwards-compatible.



-Olof




-Olof

Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Olof Johansson]

On Mon, Sep 12, 2022 at 12:05 AM Olof Johansson <olof@lixom.net> wrote:
>
> Hi,
>
> On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
> >
> > The original dts was created based on the non-production rev1 silicon
> > which was only used for evaluation.  Update the PCIe nodes to align with
> > the different controller used in production rev2 silicon.
>
> How can I confirm what version of silicon I have on a system?
>
> My non-evaluation commercially purchased system (HoneyComb LX2K) has:
>
> # cat /sys/bus/soc/devices/soc0/revision
> 1.0
>
> And I will be really grumpy if this system stops working. It's what I
> use to do all my maintainer work, even if that's been fairly dormant
> this year.
>
> It's overall setting off red flags to update an in-place devicetree to
> a "new revision" of silicon instead of adding a new DT for said
> revision. 2160A has been on the market for several years, so it just
> seems odd to all of the sudden retroactively make things
> non-backwards-compatible.

Confirmed that this patch renders my HoneyComb unbootable -- PCIe doesn't probe.

Shawn, please revert, and be on the lookout for similar problematic
approaches in the future. Thanks!


-Olof

Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Russell King (Oracle)]

On Mon, Sep 12, 2022 at 11:54:06AM -0700, Olof Johansson wrote:
> On Mon, Sep 12, 2022 at 12:05 AM Olof Johansson <olof@lixom.net> wrote:
> >
> > Hi,
> >
> > On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
> > >
> > > The original dts was created based on the non-production rev1 silicon
> > > which was only used for evaluation.  Update the PCIe nodes to align with
> > > the different controller used in production rev2 silicon.
> >
> > How can I confirm what version of silicon I have on a system?
> >
> > My non-evaluation commercially purchased system (HoneyComb LX2K) has:
> >
> > # cat /sys/bus/soc/devices/soc0/revision
> > 1.0
> >
> > And I will be really grumpy if this system stops working. It's what I
> > use to do all my maintainer work, even if that's been fairly dormant
> > this year.
> >
> > It's overall setting off red flags to update an in-place devicetree to
> > a "new revision" of silicon instead of adding a new DT for said
> > revision. 2160A has been on the market for several years, so it just
> > seems odd to all of the sudden retroactively make things
> > non-backwards-compatible.
> 
> Confirmed that this patch renders my HoneyComb unbootable -- PCIe doesn't probe.
> 
> Shawn, please revert, and be on the lookout for similar problematic
> approaches in the future. Thanks!

I think you may also need to beware of the MC firmware revision - I
seem to remember reading in the changelog notes for it that NXP
dropped support in the MC firmware for the older silicon, though I
may be misremembering. It's been a while since I really looked at
the LX2160A from the point of view of maintaining or developing
anything for it.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Olof Johansson]

On Mon, Sep 12, 2022 at 1:33 PM Russell King (Oracle)
<linux@armlinux.org.uk> wrote:
>
> On Mon, Sep 12, 2022 at 11:54:06AM -0700, Olof Johansson wrote:
> > On Mon, Sep 12, 2022 at 12:05 AM Olof Johansson <olof@lixom.net> wrote:
> > >
> > > Hi,
> > >
> > > On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
> > > >
> > > > The original dts was created based on the non-production rev1 silicon
> > > > which was only used for evaluation.  Update the PCIe nodes to align with
> > > > the different controller used in production rev2 silicon.
> > >
> > > How can I confirm what version of silicon I have on a system?
> > >
> > > My non-evaluation commercially purchased system (HoneyComb LX2K) has:
> > >
> > > # cat /sys/bus/soc/devices/soc0/revision
> > > 1.0
> > >
> > > And I will be really grumpy if this system stops working. It's what I
> > > use to do all my maintainer work, even if that's been fairly dormant
> > > this year.
> > >
> > > It's overall setting off red flags to update an in-place devicetree to
> > > a "new revision" of silicon instead of adding a new DT for said
> > > revision. 2160A has been on the market for several years, so it just
> > > seems odd to all of the sudden retroactively make things
> > > non-backwards-compatible.
> >
> > Confirmed that this patch renders my HoneyComb unbootable -- PCIe doesn't probe.
> >
> > Shawn, please revert, and be on the lookout for similar problematic
> > approaches in the future. Thanks!
>
> I think you may also need to beware of the MC firmware revision - I
> seem to remember reading in the changelog notes for it that NXP
> dropped support in the MC firmware for the older silicon, though I
> may be misremembering. It's been a while since I really looked at
> the LX2160A from the point of view of maintaining or developing
> anything for it.

Yeah, and if anything this speaks against trying to update u-boot/EFI
on it to something newer, bugs in firmware or not.


-Olof

RE: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Leo Li]

> -----Original Message-----
> From: Olof Johansson <olof@lixom.net>
> Sent: Monday, September 12, 2022 2:05 AM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: shawnguo@kernel.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Z.Q. Hou <zhiqiang.hou@nxp.com>
> Subject: Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match
> rev2 silicon
> 
> Hi,
> 
> On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
> >
> > The original dts was created based on the non-production rev1 silicon
> > which was only used for evaluation.  Update the PCIe nodes to align
> > with the different controller used in production rev2 silicon.
> 
> How can I confirm what version of silicon I have on a system?
> 
> My non-evaluation commercially purchased system (HoneyComb LX2K) has:
> 
> # cat /sys/bus/soc/devices/soc0/revision
> 1.0

This is different from the information I got.  If there is still active Rev1.0 system in use, I would agree that we probably need to create a new device tree for the rev2 silicon.  Thanks for the information.

> 
> And I will be really grumpy if this system stops working. It's what I use to do
> all my maintainer work, even if that's been fairly dormant this year.
> 
> It's overall setting off red flags to update an in-place devicetree to a "new
> revision" of silicon instead of adding a new DT for said revision. 2160A has
> been on the market for several years, so it just seems odd to all of the
> sudden retroactively make things non-backwards-compatible.
> 
> 
> 
> -Olof
> 
> 
> 
> 
> -Olof

Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Shawn Guo]

On Mon, Sep 12, 2022 at 08:25:39PM +0000, Leo Li wrote:
> 
> 
> > -----Original Message-----
> > From: Olof Johansson <olof@lixom.net>
> > Sent: Monday, September 12, 2022 2:05 AM
> > To: Leo Li <leoyang.li@nxp.com>
> > Cc: shawnguo@kernel.org; devicetree@vger.kernel.org;
> > robh+dt@kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; Z.Q. Hou <zhiqiang.hou@nxp.com>
> > Subject: Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match
> > rev2 silicon
> > 
> > Hi,
> > 
> > On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
> > >
> > > The original dts was created based on the non-production rev1 silicon
> > > which was only used for evaluation.  Update the PCIe nodes to align
> > > with the different controller used in production rev2 silicon.
> > 
> > How can I confirm what version of silicon I have on a system?
> > 
> > My non-evaluation commercially purchased system (HoneyComb LX2K) has:
> > 
> > # cat /sys/bus/soc/devices/soc0/revision
> > 1.0
> 
> This is different from the information I got.  If there is still active Rev1.0 system in use, I would agree that we probably need to create a new device tree for the rev2 silicon.  Thanks for the information.

Dropped both patches.

Shawn

RE: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon

[Leo Li]

> -----Original Message-----
> From: Olof Johansson <olof@lixom.net>
> Sent: Monday, September 12, 2022 2:05 AM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: shawnguo@kernel.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Z.Q. Hou <zhiqiang.hou@nxp.com>
> Subject: Re: [PATCH v4 1/2] arm64: dts: lx2160a: update PCIe nodes to match
> rev2 silicon
> 
> Hi,
> 
> On Wed, Aug 17, 2022 at 1:26 PM Li Yang <leoyang.li@nxp.com> wrote:
> >
> > The original dts was created based on the non-production rev1 silicon
> > which was only used for evaluation.  Update the PCIe nodes to align
> > with the different controller used in production rev2 silicon.
> 
> How can I confirm what version of silicon I have on a system?
> 
> My non-evaluation commercially purchased system (HoneyComb LX2K) has:
> 
> # cat /sys/bus/soc/devices/soc0/revision
> 1.0
> 
> And I will be really grumpy if this system stops working. It's what I use to do
> all my maintainer work, even if that's been fairly dormant this year.
> 
> It's overall setting off red flags to update an in-place devicetree to a "new
> revision" of silicon instead of adding a new DT for said revision. 2160A has
> been on the market for several years, so it just seems odd to all of the
> sudden retroactively make things non-backwards-compatible.

Some more background information.  The Rev1 silicon was only shipped for a very short period of time(for evaluation purpose only from what I heard) before the rev2 was out to fix some critical hardware issues.  And we have recommended all customers to switch to Rev2 to avoid potential issues in Rev1.  This non-backwards-compatible change is to avoid the potential confusion between rev1 and rev2 on assumption that there is no remaining users of Rev1 now, which seems to be not the case according to your response.

Regards,
Leo

[PATCH v4 2/2] arm64: dts: lx2160a: add pcie EP mode nodes

[Li Yang]

From: Xiaowei Bao <xiaowei.bao@nxp.com>

The LX2160A PCIe EP mode nodes based on controller used on lx2160a rev2.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a7c549277dcc..97786b454ec7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1131,6 +1131,16 @@ pcie1: pcie@3400000 {
 			status = "disabled";
 		};
 
+		pcie_ep1: pcie-ep@3400000 {
+			compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03400000 0x0 0x00100000
+			       0x80 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ob-windows = <8>;
+			num-ib-windows = <8>;
+			status = "disabled";
+		};
+
 		pcie2: pcie@3500000 {
 			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
@@ -1159,6 +1169,16 @@ pcie2: pcie@3500000 {
 			status = "disabled";
 		};
 
+		pcie_ep2: pcie-ep@3500000 {
+			compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03500000 0x0 0x00100000
+			       0x88 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ob-windows = <8>;
+			num-ib-windows = <8>;
+			status = "disabled";
+		};
+
 		pcie3: pcie@3600000 {
 			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
@@ -1187,6 +1207,16 @@ pcie3: pcie@3600000 {
 			status = "disabled";
 		};
 
+		pcie_ep3: pcie-ep@3600000 {
+			compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03600000 0x0 0x00100000
+			       0x90 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ob-windows = <256>;
+			num-ib-windows = <24>;
+			status = "disabled";
+		};
+
 		pcie4: pcie@3700000 {
 			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
 			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
@@ -1215,6 +1245,16 @@ pcie4: pcie@3700000 {
 			status = "disabled";
 		};
 
+		pcie_ep4: pcie-ep@3700000 {
+			compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03700000 0x0 0x00100000
+			       0x98 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ob-windows = <8>;
+			num-ib-windows = <8>;
+			status = "disabled";
+		};
+
 		pcie5: pcie@3800000 {
 			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
 			reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
@@ -1243,6 +1283,16 @@ pcie5: pcie@3800000 {
 			status = "disabled";
 		};
 
+		pcie_ep5: pcie-ep@3800000 {
+			compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03800000 0x0 0x00100000
+			       0xa0 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ob-windows = <256>;
+			num-ib-windows = <24>;
+			status = "disabled";
+		};
+
 		pcie6: pcie@3900000 {
 			compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
 			reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
@@ -1271,6 +1321,16 @@ pcie6: pcie@3900000 {
 			status = "disabled";
 		};
 
+		pcie_ep6: pcie-ep@3900000 {
+			compatible = "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep";
+			reg = <0x00 0x03900000 0x0 0x00100000
+			       0xa8 0x00000000 0x8 0x00000000>;
+			reg-names = "regs", "addr_space";
+			num-ob-windows = <8>;
+			num-ib-windows = <8>;
+			status = "disabled";
+		};
+
 		smmu: iommu@5000000 {
 			compatible = "arm,mmu-500";
 			reg = <0 0x5000000 0 0x800000>;
-- 
2.37.1

Re: [PATCH v4 0/2] lx216x DTS updates

[Shawn Guo]

On Wed, Aug 17, 2022 at 03:25:36PM -0500, Li Yang wrote:
> Some accumulated updates for lx2160/lx2162 SoC and boards.
> 
> v2 updates:
> - Dropped duplicated "arm64: dts: lx2160a-qds: enable sata nodes"
> - Removed binding patches which are applied in fsl-soc tree
> - Enables optee-tz in the missing lx2162a-qds board
> - added new patches "arm64: dts: lx2162a-qds: add interrupt line for RTC node"
> - added new patches "arm64: dts: lx2162a-qds: enable CAN nodes"
> 
> v3 updates:
> - Dropped "arm64: dts: lx2162a-qds: enable CAN nodes" merged
> - Added new "fsl,lx2160ar2-pcie" compatible and use it dts update
> - Changed pcie_ep node name to pcie-ep
> - Added Fixes tag for "arm64: dts: lx2160a: fix scl-gpios property name"
> 
> v4 updates:
> - Dropped patches from v3 that have been merged
> 
> Li Yang (1):
>   arm64: dts: lx2160a: update PCIe nodes to match rev2 silicon
> 
> Xiaowei Bao (1):
>   arm64: dts: lx2160a: add pcie EP mode nodes

Applied both, thanks!