* [RESEND PATCH 0/2] mtd: spi-nor: add entry for mt35xu512aba flash @ 2018-09-19 4:50 Yogesh Gaur 2018-09-19 4:50 ` [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash Yogesh Gaur 2018-09-19 4:50 ` [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur 0 siblings, 2 replies; 8+ messages in thread From: Yogesh Gaur @ 2018-09-19 4:50 UTC (permalink / raw) To: linux-mtd, linux-spi Cc: marek.vasut, cyrille.pitchen, boris.brezillon, computersforpeace, frieder.schrempf, linux-kernel, Yogesh Gaur Add MFR_ID information, 0x002C, related to the Micron flash. Currently, MFR_ID 0x0020 is being specified as Micron flash ID but these are actually CFI ID of STMicro flashes. Rename SNOR_MFR_MICRON to SNOR_MFR_ST and add entry for SNOR_MFR_MICRON having CFI ID value of Micron flash. Add entry of mt35xu512aba flash in spi_nor_ids table. Yogesh Gaur (2): mtd: spi-nor: add macros related to MICRON flash mtd: spi-nor: add entry for mt35xu512aba flash drivers/mtd/spi-nor/spi-nor.c | 12 +++++++++--- include/linux/mtd/cfi.h | 1 + include/linux/mtd/spi-nor.h | 3 ++- 3 files changed, 12 insertions(+), 4 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash 2018-09-19 4:50 [RESEND PATCH 0/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur @ 2018-09-19 4:50 ` Yogesh Gaur 2018-09-19 16:30 ` Tudor Ambarus 2018-10-09 4:01 ` Tudor Ambarus 2018-09-19 4:50 ` [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur 1 sibling, 2 replies; 8+ messages in thread From: Yogesh Gaur @ 2018-09-19 4:50 UTC (permalink / raw) To: linux-mtd, linux-spi Cc: marek.vasut, cyrille.pitchen, boris.brezillon, computersforpeace, frieder.schrempf, linux-kernel, Yogesh Gaur Some MICRON related macros in spi-nor domain were ST. Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. Added entry of MFR Id for Micron flashes, 0x002C. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> --- drivers/mtd/spi-nor/spi-nor.c | 9 ++++++--- include/linux/mtd/cfi.h | 1 + include/linux/mtd/spi-nor.h | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index f028277..33a55bc 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, u8 cmd; switch (JEDEC_MFR(info)) { + case SNOR_MFR_ST: case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; @@ -1096,7 +1097,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, - /* Micron */ + /* Micron <--> ST Micro */ { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, @@ -2502,6 +2503,7 @@ static int spi_nor_init_params(struct spi_nor *nor, params->quad_enable = macronix_quad_enable; break; + case SNOR_MFR_ST: case SNOR_MFR_MICRON: break; @@ -2876,8 +2878,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, mtd->_resume = spi_nor_resume; /* NOR protection support for STmicro/Micron chips and similar */ - if (JEDEC_MFR(info) == SNOR_MFR_MICRON || - info->flags & SPI_NOR_HAS_LOCK) { + if (JEDEC_MFR(info) == SNOR_MFR_ST || + JEDEC_MFR(info) == SNOR_MFR_MICRON || + info->flags & SPI_NOR_HAS_LOCK) { nor->flash_lock = stm_lock; nor->flash_unlock = stm_unlock; nor->flash_is_locked = stm_is_locked; diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 9b57a9b..cbf7716 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -377,6 +377,7 @@ struct cfi_fixup { #define CFI_MFR_SHARP 0x00B0 #define CFI_MFR_SST 0x00BF #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ +#define CFI_MFR_MICRON 0x002C /* Micron */ #define CFI_MFR_TOSHIBA 0x0098 #define CFI_MFR_WINBOND 0x00DA diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index c922e97..f43bfc5 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -23,7 +23,8 @@ #define SNOR_MFR_ATMEL CFI_MFR_ATMEL #define SNOR_MFR_GIGADEVICE 0xc8 #define SNOR_MFR_INTEL CFI_MFR_INTEL -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash 2018-09-19 4:50 ` [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash Yogesh Gaur @ 2018-09-19 16:30 ` Tudor Ambarus 2018-09-20 4:31 ` Yogesh Narayan Gaur 2018-10-09 4:01 ` Tudor Ambarus 1 sibling, 1 reply; 8+ messages in thread From: Tudor Ambarus @ 2018-09-19 16:30 UTC (permalink / raw) To: Yogesh Gaur, linux-mtd, linux-spi Cc: boris.brezillon, linux-kernel, marek.vasut, frieder.schrempf, cyrille.pitchen, computersforpeace Hi, On 09/19/2018 07:50 AM, Yogesh Gaur wrote: > Some MICRON related macros in spi-nor domain were ST. > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. > > Added entry of MFR Id for Micron flashes, 0x002C. > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > --- > drivers/mtd/spi-nor/spi-nor.c | 9 ++++++--- > include/linux/mtd/cfi.h | 1 + > include/linux/mtd/spi-nor.h | 3 ++- > 3 files changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index f028277..33a55bc 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, > u8 cmd; > > switch (JEDEC_MFR(info)) { > + case SNOR_MFR_ST: We should mark switch cases where we are expecting to fall through, so that we will be prepared when enabling -Wimplicit-fallthrough. > case SNOR_MFR_MICRON: > /* Some Micron need WREN command; all will accept it */ > need_wren = true; > @@ -1096,7 +1097,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, > > - /* Micron */ > + /* Micron <--> ST Micro */ > { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, > { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, > @@ -2502,6 +2503,7 @@ static int spi_nor_init_params(struct spi_nor *nor, > params->quad_enable = macronix_quad_enable; > break; > > + case SNOR_MFR_ST: > case SNOR_MFR_MICRON: > break; > > @@ -2876,8 +2878,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, > mtd->_resume = spi_nor_resume; > > /* NOR protection support for STmicro/Micron chips and similar */ > - if (JEDEC_MFR(info) == SNOR_MFR_MICRON || > - info->flags & SPI_NOR_HAS_LOCK) { > + if (JEDEC_MFR(info) == SNOR_MFR_ST || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > + info->flags & SPI_NOR_HAS_LOCK) { > nor->flash_lock = stm_lock; > nor->flash_unlock = stm_unlock; > nor->flash_is_locked = stm_is_locked; > diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h > index 9b57a9b..cbf7716 100644 > --- a/include/linux/mtd/cfi.h > +++ b/include/linux/mtd/cfi.h > @@ -377,6 +377,7 @@ struct cfi_fixup { > #define CFI_MFR_SHARP 0x00B0 > #define CFI_MFR_SST 0x00BF > #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ > +#define CFI_MFR_MICRON 0x002C /* Micron */ Can you point us to a datasheet to verify the id? Best, ta > #define CFI_MFR_TOSHIBA 0x0098 > #define CFI_MFR_WINBOND 0x00DA > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index c922e97..f43bfc5 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -23,7 +23,8 @@ > #define SNOR_MFR_ATMEL CFI_MFR_ATMEL > #define SNOR_MFR_GIGADEVICE 0xc8 > #define SNOR_MFR_INTEL CFI_MFR_INTEL > -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ > +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ > +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ > #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX > #define SNOR_MFR_SPANSION CFI_MFR_AMD > #define SNOR_MFR_SST CFI_MFR_SST > ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash 2018-09-19 16:30 ` Tudor Ambarus @ 2018-09-20 4:31 ` Yogesh Narayan Gaur 2018-09-20 9:20 ` Tudor Ambarus 0 siblings, 1 reply; 8+ messages in thread From: Yogesh Narayan Gaur @ 2018-09-20 4:31 UTC (permalink / raw) To: Tudor Ambarus, linux-mtd, linux-spi Cc: boris.brezillon, linux-kernel, marek.vasut, frieder.schrempf, cyrille.pitchen, computersforpeace Hi Tudor, > -----Original Message----- > From: Tudor Ambarus [mailto:tudor.ambarus@microchip.com] > Sent: Wednesday, September 19, 2018 10:00 PM > To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; linux- > mtd@lists.infradead.org; linux-spi@vger.kernel.org > Cc: boris.brezillon@bootlin.com; linux-kernel@vger.kernel.org; > marek.vasut@gmail.com; frieder.schrempf@exceet.de; > cyrille.pitchen@wedev4u.fr; computersforpeace@gmail.com > Subject: Re: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON > flash > > Hi, > > On 09/19/2018 07:50 AM, Yogesh Gaur wrote: > > Some MICRON related macros in spi-nor domain were ST. > > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. > > > > Added entry of MFR Id for Micron flashes, 0x002C. > > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > > --- > > drivers/mtd/spi-nor/spi-nor.c | 9 ++++++--- > > include/linux/mtd/cfi.h | 1 + > > include/linux/mtd/spi-nor.h | 3 ++- > > 3 files changed, 9 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/mtd/spi-nor/spi-nor.c > > b/drivers/mtd/spi-nor/spi-nor.c index f028277..33a55bc 100644 > > --- a/drivers/mtd/spi-nor/spi-nor.c > > +++ b/drivers/mtd/spi-nor/spi-nor.c > > @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const > struct flash_info *info, > > u8 cmd; > > > > switch (JEDEC_MFR(info)) { > > + case SNOR_MFR_ST: > > We should mark switch cases where we are expecting to fall through, so that we > will be prepared when enabling -Wimplicit-fallthrough. Please explain more, not able to get this comment. Sorry for ignorance. > > > case SNOR_MFR_MICRON: > > /* Some Micron need WREN command; all will accept it */ > > need_wren = true; > > @@ -1096,7 +1097,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, > loff_t ofs, uint64_t len) > > { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, > > SPI_NOR_QUAD_READ) }, > > > > - /* Micron */ > > + /* Micron <--> ST Micro */ > > { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | > SPI_NOR_QUAD_READ) }, > > { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, > SPI_NOR_QUAD_READ) }, > > { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, > SPI_NOR_QUAD_READ) }, > > @@ -2502,6 +2503,7 @@ static int spi_nor_init_params(struct spi_nor *nor, > > params->quad_enable = macronix_quad_enable; > > break; > > > > + case SNOR_MFR_ST: > > case SNOR_MFR_MICRON: > > break; > > > > @@ -2876,8 +2878,9 @@ int spi_nor_scan(struct spi_nor *nor, const char > *name, > > mtd->_resume = spi_nor_resume; > > > > /* NOR protection support for STmicro/Micron chips and similar */ > > - if (JEDEC_MFR(info) == SNOR_MFR_MICRON || > > - info->flags & SPI_NOR_HAS_LOCK) { > > + if (JEDEC_MFR(info) == SNOR_MFR_ST || > > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > > + info->flags & SPI_NOR_HAS_LOCK) { > > nor->flash_lock = stm_lock; > > nor->flash_unlock = stm_unlock; > > nor->flash_is_locked = stm_is_locked; diff --git > > a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index > > 9b57a9b..cbf7716 100644 > > --- a/include/linux/mtd/cfi.h > > +++ b/include/linux/mtd/cfi.h > > @@ -377,6 +377,7 @@ struct cfi_fixup { > > #define CFI_MFR_SHARP 0x00B0 > > #define CFI_MFR_SST 0x00BF > > #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ > > +#define CFI_MFR_MICRON 0x002C /* Micron */ > > Can you point us to a datasheet to verify the id? > Currently data sheet of this flash is under NDA, I have asked Micron guys to provide the public link of this data sheet. -- Regards Yogesh Gaur. > Best, > ta > > > #define CFI_MFR_TOSHIBA 0x0098 > > #define CFI_MFR_WINBOND 0x00DA > > > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > > index c922e97..f43bfc5 100644 > > --- a/include/linux/mtd/spi-nor.h > > +++ b/include/linux/mtd/spi-nor.h > > @@ -23,7 +23,8 @@ > > #define SNOR_MFR_ATMEL CFI_MFR_ATMEL > > #define SNOR_MFR_GIGADEVICE 0xc8 > > #define SNOR_MFR_INTEL CFI_MFR_INTEL > > -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron > */ > > +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ > > +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ > > #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX > > #define SNOR_MFR_SPANSION CFI_MFR_AMD > > #define SNOR_MFR_SST CFI_MFR_SST > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash 2018-09-20 4:31 ` Yogesh Narayan Gaur @ 2018-09-20 9:20 ` Tudor Ambarus 0 siblings, 0 replies; 8+ messages in thread From: Tudor Ambarus @ 2018-09-20 9:20 UTC (permalink / raw) To: Yogesh Narayan Gaur, linux-mtd, linux-spi Cc: boris.brezillon, linux-kernel, marek.vasut, frieder.schrempf, cyrille.pitchen, computersforpeace >>> diff --git a/drivers/mtd/spi-nor/spi-nor.c >>> @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const >> struct flash_info *info, >>> u8 cmd; >>> >>> switch (JEDEC_MFR(info)) { >>> + case SNOR_MFR_ST: >> >> We should mark switch cases where we are expecting to fall through, so that we >> will be prepared when enabling -Wimplicit-fallthrough. > > Please explain more, not able to get this comment. Sorry for ignorance. > >> >>> case SNOR_MFR_MICRON: >>> /* Some Micron need WREN command; all will accept it */ >>> need_wren = true; We can ignore my comment, it's not in the scope of this patch. I wrongly suggested to do this: case SNOR_MFR_ST: /* fall through */ case SNOR_MFR_MICRON: in order to suppress the -Wimplicit-fallthrough warning that I thought it will appear on gcc 7. The suggestion is wrong because the warning is not emitted for empty case bodies, so it's not needed here. However, when compiling with gcc 7 and -Wimplicit-fallthrough the following can be seen: drivers/mtd/spi-nor/spi-nor.c: In function ‘set_4byte’: drivers/mtd/spi-nor/spi-nor.c:290:13: warning: this statement may fall through [-Wimplicit-fallthrough=] need_wren = true; ~~~~~~~~~~^~~~~~ drivers/mtd/spi-nor/spi-nor.c:291:2: note: here case SNOR_MFR_MACRONIX: ^~~~ We should add a /* fall through */ comment after setting need_wren = true;, but it's not in the scope of this patch. Cheers, ta ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash 2018-09-19 4:50 ` [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash Yogesh Gaur 2018-09-19 16:30 ` Tudor Ambarus @ 2018-10-09 4:01 ` Tudor Ambarus 1 sibling, 0 replies; 8+ messages in thread From: Tudor Ambarus @ 2018-10-09 4:01 UTC (permalink / raw) To: Yogesh Gaur, linux-mtd, linux-spi Cc: boris.brezillon, linux-kernel, marek.vasut, frieder.schrempf, cyrille.pitchen, computersforpeace On 09/19/2018 07:50 AM, Yogesh Gaur wrote: > Some MICRON related macros in spi-nor domain were ST. > Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. > > Added entry of MFR Id for Micron flashes, 0x002C. > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > drivers/mtd/spi-nor/spi-nor.c | 9 ++++++--- > include/linux/mtd/cfi.h | 1 + > include/linux/mtd/spi-nor.h | 3 ++- > 3 files changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index f028277..33a55bc 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -271,6 +271,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, > u8 cmd; > > switch (JEDEC_MFR(info)) { > + case SNOR_MFR_ST: > case SNOR_MFR_MICRON: > /* Some Micron need WREN command; all will accept it */ > need_wren = true; > @@ -1096,7 +1097,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, > > - /* Micron */ > + /* Micron <--> ST Micro */ > { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, > { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, > @@ -2502,6 +2503,7 @@ static int spi_nor_init_params(struct spi_nor *nor, > params->quad_enable = macronix_quad_enable; > break; > > + case SNOR_MFR_ST: > case SNOR_MFR_MICRON: > break; > > @@ -2876,8 +2878,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, > mtd->_resume = spi_nor_resume; > > /* NOR protection support for STmicro/Micron chips and similar */ > - if (JEDEC_MFR(info) == SNOR_MFR_MICRON || > - info->flags & SPI_NOR_HAS_LOCK) { > + if (JEDEC_MFR(info) == SNOR_MFR_ST || > + JEDEC_MFR(info) == SNOR_MFR_MICRON || > + info->flags & SPI_NOR_HAS_LOCK) { > nor->flash_lock = stm_lock; > nor->flash_unlock = stm_unlock; > nor->flash_is_locked = stm_is_locked; > diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h > index 9b57a9b..cbf7716 100644 > --- a/include/linux/mtd/cfi.h > +++ b/include/linux/mtd/cfi.h > @@ -377,6 +377,7 @@ struct cfi_fixup { > #define CFI_MFR_SHARP 0x00B0 > #define CFI_MFR_SST 0x00BF > #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ > +#define CFI_MFR_MICRON 0x002C /* Micron */ > #define CFI_MFR_TOSHIBA 0x0098 > #define CFI_MFR_WINBOND 0x00DA > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index c922e97..f43bfc5 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -23,7 +23,8 @@ > #define SNOR_MFR_ATMEL CFI_MFR_ATMEL > #define SNOR_MFR_GIGADEVICE 0xc8 > #define SNOR_MFR_INTEL CFI_MFR_INTEL > -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ > +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ > +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ > #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX > #define SNOR_MFR_SPANSION CFI_MFR_AMD > #define SNOR_MFR_SST CFI_MFR_SST > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash 2018-09-19 4:50 [RESEND PATCH 0/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur 2018-09-19 4:50 ` [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash Yogesh Gaur @ 2018-09-19 4:50 ` Yogesh Gaur 2018-09-19 16:23 ` Tudor Ambarus 1 sibling, 1 reply; 8+ messages in thread From: Yogesh Gaur @ 2018-09-19 4:50 UTC (permalink / raw) To: linux-mtd, linux-spi Cc: marek.vasut, cyrille.pitchen, boris.brezillon, computersforpeace, frieder.schrempf, linux-kernel, Yogesh Gaur Add entry for mt35xu512aba Micron NOR flash. This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> --- drivers/mtd/spi-nor/spi-nor.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 33a55bc..6042df8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1113,6 +1113,9 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + /* Micron */ + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) }, + /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash 2018-09-19 4:50 ` [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur @ 2018-09-19 16:23 ` Tudor Ambarus 0 siblings, 0 replies; 8+ messages in thread From: Tudor Ambarus @ 2018-09-19 16:23 UTC (permalink / raw) To: Yogesh Gaur, linux-mtd, linux-spi Cc: boris.brezillon, linux-kernel, marek.vasut, frieder.schrempf, cyrille.pitchen, computersforpeace Hi, On 09/19/2018 07:50 AM, Yogesh Gaur wrote: > Add entry for mt35xu512aba Micron NOR flash. > This flash is having uniform sector erase size of 128KB, have > support of FSR(flag status register), flash size is 64MB and > supports 4-byte commands. > Seems that the datasheet for mt35xu512aba is not public, I couldn't verify your statement. > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> > --- > drivers/mtd/spi-nor/spi-nor.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 33a55bc..6042df8 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1113,6 +1113,9 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > > + /* Micron */ > + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) }, nitpick on style: Brian picked a style that seems reasonable for splitting up the flags, see 9648388fc7737365be7a8092e77df78ccc2cd1a4. Best, ta ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-10-09 4:01 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-09-19 4:50 [RESEND PATCH 0/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur 2018-09-19 4:50 ` [RESEND PATCH 1/2] mtd: spi-nor: add macros related to MICRON flash Yogesh Gaur 2018-09-19 16:30 ` Tudor Ambarus 2018-09-20 4:31 ` Yogesh Narayan Gaur 2018-09-20 9:20 ` Tudor Ambarus 2018-10-09 4:01 ` Tudor Ambarus 2018-09-19 4:50 ` [RESEND PATCH 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Yogesh Gaur 2018-09-19 16:23 ` Tudor Ambarus
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